Staging: brcm80211: phy: s/uint8/u8/

Replace uint8 with u8, the correct kernel type to be using here.

Cc: Brett Rudley <brudley@broadcom.com>
Cc: Henry Ptasinski <henryp@broadcom.com>
Cc: Nohee Ko <noheek@broadcom.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

drivers/staging/brcm80211/phy/wlc_phy_hal.h

@@ -94,28 +94,28 @@
 #define WLC_NUM_RATES_MCS_3_STREAM  8
 #define WLC_NUM_RATES_MCS_4_STREAM  8
 typedef struct txpwr_limits {
-	uint8 cck[WLC_NUM_RATES_CCK];
-	uint8 ofdm[WLC_NUM_RATES_OFDM];
+	u8 cck[WLC_NUM_RATES_CCK];
+	u8 ofdm[WLC_NUM_RATES_OFDM];
 
-	uint8 ofdm_cdd[WLC_NUM_RATES_OFDM];
+	u8 ofdm_cdd[WLC_NUM_RATES_OFDM];
 
-	uint8 ofdm_40_siso[WLC_NUM_RATES_OFDM];
-	uint8 ofdm_40_cdd[WLC_NUM_RATES_OFDM];
+	u8 ofdm_40_siso[WLC_NUM_RATES_OFDM];
+	u8 ofdm_40_cdd[WLC_NUM_RATES_OFDM];
 
-	uint8 mcs_20_siso[WLC_NUM_RATES_MCS_1_STREAM];
-	uint8 mcs_20_cdd[WLC_NUM_RATES_MCS_1_STREAM];
-	uint8 mcs_20_stbc[WLC_NUM_RATES_MCS_1_STREAM];
-	uint8 mcs_20_mimo[WLC_NUM_RATES_MCS_2_STREAM];
+	u8 mcs_20_siso[WLC_NUM_RATES_MCS_1_STREAM];
+	u8 mcs_20_cdd[WLC_NUM_RATES_MCS_1_STREAM];
+	u8 mcs_20_stbc[WLC_NUM_RATES_MCS_1_STREAM];
+	u8 mcs_20_mimo[WLC_NUM_RATES_MCS_2_STREAM];
 
-	uint8 mcs_40_siso[WLC_NUM_RATES_MCS_1_STREAM];
-	uint8 mcs_40_cdd[WLC_NUM_RATES_MCS_1_STREAM];
-	uint8 mcs_40_stbc[WLC_NUM_RATES_MCS_1_STREAM];
-	uint8 mcs_40_mimo[WLC_NUM_RATES_MCS_2_STREAM];
-	uint8 mcs32;
+	u8 mcs_40_siso[WLC_NUM_RATES_MCS_1_STREAM];
+	u8 mcs_40_cdd[WLC_NUM_RATES_MCS_1_STREAM];
+	u8 mcs_40_stbc[WLC_NUM_RATES_MCS_1_STREAM];
+	u8 mcs_40_mimo[WLC_NUM_RATES_MCS_2_STREAM];
+	u8 mcs32;
 } txpwr_limits_t;
 
 typedef struct {
-	uint8 vec[MAXCHANNEL / NBBY];
+	u8 vec[MAXCHANNEL / NBBY];
 } chanvec_t;
 
 struct rpc_info;
@@ -201,9 +201,9 @@ extern void wlc_phy_chanspec_band_validch(wlc_phy_t *ppi, uint band,
 extern chanspec_t wlc_phy_chanspec_band_firstch(wlc_phy_t *ppi, uint band);
 
 extern void wlc_phy_txpower_sromlimit(wlc_phy_t *ppi, uint chan,
-				      uint8 *_min_, uint8 *_max_, int rate);
+				      u8 *_min_, u8 *_max_, int rate);
 extern void wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan,
-					      uint8 *_max_, uint8 *_min_);
+					      u8 *_max_, u8 *_min_);
 extern void wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint band, int32 *,
 					    int32 *, uint32 *);
 extern void wlc_phy_txpower_limit_set(wlc_phy_t *ppi, struct txpwr_limits *,
@@ -213,39 +213,39 @@ extern int wlc_phy_txpower_set(wlc_phy_t *ppi, uint qdbm, bool override);
 extern void wlc_phy_txpower_target_set(wlc_phy_t *ppi, struct txpwr_limits *);
 extern bool wlc_phy_txpower_hw_ctrl_get(wlc_phy_t *ppi);
 extern void wlc_phy_txpower_hw_ctrl_set(wlc_phy_t *ppi, bool hwpwrctrl);
-extern uint8 wlc_phy_txpower_get_target_min(wlc_phy_t *ppi);
-extern uint8 wlc_phy_txpower_get_target_max(wlc_phy_t *ppi);
+extern u8 wlc_phy_txpower_get_target_min(wlc_phy_t *ppi);
+extern u8 wlc_phy_txpower_get_target_max(wlc_phy_t *ppi);
 extern bool wlc_phy_txpower_ipa_ison(wlc_phy_t *pih);
 
-extern void wlc_phy_stf_chain_init(wlc_phy_t *pih, uint8 txchain,
-				   uint8 rxchain);
-extern void wlc_phy_stf_chain_set(wlc_phy_t *pih, uint8 txchain,
-				  uint8 rxchain);
-extern void wlc_phy_stf_chain_get(wlc_phy_t *pih, uint8 *txchain,
-				  uint8 *rxchain);
-extern uint8 wlc_phy_stf_chain_active_get(wlc_phy_t *pih);
+extern void wlc_phy_stf_chain_init(wlc_phy_t *pih, u8 txchain,
+				   u8 rxchain);
+extern void wlc_phy_stf_chain_set(wlc_phy_t *pih, u8 txchain,
+				  u8 rxchain);
+extern void wlc_phy_stf_chain_get(wlc_phy_t *pih, u8 *txchain,
+				  u8 *rxchain);
+extern u8 wlc_phy_stf_chain_active_get(wlc_phy_t *pih);
 extern int8 wlc_phy_stf_ssmode_get(wlc_phy_t *pih, chanspec_t chanspec);
 extern void wlc_phy_ldpc_override_set(wlc_phy_t *ppi, bool val);
 
-extern void wlc_phy_cal_perical(wlc_phy_t *ppi, uint8 reason);
+extern void wlc_phy_cal_perical(wlc_phy_t *ppi, u8 reason);
 extern void wlc_phy_noise_sample_request_external(wlc_phy_t *ppi);
 extern void wlc_phy_edcrs_lock(wlc_phy_t *pih, bool lock);
 extern void wlc_phy_cal_papd_recal(wlc_phy_t *ppi);
 
-extern void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, uint8 val);
-extern bool wlc_phy_ant_rxdiv_get(wlc_phy_t *ppi, uint8 *pval);
+extern void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val);
+extern bool wlc_phy_ant_rxdiv_get(wlc_phy_t *ppi, u8 *pval);
 extern void wlc_phy_clear_tssi(wlc_phy_t *ppi);
 extern void wlc_phy_hold_upd(wlc_phy_t *ppi, mbool id, bool val);
 extern void wlc_phy_mute_upd(wlc_phy_t *ppi, bool val, mbool flags);
 
-extern void wlc_phy_antsel_type_set(wlc_phy_t *ppi, uint8 antsel_type);
+extern void wlc_phy_antsel_type_set(wlc_phy_t *ppi, u8 antsel_type);
 
 extern void wlc_phy_txpower_get_current(wlc_phy_t *ppi, tx_power_t *power,
 					uint channel);
 
 extern void wlc_phy_initcal_enable(wlc_phy_t *pih, bool initcal);
 extern bool wlc_phy_test_ison(wlc_phy_t *ppi);
-extern void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, uint8 txpwr_percent);
+extern void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent);
 extern void wlc_phy_ofdm_rateset_war(wlc_phy_t *pih, bool war);
 extern void wlc_phy_bf_preempt_enable(wlc_phy_t *pih, bool bf_preempt);
 extern void wlc_phy_machwcap_set(wlc_phy_t *ppi, uint32 machwcap);
@@ -255,9 +255,9 @@ extern void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end);
 extern void wlc_phy_freqtrack_start(wlc_phy_t *ppi);
 extern void wlc_phy_freqtrack_end(wlc_phy_t *ppi);
 
-extern const uint8 *wlc_phy_get_ofdm_rate_lookup(void);
+extern const u8 *wlc_phy_get_ofdm_rate_lookup(void);
 
 extern int8 wlc_phy_get_tx_power_offset_by_mcs(wlc_phy_t *ppi,
-					       uint8 mcs_offset);
-extern int8 wlc_phy_get_tx_power_offset(wlc_phy_t *ppi, uint8 tbl_offset);
+					       u8 mcs_offset);
+extern int8 wlc_phy_get_tx_power_offset(wlc_phy_t *ppi, u8 tbl_offset);
 #endif				/* _wlc_phy_h_ */

drivers/staging/brcm80211/phy/wlc_phy_lcn.h

@@ -21,42 +21,42 @@
 
 struct phy_info_lcnphy {
 	int lcnphy_txrf_sp_9_override;
-	uint8 lcnphy_full_cal_channel;
-	uint8 lcnphy_cal_counter;
+	u8 lcnphy_full_cal_channel;
+	u8 lcnphy_cal_counter;
 	uint16 lcnphy_cal_temper;
 	bool lcnphy_recal;
 
-	uint8 lcnphy_rc_cap;
+	u8 lcnphy_rc_cap;
 	uint32 lcnphy_mcs20_po;
 
-	uint8 lcnphy_tr_isolation_mid;
-	uint8 lcnphy_tr_isolation_low;
-	uint8 lcnphy_tr_isolation_hi;
+	u8 lcnphy_tr_isolation_mid;
+	u8 lcnphy_tr_isolation_low;
+	u8 lcnphy_tr_isolation_hi;
 
-	uint8 lcnphy_bx_arch;
-	uint8 lcnphy_rx_power_offset;
-	uint8 lcnphy_rssi_vf;
-	uint8 lcnphy_rssi_vc;
-	uint8 lcnphy_rssi_gs;
-	uint8 lcnphy_tssi_val;
-	uint8 lcnphy_rssi_vf_lowtemp;
-	uint8 lcnphy_rssi_vc_lowtemp;
-	uint8 lcnphy_rssi_gs_lowtemp;
+	u8 lcnphy_bx_arch;
+	u8 lcnphy_rx_power_offset;
+	u8 lcnphy_rssi_vf;
+	u8 lcnphy_rssi_vc;
+	u8 lcnphy_rssi_gs;
+	u8 lcnphy_tssi_val;
+	u8 lcnphy_rssi_vf_lowtemp;
+	u8 lcnphy_rssi_vc_lowtemp;
+	u8 lcnphy_rssi_gs_lowtemp;
 
-	uint8 lcnphy_rssi_vf_hightemp;
-	uint8 lcnphy_rssi_vc_hightemp;
-	uint8 lcnphy_rssi_gs_hightemp;
+	u8 lcnphy_rssi_vf_hightemp;
+	u8 lcnphy_rssi_vc_hightemp;
+	u8 lcnphy_rssi_gs_hightemp;
 
 	int16 lcnphy_pa0b0;
 	int16 lcnphy_pa0b1;
 	int16 lcnphy_pa0b2;
 
 	uint16 lcnphy_rawtempsense;
-	uint8 lcnphy_measPower;
-	uint8 lcnphy_tempsense_slope;
-	uint8 lcnphy_freqoffset_corr;
-	uint8 lcnphy_tempsense_option;
-	uint8 lcnphy_tempcorrx;
+	u8 lcnphy_measPower;
+	u8 lcnphy_tempsense_slope;
+	u8 lcnphy_freqoffset_corr;
+	u8 lcnphy_tempsense_option;
+	u8 lcnphy_tempcorrx;
 	bool lcnphy_iqcal_swp_dis;
 	bool lcnphy_hw_iqcal_en;
 	uint lcnphy_bandedge_corr;
@@ -85,14 +85,14 @@ struct phy_info_lcnphy {
 	uint16 lcnphy_Very_Low_Gain_db;
 	int8 lcnphy_lastsensed_temperature;
 	int8 lcnphy_pkteng_rssi_slope;
-	uint8 lcnphy_saved_tx_user_target[TXP_NUM_RATES];
-	uint8 lcnphy_volt_winner;
-	uint8 lcnphy_volt_low;
-	uint8 lcnphy_54_48_36_24mbps_backoff;
-	uint8 lcnphy_11n_backoff;
-	uint8 lcnphy_lowerofdm;
-	uint8 lcnphy_cck;
-	uint8 lcnphy_psat_2pt3_detected;
+	u8 lcnphy_saved_tx_user_target[TXP_NUM_RATES];
+	u8 lcnphy_volt_winner;
+	u8 lcnphy_volt_low;
+	u8 lcnphy_54_48_36_24mbps_backoff;
+	u8 lcnphy_11n_backoff;
+	u8 lcnphy_lowerofdm;
+	u8 lcnphy_cck;
+	u8 lcnphy_psat_2pt3_detected;
 	int32 lcnphy_lowest_Re_div_Im;
 	int8 lcnphy_final_papd_cal_idx;
 	uint16 lcnphy_extstxctrl4;
@@ -102,19 +102,19 @@ struct phy_info_lcnphy {
 	int16 lcnphy_ofdm_dig_filt_type;
 	lcnphy_cal_results_t lcnphy_cal_results;
 
-	uint8 lcnphy_psat_pwr;
-	uint8 lcnphy_psat_indx;
+	u8 lcnphy_psat_pwr;
+	u8 lcnphy_psat_indx;
 	int32 lcnphy_min_phase;
-	uint8 lcnphy_final_idx;
-	uint8 lcnphy_start_idx;
-	uint8 lcnphy_current_index;
+	u8 lcnphy_final_idx;
+	u8 lcnphy_start_idx;
+	u8 lcnphy_current_index;
 	uint16 lcnphy_logen_buf_1;
 	uint16 lcnphy_local_ovr_2;
 	uint16 lcnphy_local_oval_6;
 	uint16 lcnphy_local_oval_5;
 	uint16 lcnphy_logen_mixer_1;
 
-	uint8 lcnphy_aci_stat;
+	u8 lcnphy_aci_stat;
 	uint lcnphy_aci_start_time;
 	int8 lcnphy_tx_power_offset[TXP_NUM_RATES];
 };

drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c

@@ -450,7 +450,7 @@ CONST uint16 dot11lcn_aux_gain_idx_tbl_2G[] = {
 	0x0000
 };
 
-CONST uint8 dot11lcn_gain_val_tbl_2G[] = {
+CONST u8 dot11lcn_gain_val_tbl_2G[] = {
 	0xfc,
 	0x02,
 	0x08,
@@ -915,7 +915,7 @@ CONST uint16 dot11lcn_aux_gain_idx_tbl_extlna_2G[] = {
 	0x0000
 };
 
-CONST uint8 dot11lcn_gain_val_tbl_extlna_2G[] = {
+CONST u8 dot11lcn_gain_val_tbl_extlna_2G[] = {
 	0xfc,
 	0x02,
 	0x08,
@@ -2131,7 +2131,7 @@ CONST uint16 dot11lcn_sw_ctrl_tbl_rev0[] = {
 	0x0002,
 };
 
-CONST uint8 dot11lcn_nf_table_rev0[] = {
+CONST u8 dot11lcn_nf_table_rev0[] = {
 	0x5f,
 	0x36,
 	0x29,
@@ -2150,7 +2150,7 @@ CONST uint8 dot11lcn_nf_table_rev0[] = {
 	0x1f,
 };
 
-CONST uint8 dot11lcn_gain_val_tbl_rev0[] = {
+CONST u8 dot11lcn_gain_val_tbl_rev0[] = {
 	0x09,
 	0x0f,
 	0x14,
@@ -2213,7 +2213,7 @@ CONST uint8 dot11lcn_gain_val_tbl_rev0[] = {
 	0x00,
 };
 
-CONST uint8 dot11lcn_spur_tbl_rev0[] = {
+CONST u8 dot11lcn_spur_tbl_rev0[] = {
 	0x01,
 	0x01,
 	0x01,

drivers/staging/brcm80211/phy/wlc_phytbl_n.c

@@ -854,7 +854,7 @@ CONST uint32 frame_struct_rev0[] = {
 	0x00000000,
 };
 
-CONST uint8 frame_lut_rev0[] = {
+CONST u8 frame_lut_rev0[] = {
 	0x02,
 	0x04,
 	0x14,
@@ -2607,7 +2607,7 @@ CONST uint32 chanest_tbl_rev0[] = {
 	0x10101010,
 };
 
-CONST uint8 mcs_tbl_rev0[] = {
+CONST u8 mcs_tbl_rev0[] = {
 	0x00,
 	0x08,
 	0x0a,
@@ -3256,7 +3256,7 @@ CONST uint32 noise_var_tbl1_rev0[] = {
 	0x0000014d,
 };
 
-CONST uint8 est_pwr_lut_core0_rev0[] = {
+CONST u8 est_pwr_lut_core0_rev0[] = {
 	0x50,
 	0x4f,
 	0x4e,
@@ -3323,7 +3323,7 @@ CONST uint8 est_pwr_lut_core0_rev0[] = {
 	0x11,
 };
 
-CONST uint8 est_pwr_lut_core1_rev0[] = {
+CONST u8 est_pwr_lut_core1_rev0[] = {
 	0x50,
 	0x4f,
 	0x4e,
@@ -3390,7 +3390,7 @@ CONST uint8 est_pwr_lut_core1_rev0[] = {
 	0x11,
 };
 
-CONST uint8 adj_pwr_lut_core0_rev0[] = {
+CONST u8 adj_pwr_lut_core0_rev0[] = {
 	0x00,
 	0x00,
 	0x00,
@@ -3521,7 +3521,7 @@ CONST uint8 adj_pwr_lut_core0_rev0[] = {
 	0x00,
 };
 
-CONST uint8 adj_pwr_lut_core1_rev0[] = {
+CONST u8 adj_pwr_lut_core1_rev0[] = {
 	0x00,
 	0x00,
 	0x00,
@@ -7616,7 +7616,7 @@ CONST uint32 chanest_tbl_rev3[] = {
 	0x10101010,
 };
 
-CONST uint8 frame_lut_rev3[] = {
+CONST u8 frame_lut_rev3[] = {
 	0x02,
 	0x04,
 	0x14,
@@ -7651,7 +7651,7 @@ CONST uint8 frame_lut_rev3[] = {
 	0x2a,
 };
 
-CONST uint8 est_pwr_lut_core0_rev3[] = {
+CONST u8 est_pwr_lut_core0_rev3[] = {
 	0x55,
 	0x54,
 	0x54,
@@ -7718,7 +7718,7 @@ CONST uint8 est_pwr_lut_core0_rev3[] = {
 	0xfd,
 };
 
-CONST uint8 est_pwr_lut_core1_rev3[] = {
+CONST u8 est_pwr_lut_core1_rev3[] = {
 	0x55,
 	0x54,
 	0x54,
@@ -7785,7 +7785,7 @@ CONST uint8 est_pwr_lut_core1_rev3[] = {
 	0xfd,
 };
 
-CONST uint8 adj_pwr_lut_core0_rev3[] = {
+CONST u8 adj_pwr_lut_core0_rev3[] = {
 	0x00,
 	0x00,
 	0x00,
@@ -7916,7 +7916,7 @@ CONST uint8 adj_pwr_lut_core0_rev3[] = {
 	0x00,
 };
 
-CONST uint8 adj_pwr_lut_core1_rev3[] = {
+CONST u8 adj_pwr_lut_core1_rev3[] = {
 	0x00,
 	0x00,
 	0x00,