Commit e8e3faa0 authored by Alexander Shiyan's avatar Alexander Shiyan Committed by Shawn Guo

ARM: i.MX27 clk: Introduce DT include for clock provider

Use clock defines in order to make devicetrees more human readable.
Signed-off-by: default avatarAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent 3543fc54
......@@ -7,117 +7,22 @@ Required properties:
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX27
clocks and IDs.
Clock ID
-----------------------
dummy 0
ckih 1
ckil 2
mpll 3
spll 4
mpll_main2 5
ahb 6
ipg 7
nfc_div 8
per1_div 9
per2_div 10
per3_div 11
per4_div 12
vpu_sel 13
vpu_div 14
usb_div 15
cpu_sel 16
clko_sel 17
cpu_div 18
clko_div 19
ssi1_sel 20
ssi2_sel 21
ssi1_div 22
ssi2_div 23
clko_en 24
ssi2_ipg_gate 25
ssi1_ipg_gate 26
slcdc_ipg_gate 27
sdhc3_ipg_gate 28
sdhc2_ipg_gate 29
sdhc1_ipg_gate 30
scc_ipg_gate 31
sahara_ipg_gate 32
rtc_ipg_gate 33
pwm_ipg_gate 34
owire_ipg_gate 35
lcdc_ipg_gate 36
kpp_ipg_gate 37
iim_ipg_gate 38
i2c2_ipg_gate 39
i2c1_ipg_gate 40
gpt6_ipg_gate 41
gpt5_ipg_gate 42
gpt4_ipg_gate 43
gpt3_ipg_gate 44
gpt2_ipg_gate 45
gpt1_ipg_gate 46
gpio_ipg_gate 47
fec_ipg_gate 48
emma_ipg_gate 49
dma_ipg_gate 50
cspi3_ipg_gate 51
cspi2_ipg_gate 52
cspi1_ipg_gate 53
nfc_baud_gate 54
ssi2_baud_gate 55
ssi1_baud_gate 56
vpu_baud_gate 57
per4_gate 58
per3_gate 59
per2_gate 60
per1_gate 61
usb_ahb_gate 62
slcdc_ahb_gate 63
sahara_ahb_gate 64
lcdc_ahb_gate 65
vpu_ahb_gate 66
fec_ahb_gate 67
emma_ahb_gate 68
emi_ahb_gate 69
dma_ahb_gate 70
csi_ahb_gate 71
brom_ahb_gate 72
ata_ahb_gate 73
wdog_ipg_gate 74
usb_ipg_gate 75
uart6_ipg_gate 76
uart5_ipg_gate 77
uart4_ipg_gate 78
uart3_ipg_gate 79
uart2_ipg_gate 80
uart1_ipg_gate 81
ckih_div1p5 82
fpm 83
mpll_osc_sel 84
mpll_sel 85
spll_gate 86
mshc_div 87
rtic_ipg_gate 88
mshc_ipg_gate 89
rtic_ahb_gate 90
mshc_baud_gate 91
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
for the full list of i.MX27 clock IDs.
Examples:
clks: ccm@10027000{
clks: ccm@10027000{
compatible = "fsl,imx27-ccm";
reg = <0x10027000 0x1000>;
#clock-cells = <1>;
};
};
uart1: serial@1000a000 {
uart1: serial@1000a000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks 81>, <&clks 61>;
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
<&clks IMX27_CLK_PER1_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
};
This diff is collapsed.
/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX27_H
#define __DT_BINDINGS_CLOCK_IMX27_H
#define IMX27_CLK_DUMMY 0
#define IMX27_CLK_CKIH 1
#define IMX27_CLK_CKIL 2
#define IMX27_CLK_MPLL 3
#define IMX27_CLK_SPLL 4
#define IMX27_CLK_MPLL_MAIN2 5
#define IMX27_CLK_AHB 6
#define IMX27_CLK_IPG 7
#define IMX27_CLK_NFC_DIV 8
#define IMX27_CLK_PER1_DIV 9
#define IMX27_CLK_PER2_DIV 10
#define IMX27_CLK_PER3_DIV 11
#define IMX27_CLK_PER4_DIV 12
#define IMX27_CLK_VPU_SEL 13
#define IMX27_CLK_VPU_DIV 14
#define IMX27_CLK_USB_DIV 15
#define IMX27_CLK_CPU_SEL 16
#define IMX27_CLK_CLKO_SEL 17
#define IMX27_CLK_CPU_DIV 18
#define IMX27_CLK_CLKO_DIV 19
#define IMX27_CLK_SSI1_SEL 20
#define IMX27_CLK_SSI2_SEL 21
#define IMX27_CLK_SSI1_DIV 22
#define IMX27_CLK_SSI2_DIV 23
#define IMX27_CLK_CLKO_EN 24
#define IMX27_CLK_SSI2_IPG_GATE 25
#define IMX27_CLK_SSI1_IPG_GATE 26
#define IMX27_CLK_SLCDC_IPG_GATE 27
#define IMX27_CLK_SDHC3_IPG_GATE 28
#define IMX27_CLK_SDHC2_IPG_GATE 29
#define IMX27_CLK_SDHC1_IPG_GATE 30
#define IMX27_CLK_SCC_IPG_GATE 31
#define IMX27_CLK_SAHARA_IPG_GATE 32
#define IMX27_CLK_RTC_IPG_GATE 33
#define IMX27_CLK_PWM_IPG_GATE 34
#define IMX27_CLK_OWIRE_IPG_GATE 35
#define IMX27_CLK_LCDC_IPG_GATE 36
#define IMX27_CLK_KPP_IPG_GATE 37
#define IMX27_CLK_IIM_IPG_GATE 38
#define IMX27_CLK_I2C2_IPG_GATE 39
#define IMX27_CLK_I2C1_IPG_GATE 40
#define IMX27_CLK_GPT6_IPG_GATE 41
#define IMX27_CLK_GPT5_IPG_GATE 42
#define IMX27_CLK_GPT4_IPG_GATE 43
#define IMX27_CLK_GPT3_IPG_GATE 44
#define IMX27_CLK_GPT2_IPG_GATE 45
#define IMX27_CLK_GPT1_IPG_GATE 46
#define IMX27_CLK_GPIO_IPG_GATE 47
#define IMX27_CLK_FEC_IPG_GATE 48
#define IMX27_CLK_EMMA_IPG_GATE 49
#define IMX27_CLK_DMA_IPG_GATE 50
#define IMX27_CLK_CSPI3_IPG_GATE 51
#define IMX27_CLK_CSPI2_IPG_GATE 52
#define IMX27_CLK_CSPI1_IPG_GATE 53
#define IMX27_CLK_NFC_BAUD_GATE 54
#define IMX27_CLK_SSI2_BAUD_GATE 55
#define IMX27_CLK_SSI1_BAUD_GATE 56
#define IMX27_CLK_VPU_BAUD_GATE 57
#define IMX27_CLK_PER4_GATE 58
#define IMX27_CLK_PER3_GATE 59
#define IMX27_CLK_PER2_GATE 60
#define IMX27_CLK_PER1_GATE 61
#define IMX27_CLK_USB_AHB_GATE 62
#define IMX27_CLK_SLCDC_AHB_GATE 63
#define IMX27_CLK_SAHARA_AHB_GATE 64
#define IMX27_CLK_LCDC_AHB_GATE 65
#define IMX27_CLK_VPU_AHB_GATE 66
#define IMX27_CLK_FEC_AHB_GATE 67
#define IMX27_CLK_EMMA_AHB_GATE 68
#define IMX27_CLK_EMI_AHB_GATE 69
#define IMX27_CLK_DMA_AHB_GATE 70
#define IMX27_CLK_CSI_AHB_GATE 71
#define IMX27_CLK_BROM_AHB_GATE 72
#define IMX27_CLK_ATA_AHB_GATE 73
#define IMX27_CLK_WDOG_IPG_GATE 74
#define IMX27_CLK_USB_IPG_GATE 75
#define IMX27_CLK_UART6_IPG_GATE 76
#define IMX27_CLK_UART5_IPG_GATE 77
#define IMX27_CLK_UART4_IPG_GATE 78
#define IMX27_CLK_UART3_IPG_GATE 79
#define IMX27_CLK_UART2_IPG_GATE 80
#define IMX27_CLK_UART1_IPG_GATE 81
#define IMX27_CLK_CKIH_DIV1P5 82
#define IMX27_CLK_FPM 83
#define IMX27_CLK_MPLL_OSC_SEL 84
#define IMX27_CLK_MPLL_SEL 85
#define IMX27_CLK_SPLL_GATE 86
#define IMX27_CLK_MSHC_DIV 87
#define IMX27_CLK_RTIC_IPG_GATE 88
#define IMX27_CLK_MSHC_IPG_GATE 89
#define IMX27_CLK_RTIC_AHB_GATE 90
#define IMX27_CLK_MSHC_BAUD_GATE 91
#define IMX27_CLK_MAX 92
#endif
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