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Kirill Smelkov
linux
Commits
e8f064c2
Commit
e8f064c2
authored
Aug 18, 2003
by
Linus Torvalds
Browse files
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Plain Diff
Update the 32-bit Ninja SCSI driver from YOKOTA Hiroshi.
parent
ad6ab150
Changes
5
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5 changed files
with
2468 additions
and
2090 deletions
+2468
-2090
MAINTAINERS
MAINTAINERS
+1
-1
drivers/scsi/nsp32.c
drivers/scsi/nsp32.c
+2053
-1913
drivers/scsi/nsp32.h
drivers/scsi/nsp32.h
+360
-113
drivers/scsi/nsp32_debug.c
drivers/scsi/nsp32_debug.c
+5
-4
drivers/scsi/nsp32_io.h
drivers/scsi/nsp32_io.h
+49
-59
No files found.
MAINTAINERS
View file @
e8f064c2
...
@@ -1348,7 +1348,7 @@ M: Andreas Mohr <100.30936@germany.net>
...
@@ -1348,7 +1348,7 @@ M: Andreas Mohr <100.30936@germany.net>
L: linux-net@vger.kernel.org
L: linux-net@vger.kernel.org
S: Maintained
S: Maintained
NINJA SCSI-3 / NINJA SCSI-32Bi PCMCIA SCSI HOST ADAPTER DRIVER
NINJA SCSI-3 / NINJA SCSI-32Bi
(16bit/CardBus)
PCMCIA SCSI HOST ADAPTER DRIVER
P: YOKOTA Hiroshi
P: YOKOTA Hiroshi
M: yokota@netlab.is.tsukuba.ac.jp
M: yokota@netlab.is.tsukuba.ac.jp
W: http://www.netlab.is.tsukuba.ac.jp/~yokota/izumi/ninja/
W: http://www.netlab.is.tsukuba.ac.jp/~yokota/izumi/ninja/
...
...
drivers/scsi/nsp32.c
View file @
e8f064c2
This source diff could not be displayed because it is too large. You can
view the blob
instead.
drivers/scsi/nsp32.h
View file @
e8f064c2
/*
/*
* Workbit NinjaSCSI-32Bi/UDE PCI/Card
b
us SCSI Host Bus Adapter driver
* Workbit NinjaSCSI-32Bi/UDE PCI/Card
B
us SCSI Host Bus Adapter driver
* Basic data header
* Basic data header
*
*
* This program is free software; you can redistribute it and/or modify
* This program is free software; you can redistribute it and/or modify
...
@@ -16,24 +16,23 @@
...
@@ -16,24 +16,23 @@
#ifndef _NSP32_H
#ifndef _NSP32_H
#define _NSP32_H
#define _NSP32_H
//#define NSP32_DEBUG 9
//#define NSP32_DEBUG 9
/*
/*
* VENDOR/DEVICE ID
* VENDOR/DEVICE ID
*/
*/
#define PCI_VENDOR_ID_IODATA 0x10fc
#define PCI_VENDOR_ID_IODATA 0x10fc
#define PCI_VENDOR_ID_WORKBIT 0x1145
#define PCI_VENDOR_ID_WORKBIT 0x1145
#define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005
#define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005
#define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007
#define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007
#define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007
#define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007
#define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010
#define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010
#define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011
#define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011
#define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012
#define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012
#define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013
#define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013
#define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015
#define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015
#define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009
/*
/*
* MODEL
* MODEL
...
@@ -42,20 +41,20 @@ enum {
...
@@ -42,20 +41,20 @@ enum {
MODEL_IODATA
=
0
,
MODEL_IODATA
=
0
,
MODEL_KME
=
1
,
MODEL_KME
=
1
,
MODEL_WORKBIT
=
2
,
MODEL_WORKBIT
=
2
,
MODEL_
EXT_ROM
=
3
,
MODEL_
LOGITEC
=
3
,
MODEL_PCI_WORKBIT
=
4
,
MODEL_PCI_WORKBIT
=
4
,
MODEL_PCI_LOGITEC
=
5
,
MODEL_PCI_LOGITEC
=
5
,
MODEL_PCI_MELCO
=
6
,
MODEL_PCI_MELCO
=
6
,
};
};
static
char
*
nsp32_model
[]
=
{
static
char
*
nsp32_model
[]
=
{
"I-O DATA CBSC-II"
,
"I-O DATA CBSC-II
CardBus card
"
,
"KME SCSI card"
,
"KME SCSI
CardBus
card"
,
"Workbit duo SCSI card"
,
"Workbit duo SCSI
CardBus
card"
,
"
E
xternal ROM"
,
"
Logitec CardBus card with e
xternal ROM"
,
"Workbit
Standard/IO Data
PCI card"
,
"Workbit
/ I-O DATA
PCI card"
,
"Logitec PCI card"
,
"Logitec PCI card
with external ROM
"
,
"Melco
PCI card
"
,
"Melco
CardBus/PCI card with external ROM
"
,
};
};
...
@@ -64,13 +63,17 @@ static char * nsp32_model[] = {
...
@@ -64,13 +63,17 @@ static char * nsp32_model[] = {
*/
*/
#define EXTENDED_SDTR_LEN 0x03
#define EXTENDED_SDTR_LEN 0x03
/* Little Endian */
typedef
u32
u32_le
;
typedef
u16
u16_le
;
/*
/*
* MACRO
* MACRO
*/
*/
#define BIT(x) (1UL << (x))
#define NUMBER(arr) ((int) (sizeof(arr) / sizeof(arr[0])))
#define BIT(x) (1UL << (x))
#ifndef MIN
#ifndef MIN
# define MIN(a,b) ((a) > (b) ? (b) : (a))
# define MIN(a,b)
((a) > (b) ? (b) : (a))
#endif
#endif
/*
/*
...
@@ -111,7 +114,10 @@ static char * nsp32_model[] = {
...
@@ -111,7 +114,10 @@ static char * nsp32_model[] = {
# define TIMER_IRQ_MASK BIT(13)
# define TIMER_IRQ_MASK BIT(13)
# define FIFO_IRQ_MASK BIT(14)
# define FIFO_IRQ_MASK BIT(14)
# define SCSI_IRQ_MASK BIT(15)
# define SCSI_IRQ_MASK BIT(15)
# define IRQ_CONTROL_ALL_IRQ_MASK 0xf000
# define IRQ_CONTROL_ALL_IRQ_MASK (PCI_IRQ_MASK | \
TIMER_IRQ_MASK | \
FIFO_IRQ_MASK | \
SCSI_IRQ_MASK )
# define IRQSTATUS_ANY_IRQ (IRQSTATUS_RESELECT_OCCUER | \
# define IRQSTATUS_ANY_IRQ (IRQSTATUS_RESELECT_OCCUER | \
IRQSTATUS_PHASE_CHANGE_IRQ | \
IRQSTATUS_PHASE_CHANGE_IRQ | \
IRQSTATUS_SCSIRESET_IRQ | \
IRQSTATUS_SCSIRESET_IRQ | \
...
@@ -121,8 +127,8 @@ static char * nsp32_model[] = {
...
@@ -121,8 +127,8 @@ static char * nsp32_model[] = {
IRQSTATUS_BMCNTERR_IRQ | \
IRQSTATUS_BMCNTERR_IRQ | \
IRQSTATUS_AUTOSCSI_IRQ )
IRQSTATUS_AUTOSCSI_IRQ )
#define TRANSFER_CONTROL
0x02
/* BASE+02, W, W */
#define TRANSFER_CONTROL
0x02
/* BASE+02, W, W */
#define TRANSFER_STATUS
0x02
/* BASE+02, W, R */
#define TRANSFER_STATUS
0x02
/* BASE+02, W, R */
# define CB_MMIO_MODE BIT(0)
# define CB_MMIO_MODE BIT(0)
# define CB_IO_MODE BIT(1)
# define CB_IO_MODE BIT(1)
# define BM_TEST BIT(2)
# define BM_TEST BIT(2)
...
@@ -139,26 +145,29 @@ static char * nsp32_model[] = {
...
@@ -139,26 +145,29 @@ static char * nsp32_model[] = {
# define ALL_COUNTER_CLR BIT(14)
# define ALL_COUNTER_CLR BIT(14)
# define FIFOTEST BIT(15)
# define FIFOTEST BIT(15)
#define INDEX_REG
0x04
/* BASE+04, Byte(R/W), Word(R) */
#define INDEX_REG
0x04
/* BASE+04, Byte(R/W), Word(R) */
#define TIMER_SET
0x06
/* BASE+06, W, R/W */
#define TIMER_SET
0x06
/* BASE+06, W, R/W */
# define TIMER_CNT_MASK
0xff
# define TIMER_CNT_MASK
(0xff)
# define TIMER_STOP BIT(8)
# define TIMER_STOP BIT(8)
#define DATA_REG_LOW
0x08
/* BASE+08, LowW, R/W */
#define DATA_REG_LOW
0x08
/* BASE+08, LowW, R/W */
#define DATA_REG_HI
0x0a
/* BASE+0a, Hi-W, R/W */
#define DATA_REG_HI
0x0a
/* BASE+0a, Hi-W, R/W */
#define FIFO_REST_CNT
0x0c
/* BASE+0c, W, R/W */
#define FIFO_REST_CNT
0x0c
/* BASE+0c, W, R/W */
# define FIFO_REST_MASK 0x1ff
# define FIFO_REST_MASK 0x1ff
# define FIFO_EMPTY_SHLD_FLAG BIT(14)
# define FIFO_EMPTY_SHLD_FLAG BIT(14)
# define FIFO_FULL_SHLD_FLAG BIT(15)
# define FIFO_FULL_SHLD_FLAG BIT(15)
#define SREQ_SMPL_RATE
0x0f
/* BASE+0f, B, R/W */
#define SREQ_SMPL_RATE
0x0f
/* BASE+0f, B, R/W */
# define SREQSMPLRATE_RATE0 BIT(0)
# define SREQSMPLRATE_RATE0 BIT(0)
# define SREQSMPLRATE_RATE1 BIT(1)
# define SREQSMPLRATE_RATE1 BIT(1)
# define SAMPLING_ENABLE BIT(2)
# define SAMPLING_ENABLE BIT(2)
# define SMPL_40M (0)
/* 40MHz: 0-100ns/period */
# define SMPL_20M (SREQSMPLRATE_RATE0)
/* 20MHz: 100-200ns/period */
# define SMPL_10M (SREQSMPLRATE_RATE1)
/* 10Mhz: 200- ns/period */
#define SCSI_BUS_CONTROL
0x10
/* BASE+10, B, R/W */
#define SCSI_BUS_CONTROL
0x10
/* BASE+10, B, R/W */
# define BUSCTL_SEL BIT(0)
# define BUSCTL_SEL BIT(0)
# define BUSCTL_RST BIT(1)
# define BUSCTL_RST BIT(1)
# define BUSCTL_DATAOUT_ENB BIT(2)
# define BUSCTL_DATAOUT_ENB BIT(2)
...
@@ -168,16 +177,21 @@ static char * nsp32_model[] = {
...
@@ -168,16 +177,21 @@ static char * nsp32_model[] = {
# define AUTODIRECTION BIT(6)
# define AUTODIRECTION BIT(6)
# define ACKENB BIT(7)
# define ACKENB BIT(7)
#define CLR_COUNTER
0x12
/* BASE+12, B, W */
#define CLR_COUNTER
0x12
/* BASE+12, B, W */
# define ACK_COUNTER_CLR BIT(0)
# define ACK_COUNTER_CLR BIT(0)
# define SREQ_COUNTER_CLR BIT(1)
# define SREQ_COUNTER_CLR BIT(1)
# define FIFO_HOST_POINTER_CLR BIT(2)
# define FIFO_HOST_POINTER_CLR BIT(2)
# define FIFO_REST_COUNT_CLR BIT(3)
# define FIFO_REST_COUNT_CLR BIT(3)
# define BM_COUNTER_CLR BIT(4)
# define BM_COUNTER_CLR BIT(4)
# define SAVED_ACK_CLR BIT(5)
# define SAVED_ACK_CLR BIT(5)
# define CLRCOUNTER_ALLMASK (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
# define CLRCOUNTER_ALLMASK (ACK_COUNTER_CLR | \
SREQ_COUNTER_CLR | \
#define SCSI_BUS_MONITOR 0x12
/* BASE+12, B, R */
FIFO_HOST_POINTER_CLR | \
FIFO_REST_COUNT_CLR | \
BM_COUNTER_CLR | \
SAVED_ACK_CLR )
#define SCSI_BUS_MONITOR 0x12
/* BASE+12, B, R */
# define BUSMON_MSG BIT(0)
# define BUSMON_MSG BIT(0)
# define BUSMON_IO BIT(1)
# define BUSMON_IO BIT(1)
# define BUSMON_CD BIT(2)
# define BUSMON_CD BIT(2)
...
@@ -187,20 +201,20 @@ static char * nsp32_model[] = {
...
@@ -187,20 +201,20 @@ static char * nsp32_model[] = {
# define BUSMON_SEL BIT(6)
# define BUSMON_SEL BIT(6)
# define BUSMON_ATN BIT(7)
# define BUSMON_ATN BIT(7)
#define COMMAND_DATA
0x14
/* BASE+14, B, R/W */
#define COMMAND_DATA
0x14
/* BASE+14, B, R/W */
#define PARITY_CONTROL
0x16
/* BASE+16, B, R/
W */
#define PARITY_CONTROL
0x16
/* BASE+16, B,
W */
# define PARITY_CHECK_ENABLE BIT(0)
# define PARITY_CHECK_ENABLE BIT(0)
# define PARITY_ERROR_CLEAR BIT(1)
# define PARITY_ERROR_CLEAR BIT(1)
#define PARITY_STATUS
0x16
#define PARITY_STATUS
0x16
/* BASE+16, B, R */
//# define PARITY_CHECK_ENABLE BIT(0)
//# define PARITY_CHECK_ENABLE BIT(0)
# define PARITY_ERROR_NORMAL BIT(1)
# define PARITY_ERROR_NORMAL BIT(1)
# define PARITY_ERROR_LSB BIT(1)
# define PARITY_ERROR_LSB BIT(1)
# define PARITY_ERROR_MSB BIT(2)
# define PARITY_ERROR_MSB BIT(2)
#define RESELECT_ID
0x18
/* BASE+18, B, R */
#define RESELECT_ID
0x18
/* BASE+18, B, R */
#define COMMAND_CONTROL
0x18
/* BASE+18, W, W */
#define COMMAND_CONTROL
0x18
/* BASE+18, W, W */
# define CLEAR_CDB_FIFO_POINTER BIT(0)
# define CLEAR_CDB_FIFO_POINTER BIT(0)
# define AUTO_COMMAND_PHASE BIT(1)
# define AUTO_COMMAND_PHASE BIT(1)
# define AUTOSCSI_START BIT(2)
# define AUTOSCSI_START BIT(2)
...
@@ -211,27 +225,27 @@ static char * nsp32_model[] = {
...
@@ -211,27 +225,27 @@ static char * nsp32_model[] = {
# define AUTO_MSGIN_02 BIT(7)
# define AUTO_MSGIN_02 BIT(7)
# define AUTO_MSGIN_03 BIT(8)
# define AUTO_MSGIN_03 BIT(8)
#define SET_ARBIT
0x1a
/* BASE+1a, B, W */
#define SET_ARBIT
0x1a
/* BASE+1a, B, W */
# define ARBIT_GO BIT(0)
# define ARBIT_GO BIT(0)
# define ARBIT_CLEAR BIT(1)
# define ARBIT_CLEAR BIT(1)
#define ARBIT_STATUS
0x1a
/* BASE+1a, B, R */
#define ARBIT_STATUS
0x1a
/* BASE+1a, B, R */
//# define ARBIT_GO BIT(0)
//# define ARBIT_GO BIT(0)
# define ARBIT_WIN BIT(1)
# define ARBIT_WIN BIT(1)
# define ARBIT_FAIL BIT(2)
# define ARBIT_FAIL BIT(2)
# define AUTO_PARAMETER_VALID BIT(3)
# define AUTO_PARAMETER_VALID BIT(3)
# define SGT_VALID BIT(4)
# define SGT_VALID BIT(4)
#define SYNC_REG
0x1c
/* BASE+1c, B, R/W */
#define SYNC_REG
0x1c
/* BASE+1c, B, R/W */
#define ACK_WIDTH
0x1d
/* BASE+1d, B, R/W */
#define ACK_WIDTH
0x1d
/* BASE+1d, B, R/W */
#define SCSI_DATA_WITH_ACK
0x20
/* BASE+20, B, R/W */
#define SCSI_DATA_WITH_ACK
0x20
/* BASE+20, B, R/W */
#define SCSI_OUT_LATCH_TARGET_ID 0x22
/* BASE+22, B, W */
#define SCSI_OUT_LATCH_TARGET_ID 0x22
/* BASE+22, B, W */
#define SCSI_DATA_IN
0x22
/* BASE+22, B, R */
#define SCSI_DATA_IN
0x22
/* BASE+22, B, R */
#define SCAM_CONTROL
0x24
/* BASE+24, B, W */
#define SCAM_CONTROL
0x24
/* BASE+24, B, W */
#define SCAM_STATUS
0x24
/* BASE+24, B, R */
#define SCAM_STATUS
0x24
/* BASE+24, B, R */
# define SCAM_MSG BIT(0)
# define SCAM_MSG BIT(0)
# define SCAM_IO BIT(1)
# define SCAM_IO BIT(1)
# define SCAM_CD BIT(2)
# define SCAM_CD BIT(2)
...
@@ -239,31 +253,31 @@ static char * nsp32_model[] = {
...
@@ -239,31 +253,31 @@ static char * nsp32_model[] = {
# define SCAM_SEL BIT(4)
# define SCAM_SEL BIT(4)
# define SCAM_XFEROK BIT(5)
# define SCAM_XFEROK BIT(5)
#define SCAM_DATA
0x26
/* BASE+26, B, R/W */
#define SCAM_DATA
0x26
/* BASE+26, B, R/W */
# define SD0
BIT(0)
# define SD0 BIT(0)
# define SD1
BIT(1)
# define SD1 BIT(1)
# define SD2
BIT(2)
# define SD2 BIT(2)
# define SD3
BIT(3)
# define SD3 BIT(3)
# define SD4
BIT(4)
# define SD4 BIT(4)
# define SD5
BIT(5)
# define SD5 BIT(5)
# define SD6
BIT(6)
# define SD6 BIT(6)
# define SD7
BIT(7)
# define SD7 BIT(7)
#define SACK_CNT
0x28
/* BASE+28, DW, R/W */
#define SACK_CNT
0x28
/* BASE+28, DW, R/W */
#define SREQ_CNT
0x2c
/* BASE+2c, DW, R/W */
#define SREQ_CNT
0x2c
/* BASE+2c, DW, R/W */
#define FIFO_DATA_LOW
0x30
/* BASE+30, B/W/DW, R/W */
#define FIFO_DATA_LOW
0x30
/* BASE+30, B/W/DW, R/W */
#define FIFO_DATA_HIGH
0x32
/* BASE+32, B/W, R/W */
#define FIFO_DATA_HIGH
0x32
/* BASE+32, B/W, R/W */
#define BM_START_ADR
0x34
/* BASE+34, DW, R/W */
#define BM_START_ADR
0x34
/* BASE+34, DW, R/W */
#define BM_CNT
0x38
/* BASE+38, DW, R/W */
#define BM_CNT
0x38
/* BASE+38, DW, R/W */
# define BM_COUNT_MASK 0x0001ffff
# define BM_COUNT_MASK 0x0001ffff
UL
# define SGTEND BIT(31)
# define SGTEND BIT(31)
/* Last SGT marker */
#define SGT_ADR
0x3c
/* BASE+3c, DW, R/W */
#define SGT_ADR
0x3c
/* BASE+3c, DW, R/W */
#define WAIT_REG
0x40
/* Bi only */
#define WAIT_REG
0x40
/* Bi only */
#define SCSI_EXECUTE_PHASE
0x40
/* BASE+40, W, R */
#define SCSI_EXECUTE_PHASE
0x40
/* BASE+40, W, R */
# define COMMAND_PHASE BIT(0)
# define COMMAND_PHASE BIT(0)
# define DATA_IN_PHASE BIT(1)
# define DATA_IN_PHASE BIT(1)
# define DATA_OUT_PHASE BIT(2)
# define DATA_OUT_PHASE BIT(2)
...
@@ -280,14 +294,14 @@ static char * nsp32_model[] = {
...
@@ -280,14 +294,14 @@ static char * nsp32_model[] = {
# define MSGIN_04_VALID BIT(13)
# define MSGIN_04_VALID BIT(13)
# define AUTOSCSI_BUSY BIT(15)
# define AUTOSCSI_BUSY BIT(15)
#define SCSI_CSB_IN
0x42
/* BASE+42, B, R */
#define SCSI_CSB_IN
0x42
/* BASE+42, B, R */
#define SCSI_MSG_OUT
0x44
/* BASE+44, DW, R/W */
#define SCSI_MSG_OUT
0x44
/* BASE+44, DW, R/W */
# define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
# define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
# define MV_VALID
BIT(7)
# define MV_VALID BIT(7)
#define SEL_TIME_OUT
0x48
/* BASE+48, W, R/W */
#define SEL_TIME_OUT
0x48
/* BASE+48, W, R/W */
#define SAVED_SACK_CNT
0x4c
/* BASE+4c, DW, R */
#define SAVED_SACK_CNT
0x4c
/* BASE+4c, DW, R */
#define HTOSDATADELAY 0x50
/* BASE+50, B, R/W */
#define HTOSDATADELAY 0x50
/* BASE+50, B, R/W */
#define STOHDATADELAY 0x54
/* BASE+54, B, R/W */
#define STOHDATADELAY 0x54
/* BASE+54, B, R/W */
...
@@ -299,21 +313,21 @@ static char * nsp32_model[] = {
...
@@ -299,21 +313,21 @@ static char * nsp32_model[] = {
/* indexed register */
/* indexed register */
/********************/
/********************/
#define CLOCK_DIV
0x00
/* BASE+08, IDX+00, B, R/W */
#define CLOCK_DIV
0x00
/* BASE+08, IDX+00, B, R/W */
# define CLOCK_2
BIT(0)
/* MCLK/2 */
# define CLOCK_2
BIT(0)
/* MCLK/2 */
# define CLOCK_4
BIT(1)
/* MCLK/4 */
# define CLOCK_4
BIT(1)
/* MCLK/4 */
# define PCICLK
BIT(7)
/* PCICLK (33MHz) */
# define PCICLK
BIT(7)
/* PCICLK (33MHz) */
#define TERM_PWR_CONTROL
0x01
/* BASE+08, IDX+01, B, R/W */
#define TERM_PWR_CONTROL
0x01
/* BASE+08, IDX+01, B, R/W */
# define BPWR BIT(0)
# define BPWR BIT(0)
# define SENSE BIT(1)
/* Read Only */
# define SENSE BIT(1)
/* Read Only */
#define EXT_PORT_DDR
0x02
/* BASE+08, IDX+02, B, R/W */
#define EXT_PORT_DDR
0x02
/* BASE+08, IDX+02, B, R/W */
#define EXT_PORT
0x03
/* BASE+08, IDX+03, B, R/W */
#define EXT_PORT
0x03
/* BASE+08, IDX+03, B, R/W */
# define LED_ON
0
# define LED_ON
(0)
# define LED_OFF
1
# define LED_OFF
BIT(0)
#define IRQ_SELECT
0x04
/* BASE+08, IDX+04, W, R/W */
#define IRQ_SELECT
0x04
/* BASE+08, IDX+04, W, R/W */
# define IRQSELECT_RESELECT_IRQ BIT(0)
# define IRQSELECT_RESELECT_IRQ BIT(0)
# define IRQSELECT_PHASE_CHANGE_IRQ BIT(1)
# define IRQSELECT_PHASE_CHANGE_IRQ BIT(1)
# define IRQSELECT_SCSIRESET_IRQ BIT(2)
# define IRQSELECT_SCSIRESET_IRQ BIT(2)
...
@@ -326,32 +340,35 @@ static char * nsp32_model[] = {
...
@@ -326,32 +340,35 @@ static char * nsp32_model[] = {
# define IRQSELECT_BMCNTERR_IRQ BIT(9)
# define IRQSELECT_BMCNTERR_IRQ BIT(9)
# define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10)
# define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10)
#define OLD_SCSI_PHASE
0x05
/* BASE+08, IDX+05, B, R */
#define OLD_SCSI_PHASE
0x05
/* BASE+08, IDX+05, B, R */
# define OLD_MSG BIT(0)
# define OLD_MSG BIT(0)
# define OLD_IO BIT(1)
# define OLD_IO BIT(1)
# define OLD_CD BIT(2)
# define OLD_CD BIT(2)
# define OLD_BUSY BIT(3)
# define OLD_BUSY BIT(3)
#define FIFO_FULL_SHLD_COUNT
0x06
/* BASE+08, IDX+06, B, R/W */
#define FIFO_FULL_SHLD_COUNT
0x06
/* BASE+08, IDX+06, B, R/W */
#define FIFO_EMPTY_SHLD_COUNT
0x07
/* BASE+08, IDX+07, B, R/W */
#define FIFO_EMPTY_SHLD_COUNT
0x07
/* BASE+08, IDX+07, B, R/W */
#define EXP_ROM_CONTROL 0x08
/* BASE+08, IDX+08, B, R/W */
#define EXP_ROM_CONTROL 0x08
/* BASE+08, IDX+08, B, R/W */
/* external ROM control */
# define ROM_WRITE_ENB BIT(0)
# define IO_ACCESS_ENB BIT(1)
# define ROM_ADR_CLEAR BIT(2)
#define EXP_ROM_ADR
L
0x09
/* BASE+08, IDX+09, W, R/W */
#define EXP_ROM_ADR 0x09
/* BASE+08, IDX+09, W, R/W */
#define EXP_ROM_DATA 0x0a
/* BASE+08, IDX+0a, B, R/W */
#define EXP_ROM_DATA 0x0a
/* BASE+08, IDX+0a, B, R/W */
#define CHIP_MODE
0x0b
/*
Bi only */
#define CHIP_MODE
0x0b
/* BASE+08, IDX+0b, B, R */
/* NinjaSCSI-32
Bi only */
# define OEM0 BIT(1)
# define OEM0 BIT(1)
/* OEM select */
/* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */
# define OEM1 BIT(2)
# define OEM1 BIT(2)
/* OEM select */
# define OPTB BIT(3)
# define OPTB BIT(3)
/* KME mode select */
# define OPTC BIT(4)
# define OPTC BIT(4)
/* KME mode select */
# define OPTD BIT(5)
# define OPTD BIT(5)
/* KME mode select */
# define OPTE BIT(6)
# define OPTE BIT(6)
/* KME mode select */
# define OPTF BIT(7)
# define OPTF BIT(7)
/* Power management */
#define MISC_WR
0x0c
/* BASE+08, IDX+0c, W, R/W */
#define MISC_WR
0x0c
/* BASE+08, IDX+0c, W, R/W */
#define MISC_RD
0x0c
#define MISC_RD
0x0c
# define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)
# define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)
# define SCSI2_HOST_DIRECTION_VALID BIT(1)
/* Read only */
# define SCSI2_HOST_DIRECTION_VALID BIT(1)
/* Read only */
# define HOST2_SCSI_DIRECTION_VALID BIT(2)
/* Read only */
# define HOST2_SCSI_DIRECTION_VALID BIT(2)
/* Read only */
...
@@ -362,7 +379,7 @@ static char * nsp32_model[] = {
...
@@ -362,7 +379,7 @@ static char * nsp32_model[] = {
# define MISC_MABORT_MASK BIT(7)
# define MISC_MABORT_MASK BIT(7)
# define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8)
# define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8)
#define BM_CYCLE
0x0d
/* BASE+08, IDX+0d, B, R/W */
#define BM_CYCLE
0x0d
/* BASE+08, IDX+0d, B, R/W */
# define BM_CYCLE0 BIT(0)
# define BM_CYCLE0 BIT(0)
# define BM_CYCLE1 BIT(1)
# define BM_CYCLE1 BIT(1)
# define BM_FRAME_ASSERT_TIMING BIT(2)
# define BM_FRAME_ASSERT_TIMING BIT(2)
...
@@ -373,20 +390,26 @@ static char * nsp32_model[] = {
...
@@ -373,20 +390,26 @@ static char * nsp32_model[] = {
# define MEMRD_CMD1 BIT(7)
# define MEMRD_CMD1 BIT(7)
#define SREQ_EDGH
0x0e
/* BASE+08, IDX+0e, B, W */
#define SREQ_EDGH
0x0e
/* BASE+08, IDX+0e, B, W */
# define SREQ_EDGH_SELECT BIT(0)
# define SREQ_EDGH_SELECT BIT(0)
#define UP_CNT 0x0f
/* BASE+08, IDX+0f, B, W */
#define UP_CNT
0x0f
/* BASE+08, IDX+0f, B, W */
#
define CFG_CMD_STR 0x10
/* BASE+08, IDX+10, W, R */
#
define REQCNT_UP BIT(0)
#
define CFG_LATE_CACHE 0x11
/* BASE+08, IDX+11, W, R/W */
#
define ACKCNT_UP BIT(1)
#
define CFG_BASE_ADR_1 0x12
/* BASE+08, IDX+12, W, R */
#
define BMADR_UP BIT(4)
#
define CFG_BASE_ADR_2 0x13
/* BASE+08, IDX+13, W, R */
#
define BMCNT_UP BIT(5)
#
define CFG_INLINE 0x14
/* BASE+08, IDX+14, W, R */
#
define SGT_CNT_UP BIT(7)
#define SERIAL_ROM_CTL 0x15
/* BASE+08, IDX+15, B, R */
#define CFG_CMD_STR 0x10
/* BASE+08, IDX+10, W, R */
# define SCL BIT(0)
#define CFG_LATE_CACHE 0x11
/* BASE+08, IDX+11, W, R/W */
# define ENA BIT(1)
#define CFG_BASE_ADR_1 0x12
/* BASE+08, IDX+12, W, R */
# define SDA BIT(2)
#define CFG_BASE_ADR_2 0x13
/* BASE+08, IDX+13, W, R */
#define CFG_INLINE 0x14
/* BASE+08, IDX+14, W, R */
#define SERIAL_ROM_CTL 0x15
/* BASE+08, IDX+15, B, R */
# define SCL BIT(0)
# define ENA BIT(1)
# define SDA BIT(2)
#define FIFO_HST_POINTER 0x16
/* BASE+08, IDX+16, B, R/W */
#define FIFO_HST_POINTER 0x16
/* BASE+08, IDX+16, B, R/W */
#define SREQ_DELAY 0x17
/* BASE+08, IDX+17, B, R/W */
#define SREQ_DELAY 0x17
/* BASE+08, IDX+17, B, R/W */
...
@@ -425,5 +448,229 @@ static char * nsp32_model[] = {
...
@@ -425,5 +448,229 @@ static char * nsp32_model[] = {
#define BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK )
#define BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK )
#define BUSPHASE_SELECT ( BUSMON_SEL | BUSMON_IO )
#define BUSPHASE_SELECT ( BUSMON_SEL | BUSMON_IO )
#endif
/* _NSP32_H */
/************************************************************************
* structure for DMA/Scatter Gather list
*/
#define NSP32_SG_SIZE SG_ALL
typedef
struct
_nsp32_sgtable
{
/* values must be little endian */
u32_le
addr
;
/* transfer address */
u32_le
len
;
/* transfer length. BIT(31) is for SGT_END mark */
}
__attribute__
((
packed
))
nsp32_sgtable
;
typedef
struct
_nsp32_sglun
{
nsp32_sgtable
sgt
[
NSP32_SG_SIZE
+
1
];
/* SG table */
}
__attribute__
((
packed
))
nsp32_sglun
;
#define NSP32_SG_TABLE_SIZE (sizeof(nsp32_sgtable) * NSP32_SG_SIZE * MAX_TARGET * MAX_LUN)
/* Auto parameter mode memory map. */
/* All values must be little endian. */
typedef
struct
_nsp32_autoparam
{
u8
cdb
[
4
*
0x10
];
/* SCSI Command */
u32_le
msgout
;
/* outgoing messages */
u8
syncreg
;
/* sync register value */
u8
ackwidth
;
/* ack width register value */
u8
target_id
;
/* target/host device id */
u8
sample_reg
;
/* hazard killer sampling rate */
u16_le
command_control
;
/* command control register */
u16_le
transfer_control
;
/* transfer control register */
u32_le
sgt_pointer
;
/* SG table physical address for DMA */
u32_le
dummy
[
2
];
}
__attribute__
((
packed
))
nsp32_autoparam
;
/* must be packed struct */
/*
* host data structure
*/
/* message in/out buffer */
#define MSGOUTBUF_MAX 20
#define MSGINBUF_MAX 20
/* flag for trans_method */
#define NSP32_TRANSFER_BUSMASTER BIT(0)
#define NSP32_TRANSFER_MMIO BIT(1)
/* Not supported yet */
#define NSP32_TRANSFER_PIO BIT(2)
/* Not supported yet */
/*
* structure for connected LUN dynamic data
*
* Note: Currently tagged queuing is disabled, each nsp32_lunt holds
* one SCSI command and one state.
*/
#define DISCPRIV_OK BIT(0)
/* DISCPRIV Enable mode */
#define MSGIN03 BIT(1)
/* Auto Msg In 03 Flag */
typedef
struct
_nsp32_lunt
{
Scsi_Cmnd
*
SCpnt
;
/* Current Handling Scsi_Cmnd */
unsigned
long
save_datp
;
/* Save Data Pointer - saved position from initial address */
int
msgin03
;
/* auto msg in 03 flag */
unsigned
int
sg_num
;
/* Total number of SG entries */
int
cur_entry
;
/* Current SG entry number */
nsp32_sglun
*
sglun
;
/* sg table per lun */
dma_addr_t
sglun_paddr
;
/* sglun physical address */
}
nsp32_lunt
;
/*
* SCSI TARGET/LUN definition
*/
#define NSP32_HOST_SCSIID 7
/* SCSI initiator is everytime defined as 7 */
#define MAX_TARGET 8
#define MAX_LUN 8
/* XXX: In SPI3, max number of LUN is 64. */
typedef
struct
_nsp32_sync_table
{
unsigned
char
period_num
;
/* period number */
unsigned
char
ackwidth
;
/* ack width designated by period */
unsigned
char
start_period
;
/* search range - start period */
unsigned
char
end_period
;
/* search range - end period */
unsigned
char
sample_rate
;
/* hazard killer parameter */
}
nsp32_sync_table
;
/*
* structure for target device static data
*/
/* flag for nsp32_target.sync_flag */
#define SDTR_INITIATOR BIT(0)
/* sending SDTR from initiator */
#define SDTR_TARGET BIT(1)
/* sending SDTR from target */
#define SDTR_DONE BIT(2)
/* exchanging SDTR has been processed */
/* syncronous period value for nsp32_target.config_max */
#define FAST5M 0x32
#define FAST10M 0x19
#define ULTRA20M 0x0c
/* flag for nsp32_target.{sync_offset}, period */
#define ASYNC_OFFSET 0
/* asynchronous transfer */
#define SYNC_OFFSET 0xf
/* synchronous transfer max offset */
/* syncreg:
bit:07 06 05 04 03 02 01 00
---PERIOD-- ---OFFSET-- */
#define TO_SYNCREG(period, offset) (((period) & 0x0f) << 4 | ((offset) & 0x0f))
typedef
struct
_nsp32_target
{
unsigned
char
syncreg
;
/* value for SYNCREG */
unsigned
char
ackwidth
;
/* value for ACKWIDTH */
unsigned
char
period
;
/* sync period (0-255) */
unsigned
char
offset
;
/* sync offset (0-15) */
int
sync_flag
;
/* SDTR_*, 0 */
int
limit_entry
;
/* max speed limit entry designated
by EEPROM configuration */
unsigned
char
sample_reg
;
/* SREQ hazard killer register */
}
nsp32_target
;
typedef
struct
_nsp32_hw_data
{
int
IrqNumber
;
int
BaseAddress
;
int
NumAddress
;
unsigned
long
MmioAddress
;
#define NSP32_MMIO_OFFSET 0x0800
unsigned
long
MmioLength
;
Scsi_Cmnd
*
CurrentSC
;
struct
pci_dev
*
Pci
;
const
struct
pci_device_id
*
pci_devid
;
struct
Scsi_Host
*
Host
;
spinlock_t
Lock
;
char
info_str
[
100
];
/* allocated memory region */
nsp32_sglun
*
sg_list
;
/* sglist virtuxal address */
dma_addr_t
sg_paddr
;
/* physical address of hw_sg_table */
nsp32_autoparam
*
autoparam
;
/* auto parameter transfer region */
dma_addr_t
auto_paddr
;
/* physical address of autoparam */
int
cur_entry
;
/* current sgt entry */
/* target/LUN */
nsp32_lunt
*
cur_lunt
;
/* Current connected LUN table */
nsp32_lunt
lunt
[
MAX_TARGET
][
MAX_LUN
];
/* All LUN table */
nsp32_target
*
cur_target
;
/* Current connected SCSI ID */
nsp32_target
target
[
MAX_TARGET
];
/* SCSI ID */
int
cur_id
;
/* Current connected target ID */
int
cur_lun
;
/* Current connected target LUN */
/* behavior setting parameters */
int
trans_method
;
/* transfer method flag */
int
resettime
;
/* Reset time */
int
clock
;
/* clock dividing flag */
nsp32_sync_table
*
synct
;
/* sync_table determined by clock */
int
syncnum
;
/* the max number of synct element */
/* message buffer */
unsigned
char
msgoutbuf
[
MSGOUTBUF_MAX
];
/* msgout buffer */
char
msgout_len
;
/* msgoutbuf length */
unsigned
char
msginbuf
[
MSGINBUF_MAX
];
/* megin buffer */
char
msgin_len
;
/* msginbuf length */
#ifdef CONFIG_PM
u32
PciState
[
16
];
/* save PCI state to this area */
#endif
}
nsp32_hw_data
;
/*
* TIME definition
*/
#define RESET_HOLD_TIME 10000
/* reset time in us (SCSI-2 says the
minimum is 25us) */
#define SEL_TIMEOUT_TIME 10000
/* 250ms defined in SCSI specification
(25.6us/1unit) */
#define ARBIT_TIMEOUT_TIME 100
/* 100us */
#define REQSACK_TIMEOUT_TIME 10000
/* max wait time for REQ/SACK assertion
or negation, 10000us == 10ms */
/**************************************************************************
* Compatibility functions
*/
/* for Kernel 2.4 */
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
# define scsi_register_host(template) scsi_register_module(MODULE_SCSI_HA, template)
# define scsi_unregister_host(template) scsi_unregister_module(MODULE_SCSI_HA, template)
# define scsi_host_put(host) scsi_unregister(host)
# define pci_name(pci_dev) ((pci_dev)->slot_name)
typedef
void
irqreturn_t
;
# define IRQ_NONE
/* */
# define IRQ_HANDLED
/* */
# define IRQ_RETVAL(x)
/* */
/* This is ad-hoc version of scsi_host_get_next() */
static
inline
struct
Scsi_Host
*
scsi_host_get_next
(
struct
Scsi_Host
*
host
)
{
if
(
host
==
NULL
)
{
return
scsi_hostlist
;
}
else
{
return
host
->
next
;
}
}
/* This is ad-hoc version of scsi_host_hn_get() */
static
inline
struct
Scsi_Host
*
scsi_host_hn_get
(
unsigned
short
hostno
)
{
struct
Scsi_Host
*
host
;
for
(
host
=
scsi_host_get_next
(
NULL
);
host
!=
NULL
;
host
=
scsi_host_get_next
(
host
))
{
if
(
host
->
host_no
==
hostno
)
{
break
;
}
}
return
host
;
}
#endif
/* for Kernel 2.6 */
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
# define __devinitdata
/* */
#endif
#endif
/* _NSP32_H */
/* end */
/* end */
drivers/scsi/nsp32_debug.c
View file @
e8f064c2
/*
/*
* Workbit NinjaSCSI-32Bi/UDE PCI/Card
b
us SCSI Host Bus Adapter driver
* Workbit NinjaSCSI-32Bi/UDE PCI/Card
B
us SCSI Host Bus Adapter driver
* Debug routine
* Debug routine
*
*
* This software may be used and distributed according to the terms of
* This software may be used and distributed according to the terms of
...
@@ -88,7 +88,7 @@ static void print_commandk (unsigned char *command)
...
@@ -88,7 +88,7 @@ static void print_commandk (unsigned char *command)
int
i
,
s
;
int
i
,
s
;
// printk(KERN_DEBUG);
// printk(KERN_DEBUG);
print_opcodek
(
command
[
0
]);
print_opcodek
(
command
[
0
]);
/*printk(KERN_DEBUG
__func__ " "
);*/
/*printk(KERN_DEBUG
"%s ", __FUNCTION__
);*/
if
((
command
[
0
]
>>
5
)
==
6
||
if
((
command
[
0
]
>>
5
)
==
6
||
(
command
[
0
]
>>
5
)
==
7
)
{
(
command
[
0
]
>>
5
)
==
7
)
{
s
=
12
;
/* vender specific */
s
=
12
;
/* vender specific */
...
@@ -137,9 +137,9 @@ static void print_commandk (unsigned char *command)
...
@@ -137,9 +137,9 @@ static void print_commandk (unsigned char *command)
printk
(
"
\n
"
);
printk
(
"
\n
"
);
}
}
static
void
show_command
(
Scsi_Cmnd
*
ptr
)
static
void
show_command
(
Scsi_Cmnd
*
SCpnt
)
{
{
print_commandk
(
ptr
->
cmnd
);
print_commandk
(
SCpnt
->
cmnd
);
}
}
static
void
show_busphase
(
unsigned
char
stat
)
static
void
show_busphase
(
unsigned
char
stat
)
...
@@ -260,3 +260,4 @@ static void nsp32_print_register(int base)
...
@@ -260,3 +260,4 @@ static void nsp32_print_register(int base)
}
}
}
}
/* end */
drivers/scsi/nsp32_io.h
View file @
e8f064c2
/*
/*
* Workbit NinjaSCSI-32Bi/UDE PCI/Card
b
us SCSI Host Bus Adapter driver
* Workbit NinjaSCSI-32Bi/UDE PCI/Card
B
us SCSI Host Bus Adapter driver
* I/O routine
* I/O routine
*
*
* This software may be used and distributed according to the terms of
* This software may be used and distributed according to the terms of
...
@@ -22,30 +22,30 @@ static inline unsigned char nsp32_read1(unsigned int base,
...
@@ -22,30 +22,30 @@ static inline unsigned char nsp32_read1(unsigned int base,
return
inb
(
base
+
index
);
return
inb
(
base
+
index
);
}
}
static
inline
void
nsp32_write2
(
unsigned
int
base
,
static
inline
void
nsp32_write2
(
unsigned
int
base
,
unsigned
int
index
,
unsigned
int
index
,
unsigned
short
val
)
unsigned
short
val
)
{
{
outw
(
cpu_to_le16
(
val
)
,
(
base
+
index
));
outw
(
val
,
(
base
+
index
));
}
}
static
inline
unsigned
short
nsp32_read2
(
unsigned
int
base
,
static
inline
unsigned
short
nsp32_read2
(
unsigned
int
base
,
unsigned
int
index
)
unsigned
int
index
)
{
{
return
le16_to_cpu
(
inw
(
base
+
index
)
);
return
inw
(
base
+
index
);
}
}
static
inline
void
nsp32_write4
(
unsigned
int
base
,
static
inline
void
nsp32_write4
(
unsigned
int
base
,
unsigned
int
index
,
unsigned
int
index
,
unsigned
long
val
)
unsigned
long
val
)
{
{
outl
(
cpu_to_le32
(
val
)
,
(
base
+
index
));
outl
(
val
,
(
base
+
index
));
}
}
static
inline
unsigned
long
nsp32_read4
(
unsigned
int
base
,
static
inline
unsigned
long
nsp32_read4
(
unsigned
int
base
,
unsigned
int
index
)
unsigned
int
index
)
{
{
return
le32_to_cpu
(
inl
(
base
+
index
)
);
return
inl
(
base
+
index
);
}
}
/*==============================================*/
/*==============================================*/
...
@@ -58,7 +58,7 @@ static inline void nsp32_mmio_write1(unsigned long base,
...
@@ -58,7 +58,7 @@ static inline void nsp32_mmio_write1(unsigned long base,
ptr
=
(
unsigned
char
*
)(
base
+
NSP32_MMIO_OFFSET
+
index
);
ptr
=
(
unsigned
char
*
)(
base
+
NSP32_MMIO_OFFSET
+
index
);
*
ptr
=
val
;
writeb
(
val
,
ptr
)
;
}
}
static
inline
unsigned
char
nsp32_mmio_read1
(
unsigned
long
base
,
static
inline
unsigned
char
nsp32_mmio_read1
(
unsigned
long
base
,
...
@@ -68,18 +68,18 @@ static inline unsigned char nsp32_mmio_read1(unsigned long base,
...
@@ -68,18 +68,18 @@ static inline unsigned char nsp32_mmio_read1(unsigned long base,
ptr
=
(
unsigned
char
*
)(
base
+
NSP32_MMIO_OFFSET
+
index
);
ptr
=
(
unsigned
char
*
)(
base
+
NSP32_MMIO_OFFSET
+
index
);
return
*
ptr
;
return
readb
(
ptr
)
;
}
}
static
inline
void
nsp32_mmio_write2
(
unsigned
long
base
,
static
inline
void
nsp32_mmio_write2
(
unsigned
long
base
,
unsigned
int
index
,
unsigned
int
index
,
unsigned
short
val
)
unsigned
short
val
)
{
{
volatile
unsigned
short
*
ptr
;
volatile
unsigned
short
*
ptr
;
ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
index
);
ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
index
);
*
ptr
=
cpu_to_le16
(
val
);
writew
(
cpu_to_le16
(
val
),
ptr
);
}
}
static
inline
unsigned
short
nsp32_mmio_read2
(
unsigned
long
base
,
static
inline
unsigned
short
nsp32_mmio_read2
(
unsigned
long
base
,
...
@@ -87,11 +87,9 @@ static inline unsigned short nsp32_mmio_read2(unsigned long base,
...
@@ -87,11 +87,9 @@ static inline unsigned short nsp32_mmio_read2(unsigned long base,
{
{
volatile
unsigned
short
*
ptr
;
volatile
unsigned
short
*
ptr
;
//printk(__FUNCTION__ "\n");
ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
index
);
ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
index
);
return
le16_to_cpu
(
*
ptr
);
return
le16_to_cpu
(
readw
(
ptr
)
);
}
}
static
inline
void
nsp32_mmio_write4
(
unsigned
long
base
,
static
inline
void
nsp32_mmio_write4
(
unsigned
long
base
,
...
@@ -102,7 +100,7 @@ static inline void nsp32_mmio_write4(unsigned long base,
...
@@ -102,7 +100,7 @@ static inline void nsp32_mmio_write4(unsigned long base,
ptr
=
(
unsigned
long
*
)(
base
+
NSP32_MMIO_OFFSET
+
index
);
ptr
=
(
unsigned
long
*
)(
base
+
NSP32_MMIO_OFFSET
+
index
);
*
ptr
=
cpu_to_le32
(
val
);
writel
(
cpu_to_le32
(
val
),
ptr
);
}
}
static
inline
unsigned
long
nsp32_mmio_read4
(
unsigned
long
base
,
static
inline
unsigned
long
nsp32_mmio_read4
(
unsigned
long
base
,
...
@@ -110,16 +108,12 @@ static inline unsigned long nsp32_mmio_read4(unsigned long base,
...
@@ -110,16 +108,12 @@ static inline unsigned long nsp32_mmio_read4(unsigned long base,
{
{
volatile
unsigned
long
*
ptr
;
volatile
unsigned
long
*
ptr
;
//printk(__FUNCTION__ "\n");
ptr
=
(
unsigned
long
*
)(
base
+
NSP32_MMIO_OFFSET
+
index
);
ptr
=
(
unsigned
long
*
)(
base
+
NSP32_MMIO_OFFSET
+
index
);
return
le32_to_cpu
(
*
ptr
);
return
le32_to_cpu
(
readl
(
ptr
)
);
}
}
/*==============================================*/
/*=============================================*/
static
inline
unsigned
char
nsp32_index_read1
(
unsigned
int
base
,
static
inline
unsigned
char
nsp32_index_read1
(
unsigned
int
base
,
unsigned
int
reg
)
unsigned
int
reg
)
...
@@ -132,7 +126,7 @@ static inline void nsp32_index_write1(unsigned int base,
...
@@ -132,7 +126,7 @@ static inline void nsp32_index_write1(unsigned int base,
unsigned
int
reg
,
unsigned
int
reg
,
unsigned
char
val
)
unsigned
char
val
)
{
{
outb
(
reg
,
base
+
INDEX_REG
);
outb
(
reg
,
base
+
INDEX_REG
);
outb
(
val
,
base
+
DATA_REG_LOW
);
outb
(
val
,
base
+
DATA_REG_LOW
);
}
}
...
@@ -140,15 +134,15 @@ static inline unsigned short nsp32_index_read2(unsigned int base,
...
@@ -140,15 +134,15 @@ static inline unsigned short nsp32_index_read2(unsigned int base,
unsigned
int
reg
)
unsigned
int
reg
)
{
{
outb
(
reg
,
base
+
INDEX_REG
);
outb
(
reg
,
base
+
INDEX_REG
);
return
le16_to_cpu
(
inw
(
base
+
DATA_REG_LOW
)
);
return
inw
(
base
+
DATA_REG_LOW
);
}
}
static
inline
void
nsp32_index_write2
(
unsigned
int
base
,
static
inline
void
nsp32_index_write2
(
unsigned
int
base
,
unsigned
int
reg
,
unsigned
int
reg
,
unsigned
short
val
)
unsigned
short
val
)
{
{
outb
(
reg
,
base
+
INDEX_REG
);
outb
(
reg
,
base
+
INDEX_REG
);
outw
(
cpu_to_le16
(
val
)
,
base
+
DATA_REG_LOW
);
outw
(
val
,
base
+
DATA_REG_LOW
);
}
}
static
inline
unsigned
long
nsp32_index_read4
(
unsigned
int
base
,
static
inline
unsigned
long
nsp32_index_read4
(
unsigned
int
base
,
...
@@ -157,8 +151,8 @@ static inline unsigned long nsp32_index_read4(unsigned int base,
...
@@ -157,8 +151,8 @@ static inline unsigned long nsp32_index_read4(unsigned int base,
unsigned
long
h
,
l
;
unsigned
long
h
,
l
;
outb
(
reg
,
base
+
INDEX_REG
);
outb
(
reg
,
base
+
INDEX_REG
);
l
=
le16_to_cpu
(
inw
(
base
+
DATA_REG_LOW
)
);
l
=
inw
(
base
+
DATA_REG_LOW
);
h
=
le16_to_cpu
(
inw
(
base
+
DATA_REG_HI
)
);
h
=
inw
(
base
+
DATA_REG_HI
);
return
((
h
<<
16
)
|
l
);
return
((
h
<<
16
)
|
l
);
}
}
...
@@ -170,15 +164,14 @@ static inline void nsp32_index_write4(unsigned int base,
...
@@ -170,15 +164,14 @@ static inline void nsp32_index_write4(unsigned int base,
unsigned
long
h
,
l
;
unsigned
long
h
,
l
;
h
=
(
val
&
0xffff0000
)
>>
16
;
h
=
(
val
&
0xffff0000
)
>>
16
;
l
=
(
val
&
0x0000ffff
)
>>
0
;
l
=
(
val
&
0x0000ffff
)
>>
0
;
outb
(
reg
,
base
+
INDEX_REG
);
outb
(
reg
,
base
+
INDEX_REG
);
outw
(
cpu_to_le16
(
l
),
base
+
DATA_REG_LOW
);
outw
(
l
,
base
+
DATA_REG_LOW
);
outw
(
cpu_to_le16
(
h
),
base
+
DATA_REG_HI
);
outw
(
h
,
base
+
DATA_REG_HI
);
}
}
/*==============================================*/
/* ===================================*/
static
inline
unsigned
char
nsp32_mmio_index_read1
(
unsigned
int
base
,
static
inline
unsigned
char
nsp32_mmio_index_read1
(
unsigned
int
base
,
unsigned
int
reg
)
unsigned
int
reg
)
...
@@ -188,13 +181,12 @@ static inline unsigned char nsp32_mmio_index_read1(unsigned int base,
...
@@ -188,13 +181,12 @@ static inline unsigned char nsp32_mmio_index_read1(unsigned int base,
index_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
INDEX_REG
);
index_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
INDEX_REG
);
data_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
DATA_REG_LOW
);
data_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
DATA_REG_LOW
);
*
index_ptr
=
reg
;
writeb
(
reg
,
index_ptr
);
return
readb
(
data_ptr
);
return
((
*
data_ptr
)
&
0xff
);
}
}
static
inline
void
nsp32_mmio_index_write1
(
unsigned
int
base
,
static
inline
void
nsp32_mmio_index_write1
(
unsigned
int
base
,
unsigned
int
reg
,
unsigned
int
reg
,
unsigned
char
val
)
unsigned
char
val
)
{
{
volatile
unsigned
short
*
index_ptr
,
*
data_ptr
;
volatile
unsigned
short
*
index_ptr
,
*
data_ptr
;
...
@@ -202,8 +194,8 @@ static inline void nsp32_mmio_index_write1(unsigned int base,
...
@@ -202,8 +194,8 @@ static inline void nsp32_mmio_index_write1(unsigned int base,
index_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
INDEX_REG
);
index_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
INDEX_REG
);
data_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
DATA_REG_LOW
);
data_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
DATA_REG_LOW
);
*
index_ptr
=
reg
;
writeb
(
reg
,
index_ptr
)
;
*
data_ptr
=
(
unsigned
short
)
val
;
writeb
(
val
,
data_ptr
)
;
}
}
static
inline
unsigned
short
nsp32_mmio_index_read2
(
unsigned
int
base
,
static
inline
unsigned
short
nsp32_mmio_index_read2
(
unsigned
int
base
,
...
@@ -214,13 +206,12 @@ static inline unsigned short nsp32_mmio_index_read2(unsigned int base,
...
@@ -214,13 +206,12 @@ static inline unsigned short nsp32_mmio_index_read2(unsigned int base,
index_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
INDEX_REG
);
index_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
INDEX_REG
);
data_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
DATA_REG_LOW
);
data_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
DATA_REG_LOW
);
*
index_ptr
=
reg
;
writeb
(
reg
,
index_ptr
);
return
le16_to_cpu
(
readw
(
data_ptr
));
return
le16_to_cpu
(
*
data_ptr
);
}
}
static
inline
void
nsp32_mmio_index_write2
(
unsigned
int
base
,
static
inline
void
nsp32_mmio_index_write2
(
unsigned
int
base
,
unsigned
int
reg
,
unsigned
int
reg
,
unsigned
short
val
)
unsigned
short
val
)
{
{
volatile
unsigned
short
*
index_ptr
,
*
data_ptr
;
volatile
unsigned
short
*
index_ptr
,
*
data_ptr
;
...
@@ -228,34 +219,33 @@ static inline void nsp32_mmio_index_write2(unsigned int base,
...
@@ -228,34 +219,33 @@ static inline void nsp32_mmio_index_write2(unsigned int base,
index_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
INDEX_REG
);
index_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
INDEX_REG
);
data_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
DATA_REG_LOW
);
data_ptr
=
(
unsigned
short
*
)(
base
+
NSP32_MMIO_OFFSET
+
DATA_REG_LOW
);
*
index_ptr
=
reg
;
writeb
(
reg
,
index_ptr
)
;
*
data_ptr
=
val
;
writew
(
cpu_to_le16
(
val
),
data_ptr
)
;
}
}
/*
-------------------------------------------------------------------
*/
/*
==============================================
*/
static
inline
void
nsp32_multi_read4
(
unsigned
int
BaseAddr
,
static
inline
void
nsp32_multi_read4
(
unsigned
int
base
,
unsigned
int
Register
,
unsigned
int
reg
,
void
*
buf
,
void
*
buf
,
unsigned
long
count
)
unsigned
long
count
)
{
{
insl
(
BaseAddr
+
Register
,
buf
,
count
);
insl
(
base
+
reg
,
buf
,
count
);
}
}
static
inline
void
nsp32_fifo_read
(
unsigned
int
base
,
static
inline
void
nsp32_fifo_read
(
unsigned
int
base
,
void
*
buf
,
void
*
buf
,
unsigned
long
count
)
unsigned
long
count
)
{
{
//DEBUG(0, __FUNCTION__ "() buf=0x%p, count=0x%lx*4\n", buf, count);
nsp32_multi_read4
(
base
,
FIFO_DATA_LOW
,
buf
,
count
);
nsp32_multi_read4
(
base
,
FIFO_DATA_LOW
,
buf
,
count
);
}
}
static
inline
void
nsp32_multi_write4
(
unsigned
int
BaseAddr
,
static
inline
void
nsp32_multi_write4
(
unsigned
int
base
,
unsigned
int
Register
,
unsigned
int
reg
,
void
*
buf
,
void
*
buf
,
unsigned
long
count
)
unsigned
long
count
)
{
{
outsl
(
BaseAddr
+
Register
,
buf
,
count
);
outsl
(
base
+
reg
,
buf
,
count
);
}
}
static
inline
void
nsp32_fifo_write
(
unsigned
int
base
,
static
inline
void
nsp32_fifo_write
(
unsigned
int
base
,
...
@@ -265,5 +255,5 @@ static inline void nsp32_fifo_write(unsigned int base,
...
@@ -265,5 +255,5 @@ static inline void nsp32_fifo_write(unsigned int base,
nsp32_multi_write4
(
base
,
FIFO_DATA_LOW
,
buf
,
count
);
nsp32_multi_write4
(
base
,
FIFO_DATA_LOW
,
buf
,
count
);
}
}
#endif
/* _NSP32_IO_H */
#endif
/* _NSP32_IO_H */
/* end */
/* end */
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