drm/amd/display: remove clocks_state enum

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc_link.c

@@ -1221,9 +1221,9 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
 
 	if (link_settings.link_rate == max_link_rate) {
 		if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) {
-			if (pipe_ctx->dis_clk->cur_min_clks_state < CLOCKS_STATE_NOMINAL)
+			if (pipe_ctx->dis_clk->cur_min_clks_state < DM_PP_CLOCKS_STATE_NOMINAL)
 				pipe_ctx->dis_clk->funcs->set_min_clocks_state(
-					pipe_ctx->dis_clk, CLOCKS_STATE_NOMINAL);
+					pipe_ctx->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL);
 		} else {
 		}
 	}

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

@@ -983,8 +983,7 @@ static bool construct(
 	 */
 	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
 		pool->base.display_clock->max_clks_state =
-			dce110_resource_convert_clock_state_pp_to_dc(
-					static_clk_info.max_clocks_state);
+					static_clk_info.max_clocks_state;
 	{
 		struct irq_service_init_data init_data;
 		init_data.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

@@ -1084,7 +1084,7 @@ static uint32_t get_max_pixel_clock_for_all_paths(
 static void apply_min_clocks(
 	struct core_dc *dc,
 	struct validate_context *context,
-	enum clocks_state *clocks_state,
+	enum dm_pp_clocks_state *clocks_state,
 	bool pre_mode_set)
 {
 	struct state_dependent_clocks req_clocks = {0};
@@ -1193,7 +1193,7 @@ enum dc_status dce110_apply_ctx_to_hw(
 	enum dc_status status;
 	int i;
 	bool programmed_audio_dto = false;
-	enum clocks_state clocks_state = CLOCKS_STATE_INVALID;
+	enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID;
 
 	/* Reset old context */
 	/* look up the targets that have been removed since last commit */

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

@@ -1188,47 +1188,6 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
 		1000);
 }
 
-enum clocks_state dce110_resource_convert_clock_state_pp_to_dc(
-	enum dm_pp_clocks_state pp_clock_state)
-{
-	enum clocks_state dc_clocks_state = CLOCKS_STATE_INVALID;
-
-	switch (pp_clock_state) {
-	case DM_PP_CLOCKS_STATE_INVALID:
-		dc_clocks_state = CLOCKS_STATE_INVALID;
-		break;
-	case DM_PP_CLOCKS_STATE_ULTRA_LOW:
-		dc_clocks_state = CLOCKS_STATE_ULTRA_LOW;
-		break;
-	case DM_PP_CLOCKS_STATE_LOW:
-		dc_clocks_state = CLOCKS_STATE_LOW;
-		break;
-	case DM_PP_CLOCKS_STATE_NOMINAL:
-		dc_clocks_state = CLOCKS_STATE_NOMINAL;
-		break;
-	case DM_PP_CLOCKS_STATE_PERFORMANCE:
-		dc_clocks_state = CLOCKS_STATE_PERFORMANCE;
-		break;
-	case DM_PP_CLOCKS_DPM_STATE_LEVEL_4:
-		dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_4;
-		break;
-	case DM_PP_CLOCKS_DPM_STATE_LEVEL_5:
-		dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_5;
-		break;
-	case DM_PP_CLOCKS_DPM_STATE_LEVEL_6:
-		dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_6;
-		break;
-	case DM_PP_CLOCKS_DPM_STATE_LEVEL_7:
-		dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_7;
-		break;
-	default:
-		dc_clocks_state = CLOCKS_STATE_INVALID;
-		break;
-	}
-
-	return dc_clocks_state;
-}
-
 const struct resource_caps *dce110_resource_cap(
 	struct hw_asic_id *asic_id)
 {
@@ -1314,8 +1273,7 @@ static bool construct(
 	 */
 	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
 		pool->base.display_clock->max_clks_state =
-			dce110_resource_convert_clock_state_pp_to_dc(
-					static_clk_info.max_clocks_state);
+				static_clk_info.max_clocks_state;
 
 	{
 		struct irq_service_init_data init_data;

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h

@@ -40,9 +40,6 @@ struct dce110_resource_pool {
 
 enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx);
 
-enum clocks_state dce110_resource_convert_clock_state_pp_to_dc(
-	enum dm_pp_clocks_state pp_clock_state);
-
 void dce110_resource_build_bit_depth_reduction_params(
 		const struct core_stream *stream,
 		struct bit_depth_reduction_params *fmt_bit_depth);

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c

@@ -1314,8 +1314,7 @@ static bool construct(
 	 */
 	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
 		pool->base.display_clock->max_clks_state =
-			dce110_resource_convert_clock_state_pp_to_dc(
-					static_clk_info.max_clocks_state);
+				static_clk_info.max_clocks_state;
 
 	{
 		struct irq_service_init_data init_data;

drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c

@@ -857,41 +857,41 @@ static const struct resource_funcs dce80_res_pool_funcs = {
 	.validate_bandwidth = dce80_validate_bandwidth
 };
 
-static enum clocks_state dce80_resource_convert_clock_state_pp_to_dc(
+static enum dm_pp_clocks_state dce80_resource_convert_clock_state_pp_to_dc(
 	enum dm_pp_clocks_state pp_clock_state)
 {
-	enum clocks_state dc_clocks_state = CLOCKS_STATE_INVALID;
+	enum dm_pp_clocks_state dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID;
 
 	switch (pp_clock_state) {
 	case DM_PP_CLOCKS_STATE_INVALID:
-		dc_clocks_state = CLOCKS_STATE_INVALID;
+		dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID;
 		break;
 	case DM_PP_CLOCKS_STATE_ULTRA_LOW:
-		dc_clocks_state = CLOCKS_STATE_ULTRA_LOW;
+		dc_clocks_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
 		break;
 	case DM_PP_CLOCKS_STATE_LOW:
-		dc_clocks_state = CLOCKS_STATE_LOW;
+		dc_clocks_state = DM_PP_CLOCKS_STATE_LOW;
 		break;
 	case DM_PP_CLOCKS_STATE_NOMINAL:
-		dc_clocks_state = CLOCKS_STATE_NOMINAL;
+		dc_clocks_state = DM_PP_CLOCKS_STATE_NOMINAL;
 		break;
 	case DM_PP_CLOCKS_STATE_PERFORMANCE:
-		dc_clocks_state = CLOCKS_STATE_PERFORMANCE;
+		dc_clocks_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
 		break;
 	case DM_PP_CLOCKS_DPM_STATE_LEVEL_4:
-		dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_4;
+		dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_4;
 		break;
 	case DM_PP_CLOCKS_DPM_STATE_LEVEL_5:
-		dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_5;
+		dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_5;
 		break;
 	case DM_PP_CLOCKS_DPM_STATE_LEVEL_6:
-		dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_6;
+		dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_6;
 		break;
 	case DM_PP_CLOCKS_DPM_STATE_LEVEL_7:
-		dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_7;
+		dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_7;
 		break;
 	default:
-		dc_clocks_state = CLOCKS_STATE_INVALID;
+		dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID;
 		break;
 	}
 

drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c

@@ -105,10 +105,10 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
 
 static bool dce110_set_min_clocks_state(
 	struct display_clock *dc,
-	enum clocks_state clocks_state)
+	enum dm_pp_clocks_state clocks_state)
 {
 	struct dm_pp_power_level_change_request level_change_req = {
-			DM_PP_POWER_LEVEL_INVALID};
+			clocks_state };
 
 	if (clocks_state > dc->max_clks_state) {
 		/*Requested state exceeds max supported state.*/
@@ -121,38 +121,6 @@ static bool dce110_set_min_clocks_state(
 		return true;
 	}
 
-	switch (clocks_state) {
-	case CLOCKS_STATE_ULTRA_LOW:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_ULTRA_LOW;
-		break;
-	case CLOCKS_STATE_LOW:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_LOW;
-		break;
-	case CLOCKS_STATE_NOMINAL:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_NOMINAL;
-		break;
-	case CLOCKS_STATE_PERFORMANCE:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE;
-		break;
-	case CLOCKS_DPM_STATE_LEVEL_4:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_4;
-		break;
-	case CLOCKS_DPM_STATE_LEVEL_5:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_5;
-		break;
-	case CLOCKS_DPM_STATE_LEVEL_6:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_6;
-		break;
-	case CLOCKS_DPM_STATE_LEVEL_7:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_7;
-		break;
-	case CLOCKS_STATE_INVALID:
-	default:
-		dm_logger_write(dc->ctx->logger, LOG_WARNING,
-				"Requested state invalid state");
-		return false;
-	}
-
 	/* get max clock state from PPLIB */
 	if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req))
 		dc->cur_min_clks_state = clocks_state;
@@ -274,27 +242,27 @@ static bool display_clock_integrated_info_construct(
 
 	/*update the maximum display clock for each power state*/
 	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-		enum clocks_state clk_state = CLOCKS_STATE_INVALID;
+		enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
 
 		switch (i) {
 		case 0:
-			clk_state = CLOCKS_STATE_ULTRA_LOW;
+			clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
 			break;
 
 		case 1:
-			clk_state = CLOCKS_STATE_LOW;
+			clk_state = DM_PP_CLOCKS_STATE_LOW;
 			break;
 
 		case 2:
-			clk_state = CLOCKS_STATE_NOMINAL;
+			clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
 			break;
 
 		case 3:
-			clk_state = CLOCKS_STATE_PERFORMANCE;
+			clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
 			break;
 
 		default:
-			clk_state = CLOCKS_STATE_INVALID;
+			clk_state = DM_PP_CLOCKS_STATE_INVALID;
 			break;
 		}
 
@@ -316,27 +284,27 @@ static bool display_clock_integrated_info_construct(
 	return true;
 }
 
-static enum clocks_state get_required_clocks_state(
+static enum dm_pp_clocks_state get_required_clocks_state(
 		struct display_clock *dc,
 		struct state_dependent_clocks *req_clocks)
 {
 	int32_t i;
 	struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc);
-	enum clocks_state low_req_clk = dc->max_clks_state;
+	enum dm_pp_clocks_state low_req_clk = dc->max_clks_state;
 
 	if (!req_clocks) {
 		/* NULL pointer*/
 		dm_logger_write(dc->ctx->logger, LOG_WARNING,
 				"%s: Invalid parameter",
 				__func__);
-		return CLOCKS_STATE_INVALID;
+		return DM_PP_CLOCKS_STATE_INVALID;
 	}
 
 	/* Iterate from highest supported to lowest valid state, and update
 	 * lowest RequiredState with the lowest state that satisfies
 	 * all required clocks
 	 */
-	for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
+	for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) {
 		if ((req_clocks->display_clk_khz <=
 			max_clks_by_state[i].display_clk_khz) &&
 			(req_clocks->pixel_clk_khz <=
@@ -420,7 +388,7 @@ static void dce110_set_clock(
 	/* from power down, we need mark the clock state as ClocksStateNominal
 	 * from HWReset, so when resume we will call pplib voltage regulator.*/
 	if (requested_clk_khz == 0)
-		base->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
+		base->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
 
 	psr_wait_loop(base->ctx, requested_clk_khz);
 }
@@ -444,7 +412,7 @@ static bool dal_display_clock_dce110_construct(
 	dc_base->ctx = ctx;
 	dc_base->min_display_clk_threshold_khz = 0;
 
-	dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
+	dc_base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
 
 	dc_base->funcs = &funcs;
 
@@ -462,7 +430,7 @@ static bool dal_display_clock_dce110_construct(
  * via a pplib call to DAL IRI eventually calling a
  * DisplayEngineClock_Dce110::StoreMaxClocksState().  This call will come in
  * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
-	dc_base->max_clks_state = CLOCKS_STATE_NOMINAL;
+	dc_base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
 
 	dal_divider_range_construct(
 		&divider_ranges[DIVIDER_RANGE_01],

drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c

@@ -75,10 +75,10 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
 
 static bool dce112_set_min_clocks_state(
 	struct display_clock *dc,
-	enum clocks_state clocks_state)
+	enum dm_pp_clocks_state clocks_state)
 {
 	struct dm_pp_power_level_change_request level_change_req = {
-			DM_PP_POWER_LEVEL_INVALID };
+			clocks_state };
 
 	if (clocks_state > dc->max_clks_state) {
 		/*Requested state exceeds max supported state.*/
@@ -91,38 +91,6 @@ static bool dce112_set_min_clocks_state(
 		return true;
 	}
 
-	switch (clocks_state) {
-	case CLOCKS_STATE_ULTRA_LOW:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_ULTRA_LOW;
-		break;
-	case CLOCKS_STATE_LOW:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_LOW;
-		break;
-	case CLOCKS_STATE_NOMINAL:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_NOMINAL;
-		break;
-	case CLOCKS_STATE_PERFORMANCE:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE;
-		break;
-	case CLOCKS_DPM_STATE_LEVEL_4:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_4;
-		break;
-	case CLOCKS_DPM_STATE_LEVEL_5:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_5;
-		break;
-	case CLOCKS_DPM_STATE_LEVEL_6:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_6;
-		break;
-	case CLOCKS_DPM_STATE_LEVEL_7:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_7;
-		break;
-	case CLOCKS_STATE_INVALID:
-	default:
-		dm_logger_write(dc->ctx->logger, LOG_WARNING,
-				"Requested state invalid state");
-		return false;
-	}
-
 	/* get max clock state from PPLIB */
 	if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req))
 		dc->cur_min_clks_state = clocks_state;
@@ -229,27 +197,27 @@ static bool display_clock_integrated_info_construct(
 
 	/*update the maximum display clock for each power state*/
 	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-		enum clocks_state clk_state = CLOCKS_STATE_INVALID;
+		enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
 
 		switch (i) {
 		case 0:
-			clk_state = CLOCKS_STATE_ULTRA_LOW;
+			clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
 			break;
 
 		case 1:
-			clk_state = CLOCKS_STATE_LOW;
+			clk_state = DM_PP_CLOCKS_STATE_LOW;
 			break;
 
 		case 2:
-			clk_state = CLOCKS_STATE_NOMINAL;
+			clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
 			break;
 
 		case 3:
-			clk_state = CLOCKS_STATE_PERFORMANCE;
+			clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
 			break;
 
 		default:
-			clk_state = CLOCKS_STATE_INVALID;
+			clk_state = DM_PP_CLOCKS_STATE_INVALID;
 			break;
 		}
 
@@ -265,27 +233,27 @@ static bool display_clock_integrated_info_construct(
 	return true;
 }
 
-enum clocks_state dispclk_dce112_get_required_clocks_state(
+enum dm_pp_clocks_state dispclk_dce112_get_required_clocks_state(
 	struct display_clock *dc,
 	struct state_dependent_clocks *req_clocks)
 {
 	int32_t i;
 	struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc);
-	enum clocks_state low_req_clk = dc->max_clks_state;
+	enum dm_pp_clocks_state low_req_clk = dc->max_clks_state;
 
 	if (!req_clocks) {
 		/* NULL pointer*/
 		dm_logger_write(dc->ctx->logger, LOG_WARNING,
 				"%s: Invalid parameter",
 				__func__);
-		return CLOCKS_STATE_INVALID;
+		return DM_PP_CLOCKS_STATE_INVALID;
 	}
 
 	/* Iterate from highest supported to lowest valid state, and update
 	 * lowest RequiredState with the lowest state that satisfies
 	 * all required clocks
 	 */
-	for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
+	for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) {
 		if ((req_clocks->display_clk_khz <=
 				(disp_clk->max_clks_by_state + i)->
 					display_clk_khz) &&
@@ -321,7 +289,7 @@ void dce112_set_clock(
 	/* from power down, we need mark the clock state as ClocksStateNominal
 	 * from HWReset, so when resume we will call pplib voltage regulator.*/
 	if (requested_clk_khz == 0)
-		base->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
+		base->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
 
 	/*Program DP ref Clock*/
 	/*VBIOS will determine DPREFCLK frequency, so we don't set it*/
@@ -351,7 +319,7 @@ bool dal_display_clock_dce112_construct(
 	dc_base->ctx = ctx;
 	dc_base->min_display_clk_threshold_khz = 0;
 
-	dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
+	dc_base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
 
 	dc_base->funcs = &funcs;
 
@@ -369,7 +337,7 @@ bool dal_display_clock_dce112_construct(
  * via a pplib call to DAL IRI eventually calling a
  * DisplayEngineClock_dce112::StoreMaxClocksState().  This call will come in
  * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
-	dc_base->max_clks_state = CLOCKS_STATE_NOMINAL;
+	dc_base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
 
 	dc112->disp_clk_base.min_display_clk_threshold_khz =
 			(dc112->dentist_vco_freq_khz / 62);

drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h

@@ -71,10 +71,10 @@ bool dal_display_clock_dce112_construct(
 
 void dispclk_dce112_destroy(struct display_clock **base);
 
-enum clocks_state dispclk_dce112_get_min_clocks_state(
+enum dm_pp_clocks_state dispclk_dce112_get_min_clocks_state(
 	struct display_clock *base);
 
-enum clocks_state dispclk_dce112_get_required_clocks_state(
+enum dm_pp_clocks_state dispclk_dce112_get_required_clocks_state(
 	struct display_clock *dc,
 	struct state_dependent_clocks *req_clocks);
 
@@ -84,10 +84,10 @@ void dce112_set_clock(
 
 bool dispclk_dce112_set_min_clocks_state(
 	struct display_clock *base,
-	enum clocks_state clocks_state);
+	enum dm_pp_clocks_state clocks_state);
 
 void dispclk_dce112_store_max_clocks_state(
 	struct display_clock *base,
-	enum clocks_state max_clocks_state);
+	enum dm_pp_clocks_state max_clocks_state);
 
 #endif /* __DAL_DISPLAY_CLOCK_DCE112_H__ */

drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c

@@ -108,27 +108,27 @@ static void dce80_set_clock(
 	/* from power down, we need mark the clock state as ClocksStateNominal
 	 * from HWReset, so when resume we will call pplib voltage regulator.*/
 	if (requested_clk_khz == 0)
-		dc->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
+		dc->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
 }
 
-static enum clocks_state get_required_clocks_state
+static enum dm_pp_clocks_state get_required_clocks_state
 	(struct display_clock *dc,
 	struct state_dependent_clocks *req_clocks)
 {
 	int32_t i;
-	enum clocks_state low_req_clk = dc->max_clks_state;
+	enum dm_pp_clocks_state low_req_clk = dc->max_clks_state;
 
 	if (!req_clocks) {
 		/* NULL pointer*/
 		BREAK_TO_DEBUGGER();
-		return CLOCKS_STATE_INVALID;
+		return DM_PP_CLOCKS_STATE_INVALID;
 	}
 
 	/* Iterate from highest supported to lowest valid state, and update
 	 * lowest RequiredState with the lowest state that satisfies
 	 * all required clocks
 	 */
-	for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
+	for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) {
 		if ((req_clocks->display_clk_khz <=
 			max_clks_by_state[i].display_clk_khz) &&
 			(req_clocks->pixel_clk_khz <=
@@ -140,10 +140,10 @@ static enum clocks_state get_required_clocks_state
 
 static bool dce80_set_min_clocks_state(
 	struct display_clock *dc,
-	enum clocks_state clocks_state)
+	enum dm_pp_clocks_state clocks_state)
 {
 	struct dm_pp_power_level_change_request level_change_req = {
-			DM_PP_POWER_LEVEL_INVALID };
+			clocks_state };
 
 	if (clocks_state > dc->max_clks_state) {
 		/*Requested state exceeds max supported state.*/
@@ -156,38 +156,6 @@ static bool dce80_set_min_clocks_state(
 		return true;
 	}
 
-	switch (clocks_state) {
-	case CLOCKS_STATE_ULTRA_LOW:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_ULTRA_LOW;
-		break;
-	case CLOCKS_STATE_LOW:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_LOW;
-		break;
-	case CLOCKS_STATE_NOMINAL:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_NOMINAL;
-		break;
-	case CLOCKS_STATE_PERFORMANCE:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE;
-		break;
-	case CLOCKS_DPM_STATE_LEVEL_4:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_4;
-		break;
-	case CLOCKS_DPM_STATE_LEVEL_5:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_5;
-		break;
-	case CLOCKS_DPM_STATE_LEVEL_6:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_6;
-		break;
-	case CLOCKS_DPM_STATE_LEVEL_7:
-		level_change_req.power_level = DM_PP_POWER_LEVEL_7;
-		break;
-	case CLOCKS_STATE_INVALID:
-	default:
-		dm_logger_write(dc->ctx->logger, LOG_WARNING,
-				"Requested state invalid state");
-		return false;
-	}
-
 	/* get max clock state from PPLIB */
 	if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req))
 		dc->cur_min_clks_state = clocks_state;
@@ -326,27 +294,27 @@ static bool display_clock_integrated_info_construct(
 
 	/*update the maximum display clock for each power state*/
 	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-		enum clocks_state clk_state = CLOCKS_STATE_INVALID;
+		enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
 
 		switch (i) {
 		case 0:
-			clk_state = CLOCKS_STATE_ULTRA_LOW;
+			clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
 			break;
 
 		case 1:
-			clk_state = CLOCKS_STATE_LOW;
+			clk_state = DM_PP_CLOCKS_STATE_LOW;
 			break;
 
 		case 2:
-			clk_state = CLOCKS_STATE_NOMINAL;
+			clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
 			break;
 
 		case 3:
-			clk_state = CLOCKS_STATE_PERFORMANCE;
+			clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
 			break;
 
 		default:
-			clk_state = CLOCKS_STATE_INVALID;
+			clk_state = DM_PP_CLOCKS_STATE_INVALID;
 			break;
 		}
 
@@ -402,7 +370,7 @@ struct display_clock *dal_display_clock_dce80_create(
 	dc_base->ctx = ctx;
 	dc_base->min_display_clk_threshold_khz = 0;
 
-	dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
+	dc_base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
 
 	dc_base->funcs = &funcs;
 	/*
@@ -423,12 +391,12 @@ struct display_clock *dal_display_clock_dce80_create(
  * via a pplib call to DAL IRI eventually calling a
  * DisplayEngineClock_Dce50::StoreMaxClocksState().  This call will come in
  * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
-	dc_base->max_clks_state = CLOCKS_STATE_NOMINAL;
+	dc_base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
 /* Initially set current min clocks state to invalid since we
  * cannot make any assumption about PPLIB's initial state. This will be updated
  * by HWSS via SetMinClocksState() on first mode set prior to programming
  * state dependent clocks.*/
-	disp_clk->cur_min_clks_state = CLOCKS_STATE_INVALID;
+	disp_clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
 
 	display_clock_ss_construct(disp_clk);
 

drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h

@@ -38,7 +38,7 @@ struct display_clock_dce80 {
 	/* Flag for Enabled SS on GPU PLL*/
 	bool ss_on_gpu_pll;
 	/* Current minimum display block clocks state*/
-	enum clocks_state cur_min_clks_state;
+	enum dm_pp_clocks_state cur_min_clks_state;
 	/* DFS-bypass feature variable
 	 Cache the status of DFS-bypass feature*/
 	bool dfs_bypass_enabled;

drivers/gpu/drm/amd/display/include/display_clock_interface.h

@@ -26,29 +26,11 @@
 #ifndef __DISPLAY_CLOCK_INTERFACE_H__
 #define __DISPLAY_CLOCK_INTERFACE_H__
 
+#include "dm_services_types.h"
 #include "hw_sequencer_types.h"
 #include "grph_object_defs.h"
 #include "signal_types.h"
 
-/* Enumeration of all clocks states */
-enum clocks_state {
-	CLOCKS_STATE_INVALID = 0,
-	CLOCKS_STATE_ULTRA_LOW,
-	CLOCKS_STATE_LOW,
-	CLOCKS_STATE_NOMINAL,
-	CLOCKS_STATE_PERFORMANCE,
-	/* Starting from DCE11, Max 8 level DPM state supported */
-	CLOCKS_DPM_STATE_LEVEL_INVALID = CLOCKS_STATE_INVALID,
-	CLOCKS_DPM_STATE_LEVEL_0 = CLOCKS_STATE_ULTRA_LOW,
-	CLOCKS_DPM_STATE_LEVEL_1 = CLOCKS_STATE_LOW,
-	CLOCKS_DPM_STATE_LEVEL_2 = CLOCKS_STATE_NOMINAL,
-	CLOCKS_DPM_STATE_LEVEL_3 = CLOCKS_STATE_PERFORMANCE,
-	CLOCKS_DPM_STATE_LEVEL_4 = CLOCKS_DPM_STATE_LEVEL_3 + 1,
-	CLOCKS_DPM_STATE_LEVEL_5 = CLOCKS_DPM_STATE_LEVEL_4 + 1,
-	CLOCKS_DPM_STATE_LEVEL_6 = CLOCKS_DPM_STATE_LEVEL_5 + 1,
-	CLOCKS_DPM_STATE_LEVEL_7 = CLOCKS_DPM_STATE_LEVEL_6 + 1,
-};
-
 /* Structure containing all state-dependent clocks
  * (dependent on "enum clocks_state") */
 struct state_dependent_clocks {
@@ -61,20 +43,20 @@ struct display_clock {
 	const struct display_clock_funcs *funcs;
 	uint32_t min_display_clk_threshold_khz;
 	/* Max display block clocks state*/
-	enum clocks_state max_clks_state;
+	enum dm_pp_clocks_state max_clks_state;
 
-	enum clocks_state cur_min_clks_state;
+	enum dm_pp_clocks_state cur_min_clks_state;
 };
 
 struct display_clock_funcs {
 	void (*destroy)(struct display_clock **to_destroy);
 	void (*set_clock)(struct display_clock *disp_clk,
 		uint32_t requested_clock_khz);
-	enum clocks_state (*get_required_clocks_state)(
+	enum dm_pp_clocks_state (*get_required_clocks_state)(
 		struct display_clock *disp_clk,
 		struct state_dependent_clocks *req_clocks);
 	bool (*set_min_clocks_state)(struct display_clock *disp_clk,
-		enum clocks_state clocks_state);
+		enum dm_pp_clocks_state dm_pp_clocks_state);
 	uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
 
 };