Commit ebbfabc1 authored by Derek Fang's avatar Derek Fang Committed by Mark Brown

ASoC: rt5682: Add CCF usage for providing I2S clks

There is a need to use RT5682 as DAI clock master for other codecs
within a platform, which means that the DAI clocks are required to
remain, regardless of whether the RT5682 is actually running
playback/capture.

The RT5682 CCF basic functions are implemented almost by the existing
internal functions and asoc apis. It needs a clk provider (rt5682 mclk)
to generate the bclk and wclk outputs.

The RT5682 CCF supports and restricts as below:
1. Fmt of DAI-AIF1 must be configured to master before using CCF.
2. Only accept a 48MHz clk as the clk provider.
3. Only provide a 48kHz wclk and a set of multiples of wclk as bclk.

There are some temporary limitations in this patch until a better
implementation.
Signed-off-by: default avatarDerek Fang <derek.fang@realtek.com>
Link: https://lore.kernel.org/r/1582033912-6841-1-git-send-email-derek.fang@realtek.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 70368106
...@@ -24,6 +24,12 @@ enum rt5682_jd_src { ...@@ -24,6 +24,12 @@ enum rt5682_jd_src {
RT5682_JD1, RT5682_JD1,
}; };
enum rt5682_dai_clks {
RT5682_DAI_WCLK_IDX,
RT5682_DAI_BCLK_IDX,
RT5682_DAI_NUM_CLKS,
};
struct rt5682_platform_data { struct rt5682_platform_data {
int ldo1_en; /* GPIO for LDO1_EN */ int ldo1_en; /* GPIO for LDO1_EN */
...@@ -32,6 +38,8 @@ struct rt5682_platform_data { ...@@ -32,6 +38,8 @@ struct rt5682_platform_data {
enum rt5682_dmic1_clk_pin dmic1_clk_pin; enum rt5682_dmic1_clk_pin dmic1_clk_pin;
enum rt5682_jd_src jd_src; enum rt5682_jd_src jd_src;
unsigned int btndet_delay; unsigned int btndet_delay;
const char *dai_clk_names[RT5682_DAI_NUM_CLKS];
}; };
#endif #endif
......
This diff is collapsed.
...@@ -841,8 +841,8 @@ ...@@ -841,8 +841,8 @@
#define RT5682_TDM_M_LP_INV (0x1 << 1) #define RT5682_TDM_M_LP_INV (0x1 << 1)
#define RT5682_TDM_MS_MASK (0x1 << 0) #define RT5682_TDM_MS_MASK (0x1 << 0)
#define RT5682_TDM_MS_SFT 0 #define RT5682_TDM_MS_SFT 0
#define RT5682_TDM_MS_M (0x0 << 0) #define RT5682_TDM_MS_S (0x0 << 0)
#define RT5682_TDM_MS_S (0x1 << 0) #define RT5682_TDM_MS_M (0x1 << 0)
/* Global Clock Control (0x0080) */ /* Global Clock Control (0x0080) */
#define RT5682_SCLK_SRC_MASK (0x7 << 13) #define RT5682_SCLK_SRC_MASK (0x7 << 13)
......
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