ARM: dts: uniphier: add SoC-Glue node to UniPhier 32bit SoCs

This node consists of various system-level configuration registers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

arch/arm/boot/dts/uniphier-common32.dtsi

@@ -136,9 +136,13 @@ intc: interrupt-controller@60001000 {
 			interrupt-controller;
 		};
 
-		pinctrl: pinctrl@5f801000 {
+		soc-glue@5f800000 {
+			compatible = "simple-mfd", "syscon";
+			reg = <0x5f800000 0x2000>;
+
+			pinctrl: pinctrl {
 				 /* specify compatible in each SoC DTSI */
-			reg = <0x5f801000 0xe00>;
+			};
 		};
 	};
 };

arch/arm/boot/dts/uniphier-ph1-ld4.dtsi

@@ -182,5 +182,5 @@ &serial3 {
 };
 
 &pinctrl {
-	compatible = "socionext,ph1-ld4-pinctrl", "syscon";
+	compatible = "socionext,uniphier-ld4-pinctrl";
 };

arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi

@@ -63,5 +63,5 @@ &serial3 {
  * which makes the pinctrl driver unshareable.
  */
 &pinctrl {
-	compatible = "socionext,ph1-ld6b-pinctrl", "syscon";
+	compatible = "socionext,uniphier-ld6b-pinctrl";
 };

arch/arm/boot/dts/uniphier-ph1-pro4.dtsi

@@ -200,5 +200,5 @@ &refclk {
 };
 
 &pinctrl {
-	compatible = "socionext,ph1-pro4-pinctrl", "syscon";
+	compatible = "socionext,uniphier-pro4-pinctrl";
 };

arch/arm/boot/dts/uniphier-ph1-pro5.dtsi

@@ -194,5 +194,5 @@ &refclk {
 };
 
 &pinctrl {
-	compatible = "socionext,ph1-pro5-pinctrl", "syscon";
+	compatible = "socionext,uniphier-pro5-pinctrl";
 };

arch/arm/boot/dts/uniphier-ph1-sld8.dtsi

@@ -181,5 +181,5 @@ &serial3 {
 };
 
 &pinctrl {
-	compatible = "socionext,ph1-sld8-pinctrl", "syscon";
+	compatible = "socionext,uniphier-sld8-pinctrl";
 };

arch/arm/boot/dts/uniphier-proxstream2.dtsi

@@ -205,5 +205,5 @@ &refclk {
 };
 
 &pinctrl {
-	compatible = "socionext,proxstream2-pinctrl", "syscon";
+	compatible = "socionext,uniphier-pxs2-pinctrl";
 };