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Commit ec97489d authored by Tony Lindgren's avatar Tony Lindgren
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omap: Move dmtimer defines to dmtimer.h 

These will be needed when dmtimer platform init code gets split
for omap1 and omap2+. These will also be needed for separate
sys_timer init and driver init for the rest of the hardware timers
in the following patches. No functional changes.
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Reviewed-by: default avatarKevin Hilman <khilman@ti.com>
parent e74984e4
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Showing with 125 additions and 121 deletions
arch/arm/plat-omap/dmtimer.c
View file @ ec97489d
...@@ -41,127 +41,6 @@ ...@@ -41,127 +41,6 @@
#include <plat/dmtimer.h> #include <plat/dmtimer.h>
#include <mach/irqs.h> #include <mach/irqs.h>
/* register offsets */
#define _OMAP_TIMER_ID_OFFSET 0x00
#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
#define _OMAP_TIMER_STAT_OFFSET 0x18
#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
#define _OMAP_TIMER_CTRL_OFFSET 0x24
#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
#define OMAP_TIMER_CTRL_PT (1 << 12)
#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
#define OMAP_TIMER_CTRL_POSTED (1 << 2)
#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
#define _OMAP_TIMER_COUNTER_OFFSET 0x28
#define _OMAP_TIMER_LOAD_OFFSET 0x2c
#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
#define WP_NONE 0 /* no write pending bit */
#define WP_TCLR (1 << 0)
#define WP_TCRR (1 << 1)
#define WP_TLDR (1 << 2)
#define WP_TTGR (1 << 3)
#define WP_TMAR (1 << 4)
#define WP_TPIR (1 << 5)
#define WP_TNIR (1 << 6)
#define WP_TCVR (1 << 7)
#define WP_TOCR (1 << 8)
#define WP_TOWR (1 << 9)
#define _OMAP_TIMER_MATCH_OFFSET 0x38
#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
/* register offsets with the write pending bit encoded */
#define WPSHIFT 16
#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
| (WP_TCLR << WPSHIFT))
#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
| (WP_TCRR << WPSHIFT))
#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
| (WP_TLDR << WPSHIFT))
#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
| (WP_TTGR << WPSHIFT))
#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
| (WP_TMAR << WPSHIFT))
#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
| (WP_TPIR << WPSHIFT))
#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
| (WP_TNIR << WPSHIFT))
#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
| (WP_TCVR << WPSHIFT))
#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
struct omap_dm_timer {
unsigned long phys_base;
int irq;
#ifdef CONFIG_ARCH_OMAP2PLUS
struct clk *iclk, *fclk;
#endif
void __iomem *io_base;
unsigned reserved:1;
unsigned enabled:1;
unsigned posted:1;
};
static int dm_timer_count; static int dm_timer_count;
#ifdef CONFIG_ARCH_OMAP1 #ifdef CONFIG_ARCH_OMAP1
......
arch/arm/plat-omap/include/plat/dmtimer.h
View file @ ec97489d
...@@ -92,5 +92,130 @@ void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value ...@@ -92,5 +92,130 @@ void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value
int omap_dm_timers_active(void); int omap_dm_timers_active(void);
/*
* Do not use the defines below, they are not needed. They should be only
* used by dmtimer.c and sys_timer related code.
*/
/* register offsets */
#define _OMAP_TIMER_ID_OFFSET 0x00
#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
#define _OMAP_TIMER_STAT_OFFSET 0x18
#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
#define _OMAP_TIMER_CTRL_OFFSET 0x24
#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
#define OMAP_TIMER_CTRL_PT (1 << 12)
#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
#define OMAP_TIMER_CTRL_POSTED (1 << 2)
#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
#define _OMAP_TIMER_COUNTER_OFFSET 0x28
#define _OMAP_TIMER_LOAD_OFFSET 0x2c
#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
#define WP_NONE 0 /* no write pending bit */
#define WP_TCLR (1 << 0)
#define WP_TCRR (1 << 1)
#define WP_TLDR (1 << 2)
#define WP_TTGR (1 << 3)
#define WP_TMAR (1 << 4)
#define WP_TPIR (1 << 5)
#define WP_TNIR (1 << 6)
#define WP_TCVR (1 << 7)
#define WP_TOCR (1 << 8)
#define WP_TOWR (1 << 9)
#define _OMAP_TIMER_MATCH_OFFSET 0x38
#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
/* register offsets with the write pending bit encoded */
#define WPSHIFT 16
#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
| (WP_TCLR << WPSHIFT))
#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
| (WP_TCRR << WPSHIFT))
#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
| (WP_TLDR << WPSHIFT))
#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
| (WP_TTGR << WPSHIFT))
#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
| (WP_TMAR << WPSHIFT))
#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
| (WP_NONE << WPSHIFT))
#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
| (WP_TPIR << WPSHIFT))
#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
| (WP_TNIR << WPSHIFT))
#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
| (WP_TCVR << WPSHIFT))
#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
struct omap_dm_timer {
unsigned long phys_base;
int irq;
#ifdef CONFIG_ARCH_OMAP2PLUS
struct clk *iclk, *fclk;
#endif
void __iomem *io_base;
unsigned reserved:1;
unsigned enabled:1;
unsigned posted:1;
};
#endif /* __ASM_ARCH_DMTIMER_H */ #endif /* __ASM_ARCH_DMTIMER_H */
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