Commit eca05f00 authored by Elaine Zhang's avatar Elaine Zhang Committed by Heiko Stuebner

clk: rockchip: fix up the pll clks error for rv1108 SoC

fix up the lock_shift describe error.
remove the ROCKCHIP_PLL_SYNC_RATE flag for gpll.
Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: default avatarAndy Yan <andy.yan@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent d00b4d94
......@@ -148,11 +148,11 @@ PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" };
static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0),
RV1108_PLL_CON(3), 8, 31, 0, rv1108_pll_rates),
RV1108_PLL_CON(3), 8, 0, 0, rv1108_pll_rates),
[dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8),
RV1108_PLL_CON(11), 8, 31, 0, NULL),
RV1108_PLL_CON(11), 8, 1, 0, NULL),
[gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16),
RV1108_PLL_CON(19), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rv1108_pll_rates),
RV1108_PLL_CON(19), 8, 2, 0, rv1108_pll_rates),
};
#define MFLAGS CLK_MUX_HIWORD_MASK
......
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