Merge bk://ppc.bkbits.net/for-linus-ppc

into ppc970.osdl.org:/home/torvalds/v2.6/linux

Documentation/powerpc/mpc52xx.txt

 Linux 2.6.x on MPC52xx family
 -----------------------------
 
-For the latest info, go to http://www.246tNt.com/mpc52xx/state.txt
+For the latest info, go to http://www.246tNt.com/mpc52xx/
  
 To compile/use :
 
@@ -37,12 +37,3 @@ Some remarks :
  - Of course, I inspired myself from the 2.4 port. If you think I forgot to
    mention you/your company in the copyright of some code, I'll correct it
    ASAP.
- - The codes wants the MBAR to be set at 0xf0000000 by the bootloader. It's
-   mapped 1:1 with the MMU. If for whatever reason, you want to change this,
-   beware that some code depends on the 0xf0000000 address and other depends
-   on the 1:1 mapping.
- - Most of the code assumes that port multiplexing, frequency selection, ...
-   has already been done. IMHO this should be done as early as possible, in
-   the bootloader. If for whatever reason you can't do it there, do it in the
-   platform setup code (if U-Boot) or in the arch/ppc/boot/simple/... (if
-   DBug)

MAINTAINERS

@@ -1301,6 +1301,15 @@ W:	http://www.penguinppc.org/
 L:	linuxppc-dev@lists.linuxppc.org
 S:	Maintained
 
+LINUX FOR POWERPC EMBEDDED MPC52XX
+P:	Sylvain Munaut
+M:	tnt@246tNt.com
+W:	http://www.246tNt.com/mpc52xx/
+W:	http://www.penguinppc.org/
+L:	linuxppc-dev@ozlabs.org
+L:	linuxppc-embedded@ozlabs.org
+S:	Maintained
+
 LINUX FOR POWERPC EMBEDDED PPC4XX
 P:	Matt Porter
 M:	mporter@kernel.crashing.org

arch/ppc/boot/simple/misc.c

@@ -48,7 +48,9 @@
  * Val Henson has requested that Gemini doesn't wait for the
  * user to edit the cmdline or not.
  */
-#if (defined(CONFIG_SERIAL_8250_CONSOLE) || defined(CONFIG_VGA_CONSOLE)) \
+#if (defined(CONFIG_SERIAL_8250_CONSOLE) \
+	|| defined(CONFIG_VGA_CONSOLE) \
+	|| defined(CONFIG_SERIAL_MPC52xx_CONSOLE)) \
 	&& !defined(CONFIG_GEMINI)
 #define INTERACTIVE_CONSOLE	1
 #endif

arch/ppc/kernel/cputable.c

@@ -63,6 +63,17 @@ extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spe
 #define CPU_FTR_COMMON                  0
 #endif
 
+/* The powersave features NAP & DOZE seems to confuse BDI when
+   debugging. So if a BDI is used, disable theses
+ */
+#ifndef CONFIG_BDI_SWITCH
+#define CPU_FTR_MAYBE_CAN_DOZE	CPU_FTR_CAN_DOZE
+#define CPU_FTR_MAYBE_CAN_NAP	CPU_FTR_CAN_NAP
+#else
+#define CPU_FTR_MAYBE_CAN_DOZE	0
+#define CPU_FTR_MAYBE_CAN_NAP	0
+#endif
+
 struct cpu_spec	cpu_specs[] = {
 #if CLASSIC_PPC
     { 	/* 601 */
@@ -76,8 +87,8 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 603 */
     	0xffff0000, 0x00030000, "603",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-    	CPU_FTR_CAN_NAP,
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+    	CPU_FTR_MAYBE_CAN_NAP,
 	COMMON_PPC,
     	32, 32,
 	__setup_cpu_603
@@ -85,8 +96,8 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 603e */
     	0xffff0000, 0x00060000, "603e",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-    	CPU_FTR_CAN_NAP,
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+    	CPU_FTR_MAYBE_CAN_NAP,
 	COMMON_PPC,
 	32, 32,
 	__setup_cpu_603
@@ -94,8 +105,8 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 603ev */
     	0xffff0000, 0x00070000, "603ev",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-    	CPU_FTR_CAN_NAP,
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+    	CPU_FTR_MAYBE_CAN_NAP,
 	COMMON_PPC,
 	32, 32,
 	__setup_cpu_603
@@ -139,8 +150,8 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 740/750 (0x4202, don't support TAU ?) */
     	0xffffffff, 0x00084202, "740/750",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-	CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+	CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 	COMMON_PPC,
 	32, 32,
 	__setup_cpu_750
@@ -148,8 +159,8 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 745/755 */
     	0xfffff000, 0x00083000, "745/755",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 	COMMON_PPC,
 	32, 32,
 	__setup_cpu_750
@@ -157,8 +168,8 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 750CX (80100 and 8010x?) */
     	0xfffffff0, 0x00080100, "750CX",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 	COMMON_PPC,
 	32, 32,
 	__setup_cpu_750cx
@@ -166,8 +177,8 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 750CX (82201 and 82202) */
     	0xfffffff0, 0x00082200, "750CX",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 	COMMON_PPC,
 	32, 32,
 	__setup_cpu_750cx
@@ -175,8 +186,8 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 750CXe (82214) */
     	0xfffffff0, 0x00082210, "750CXe",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 	COMMON_PPC,
 	32, 32,
 	__setup_cpu_750cx
@@ -184,8 +195,8 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 750FX rev 1.x */
     	0xffffff00, 0x70000100, "750FX",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 	CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
 	COMMON_PPC,
 	32, 32,
@@ -194,8 +205,8 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 750FX rev 2.0 must disable HID0[DPM] */
     	0xffffffff, 0x70000200, "750FX",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 	CPU_FTR_NO_DPM,
 	COMMON_PPC,
 	32, 32,
@@ -204,8 +215,8 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 750FX (All revs except 2.0) */
     	0xffff0000, 0x70000000, "750FX",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 	CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 	COMMON_PPC,
 	32, 32,
@@ -213,8 +224,8 @@ struct cpu_spec	cpu_specs[] = {
     },
     {	/* 750GX */
     	0xffff0000, 0x70020000, "750GX",
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
 	CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
 	COMMON_PPC,
 	32, 32,
@@ -223,8 +234,8 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 740/750 (L2CR bit need fixup for 740) */
     	0xffff0000, 0x00080000, "740/750",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
 	COMMON_PPC,
 	32, 32,
 	__setup_cpu_750
@@ -232,9 +243,9 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 7400 rev 1.1 ? (no TAU) */
     	0xffffffff, 0x000c1101, "7400 (1.1)",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
-	CPU_FTR_CAN_NAP,
+	CPU_FTR_MAYBE_CAN_NAP,
 	COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 	32, 32,
 	__setup_cpu_7400
@@ -242,9 +253,9 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 7400 */
     	0xffff0000, 0x000c0000, "7400",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
-	CPU_FTR_CAN_NAP,
+	CPU_FTR_MAYBE_CAN_NAP,
 	COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 	32, 32,
 	__setup_cpu_7400
@@ -252,9 +263,9 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 7410 */
     	0xffff0000, 0x800c0000, "7410",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
 	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
-	CPU_FTR_CAN_NAP,
+	CPU_FTR_MAYBE_CAN_NAP,
 	COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
 	32, 32,
 	__setup_cpu_7410
@@ -272,7 +283,7 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 7450 2.1 */
     	0xffffffff, 0x80000201, "7450",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 	CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT,
@@ -283,7 +294,7 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 7450 2.3 and newer */
     	0xffff0000, 0x80000000, "7450",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 	CPU_FTR_NEED_COHERENT,
@@ -305,7 +316,7 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 7455 rev 2.0 */
     	0xffffffff, 0x80010200, "7455",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 	CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
@@ -316,7 +327,7 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 7455 others */
     	0xffff0000, 0x80010000, "7455",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 	CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
@@ -327,7 +338,7 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 7447/7457 Rev 1.0 */
     	0xffffffff, 0x80020100, "7447/7457",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 	CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
@@ -338,7 +349,7 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 7447/7457 Rev 1.1 */
     	0xffffffff, 0x80020101, "7447/7457",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 	CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
@@ -349,7 +360,7 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 7447/7457 Rev 1.2 and later */
     	0xffff0000, 0x80020000, "7447/7457",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
 	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 	CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
@@ -360,7 +371,7 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 7447A */
     	0xffff0000, 0x80030000, "7447A",
 	CPU_FTR_COMMON |
-    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP |
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP |
 	CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
 	CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
 	CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
@@ -371,15 +382,15 @@ struct cpu_spec	cpu_specs[] = {
     {	/* 82xx (8240, 8245, 8260 are all 603e cores) */
 	0x7fff0000, 0x00810000, "82xx",
 	CPU_FTR_COMMON |
-	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB,
+	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
 	COMMON_PPC,
 	32, 32,
 	__setup_cpu_603
     },
     {	/* All G2_LE (603e core, plus some) have the same pvr */
 	0x7fff0000, 0x00820000, "G2_LE",
-	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
-	CPU_FTR_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
+	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
+	CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
 	COMMON_PPC,
 	32, 32,
 	__setup_cpu_603
@@ -440,7 +451,7 @@ struct cpu_spec	cpu_specs[] = {
 	0xffff0000, 0x00390000, "PPC970",
 	CPU_FTR_COMMON |
 	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-	CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP,
+	CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
 	COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
 	128, 128,
 	__setup_cpu_ppc970
@@ -449,7 +460,7 @@ struct cpu_spec	cpu_specs[] = {
 	0xffff0000, 0x003c0000, "PPC970FX",
 	CPU_FTR_COMMON |
 	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-	CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP,
+	CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
 	COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_ALTIVEC_COMP,
 	128, 128,
 	__setup_cpu_ppc970
@@ -458,7 +469,8 @@ struct cpu_spec	cpu_specs[] = {
 #ifdef CONFIG_8xx
     {	/* 8xx */
     	0xffff0000, 0x00500000, "8xx",
-		/* CPU_FTR_CAN_DOZE is possible, if the 8xx code is there.... */
+		/* CPU_FTR_MAYBE_CAN_DOZE is possible,
+		 * if the 8xx code is there.... */
     	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
     	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  	16, 16,
@@ -599,7 +611,7 @@ struct cpu_spec	cpu_specs[] = {
 #ifdef CONFIG_E500
     { /* e500 */
         0xffff0000, 0x80200000, "e500",
-	/* xxx - galak: add CPU_FTR_CAN_DOZE */
+	/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
         32, 32,

arch/ppc/platforms/lite5200.c

@@ -36,6 +36,8 @@
 #include <asm/mpc52xx.h>
 
 
+extern int powersave_nap;
+
 /* Board data given by U-Boot */
 bd_t __res;
 EXPORT_SYMBOL(__res);	/* For modules */
@@ -64,25 +66,55 @@ struct ocp_def board_ocp[] = {
 		.vendor		= OCP_VENDOR_INVALID
 	}
 };
-	
+
 
 /* ======================================================================== */
 /* Platform specific code                                                   */
 /* ======================================================================== */
 
 static int
-icecube_show_cpuinfo(struct seq_file *m)
+lite5200_show_cpuinfo(struct seq_file *m)
 {
 	seq_printf(m, "machine\t\t: Freescale LITE5200\n");
 	return 0;
 }
 
 static void __init
-icecube_setup_arch(void)
+lite5200_setup_cpu(void)
 {
+	struct mpc52xx_intr *intr;
+
+	u32 intr_ctrl;
+
+	/* Map zones */
+	intr = (struct mpc52xx_intr *)
+		ioremap(MPC52xx_INTR,sizeof(struct mpc52xx_intr));
+
+	if (!intr) {
+		printk("lite5200.c: Error while mapping INTR during lite5200_setup_cpu\n");
+		goto unmap_regs;
+	}
+
+	/* IRQ[0-3] setup : IRQ0     - Level Active Low  */
+	/*                  IRQ[1-3] - Level Active High */
+	intr_ctrl = in_be32(&intr->ctrl);
+	intr_ctrl &= ~0x00ff0000;
+	intr_ctrl |=  0x00c00000;
+	out_be32(&intr->ctrl, intr_ctrl);
+
+	/* Unmap reg zone */
+unmap_regs:
+	if (intr) iounmap(intr);
+}
 
+static void __init
+lite5200_setup_arch(void)
+{
 	/* Add board OCP definitions */
 	mpc52xx_add_board_devices(board_ocp);
+
+	/* CPU & Port mux setup */
+	lite5200_setup_cpu();
 }
 
 void __init
@@ -110,7 +142,7 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 			initrd_end = r5 + KERNELBASE;
 		}
 #endif
-	
+
 		/* Load the command line */
 		if (r6) {
 			*(char *)(r7+KERNELBASE) = 0;
@@ -120,14 +152,17 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 
 	/* BAT setup */
 	mpc52xx_set_bat();
-	
+
 	/* No ISA bus AFAIK */
 	isa_io_base		= 0;
 	isa_mem_base		= 0;
 
+	/* Powersave */
+	powersave_nap = 1;	/* We allow this platform to NAP */
+
 	/* Setup the ppc_md struct */
-	ppc_md.setup_arch	= icecube_setup_arch;
-	ppc_md.show_cpuinfo	= icecube_show_cpuinfo;
+	ppc_md.setup_arch	= lite5200_setup_arch;
+	ppc_md.show_cpuinfo	= lite5200_show_cpuinfo;
 	ppc_md.show_percpuinfo	= NULL;
 	ppc_md.init_IRQ		= mpc52xx_init_irq;
 	ppc_md.get_irq		= mpc52xx_get_irq;
@@ -138,12 +173,12 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	ppc_md.restart		= mpc52xx_restart;
 	ppc_md.power_off	= mpc52xx_power_off;
 	ppc_md.halt		= mpc52xx_halt;
-	
-		/* No time keeper on the IceCube */
+
+		/* No time keeper on the LITE5200 */
 	ppc_md.time_init	= NULL;
 	ppc_md.get_rtc_time	= NULL;
 	ppc_md.set_rtc_time	= NULL;
-	
+
 	ppc_md.calibrate_decr	= mpc52xx_calibrate_decr;
 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 	ppc_md.progress		= mpc52xx_progress;

arch/ppc/platforms/mpc5200.c

@@ -16,6 +16,12 @@
 #include <asm/ocp.h>
 #include <asm/mpc52xx.h>
 
+
+struct ocp_fs_i2c_data mpc5200_i2c_def = {
+        .flags  = FS_I2C_CLOCK_5200,
+};
+
+
 /* Here is the core_ocp struct.
  * With all the devices common to all board. Even if port multiplexing is
  * not setup for them (if the user don't want them, just don't select the
@@ -23,6 +29,24 @@
  * board specific file.
  */
 struct ocp_def core_ocp[] = {
+	{
+		.vendor         = OCP_VENDOR_FREESCALE,
+		.function       = OCP_FUNC_IIC,
+		.index          = 0,
+		.paddr          = MPC52xx_I2C1,
+		.irq            = OCP_IRQ_NA,   /* MPC52xx_IRQ_I2C1 - Buggy */
+		.pm             = OCP_CPM_NA,
+		.additions      = &mpc5200_i2c_def,
+	},
+	{
+		.vendor         = OCP_VENDOR_FREESCALE,
+		.function       = OCP_FUNC_IIC,
+		.index          = 1,
+		.paddr          = MPC52xx_I2C2,
+		.irq            = OCP_IRQ_NA,   /* MPC52xx_IRQ_I2C2 - Buggy */
+		.pm             = OCP_CPM_NA,
+		.additions      = &mpc5200_i2c_def,
+	},
 	{	/* Terminating entry */
 		.vendor		= OCP_VENDOR_INVALID
 	}

arch/ppc/syslib/mpc52xx_pic.c

@@ -114,7 +114,7 @@ mpc52xx_ic_ack(unsigned int irq)
 	/*
 	 * Only some irqs are reset here, others in interrupting hardware.
 	 */
-			
+
 	switch (irq) {
 	case MPC52xx_IRQ0:
 		val = in_be32(&intr->ctrl);
@@ -180,13 +180,14 @@ void __init
 mpc52xx_init_irq(void)
 {
 	int i;
+	u32 intr_ctrl;
 
 	/* Remap the necessary zones */
 	intr = (struct mpc52xx_intr *)
 		ioremap(MPC52xx_INTR, sizeof(struct mpc52xx_intr));
 	sdma = (struct mpc52xx_sdma *)
 		ioremap(MPC52xx_SDMA, sizeof(struct mpc52xx_sdma));
-	
+
 	if ((intr==NULL) || (sdma==NULL))
 		panic("Can't ioremap PIC/SDMA register for init_irq !");
 
@@ -195,12 +196,13 @@ mpc52xx_init_irq(void)
 	out_be32(&sdma->IntMask, 0xffffffff);	/* 1 means disabled */
 	out_be32(&intr->per_mask, 0x7ffffc00);	/* 1 means disabled */
 	out_be32(&intr->main_mask, 0x00010fff);	/* 1 means disabled */
-	out_be32(&intr->ctrl,
-			0x0f000000 |	/* clear IRQ 0-3 */
-			0x00c00000 |	/* IRQ0: level-sensitive, active low */
+	intr_ctrl = in_be32(&intr->ctrl);
+	intr_ctrl &=    0x00ff0000;	/* Keeps IRQ[0-3] config */
+	intr_ctrl |=	0x0f000000 |	/* clear IRQ 0-3 */
 			0x00001000 |	/* MEE master external enable */
 			0x00000000 |	/* 0 means disable IRQ 0-3 */
-			0x00000001);	/* CEb route critical normally */
+			0x00000001;	/* CEb route critical normally */
+	out_be32(&intr->ctrl, intr_ctrl);
 
 	/* Zero a bunch of the priority settings.  */
 	out_be32(&intr->per_pri1, 0);
@@ -214,6 +216,14 @@ mpc52xx_init_irq(void)
 		irq_desc[i].handler = &mpc52xx_ic;
 		irq_desc[i].status = IRQ_LEVEL;
 	}
+
+	#define IRQn_MODE(intr_ctrl,irq) (((intr_ctrl) >> (22-(i<<1))) & 0x03)
+	for (i=0 ; i<4 ; i++) {
+		int mode;
+		mode = IRQn_MODE(intr_ctrl,i);
+		if ((mode == 0x1) || (mode == 0x2))
+			irq_desc[i?MPC52xx_IRQ1+i-1:MPC52xx_IRQ0].status = 0;
+	}
 }
 
 int

arch/ppc/syslib/mpc52xx_setup.c

 /*
- * arch/ppc/syslib/mpc52xx_common.c
+ * arch/ppc/syslib/mpc52xx_setup.c
  *
  * Common code for the boards based on Freescale MPC52xx embedded CPU.
  *
@@ -23,6 +23,7 @@
 #include <asm/mpc52xx.h>
 #include <asm/mpc52xx_psc.h>
 #include <asm/ocp.h>
+#include <asm/pgtable.h>
 #include <asm/ppcboot.h>
 
 extern bd_t __res;
@@ -38,9 +39,9 @@ void
 mpc52xx_restart(char *cmd)
 {
 	struct mpc52xx_gpt* gpt0 = (struct mpc52xx_gpt*) MPC52xx_GPTx(0);
-	
+
 	local_irq_disable();
-	
+
 	/* Turn on the watchdog and wait for it to expire. It effectively
 	  does a reset */
 	if (gpt0 != NULL) {
@@ -99,24 +100,28 @@ mpc52xx_map_io(void)
 #error "mpc52xx PSC for console not selected"
 #endif
 
+static void
+mpc52xx_psc_putc(struct mpc52xx_psc * psc, unsigned char c)
+{
+	while (!(in_be16(&psc->mpc52xx_psc_status) &
+	         MPC52xx_PSC_SR_TXRDY));
+	out_8(&psc->mpc52xx_psc_buffer_8, c);
+}
+
 void
 mpc52xx_progress(char *s, unsigned short hex)
 {
 	struct mpc52xx_psc *psc = (struct mpc52xx_psc *)MPC52xx_CONSOLE;
 	char c;
 
-		/* Don't we need to disable serial interrupts ? */
-	
 	while ((c = *s++) != 0) {
-		if (c == '\n') {
-			while (!(in_be16(&psc->mpc52xx_psc_status) &
-			         MPC52xx_PSC_SR_TXRDY)) ;
-			out_8(&psc->mpc52xx_psc_buffer_8, '\r');
-		}
-		while (!(in_be16(&psc->mpc52xx_psc_status) &
-		         MPC52xx_PSC_SR_TXRDY)) ;
-		out_8(&psc->mpc52xx_psc_buffer_8, c);
+		if (c == '\n')
+			mpc52xx_psc_putc(psc, '\r');
+		mpc52xx_psc_putc(psc, c);
 	}
+
+	mpc52xx_psc_putc(psc, '\r');
+	mpc52xx_psc_putc(psc, '\n');
 }
 
 #endif  /* CONFIG_SERIAL_TEXT_DEBUG */
@@ -137,7 +142,7 @@ mpc52xx_find_end_of_memory(void)
 
 		/* Temp BAT2 mapping active when this is called ! */
 		mmap_ctl = (struct mpc52xx_mmap_ctl*) MPC52xx_MMAP_CTL;
-			
+
 		sdram_config_0 = in_be32(&mmap_ctl->sdram0);
 		sdram_config_1 = in_be32(&mmap_ctl->sdram1);
 
@@ -147,10 +152,8 @@ mpc52xx_find_end_of_memory(void)
 		if (((sdram_config_1 & 0x1f) >= 0x13) &&
 				((sdram_config_1 & 0xfff00000) == ramsize))
 			ramsize += 1 << ((sdram_config_1 & 0xf) + 17);
-
-		iounmap(mmap_ctl);
 	}
-	
+
 	return ramsize;
 }
 
@@ -167,7 +170,7 @@ mpc52xx_calibrate_decr(void)
 		/* Get RTC & Clock manager modules */
 		struct mpc52xx_rtc *rtc;
 		struct mpc52xx_cdm *cdm;
-		
+
 		rtc = (struct mpc52xx_rtc*)
 			ioremap(MPC52xx_RTC, sizeof(struct mpc52xx_rtc));
 		cdm = (struct mpc52xx_cdm*)
@@ -206,7 +209,7 @@ mpc52xx_calibrate_decr(void)
 		__res.bi_intfreq = cpufreq;
 		__res.bi_ipbfreq = ipbfreq;
 		__res.bi_pcifreq = pcifreq;
-	
+
 		/* Release mapping */
 		iounmap((void*)rtc);
 		iounmap((void*)cdm);

include/asm-ppc/mpc52xx.h

@@ -42,6 +42,7 @@ struct ocp_def;
 #define MPC52xx_MBAR_VIRT	0xf0000000	/* Virt address */
 
 #define MPC52xx_MMAP_CTL	(MPC52xx_MBAR + 0x0000)
+#define MPC52xx_SDRAM		(MPC52xx_MBAR + 0x0100)
 #define MPC52xx_CDM		(MPC52xx_MBAR + 0x0200)
 #define MPC52xx_SFTRST		(MPC52xx_MBAR + 0x0220)
 #define MPC52xx_SFTRST_BIT	0x01000000
@@ -51,6 +52,7 @@ struct ocp_def;
 #define MPC52xx_MSCAN1		(MPC52xx_MBAR + 0x0900)
 #define MPC52xx_MSCAN2		(MPC52xx_MBAR + 0x0980)
 #define MPC52xx_GPIO		(MPC52xx_MBAR + 0x0b00)
+#define MPC52xx_GPIO_WKUP	(MPC52xx_MBAR + 0x0c00)
 #define MPC52xx_PCI		(MPC52xx_MBAR + 0x0d00)
 #define MPC52xx_USB_OHCI	(MPC52xx_MBAR + 0x1000)
 #define MPC52xx_SDMA		(MPC52xx_MBAR + 0x1200)
@@ -71,10 +73,6 @@ struct ocp_def;
 /* SRAM used for SDMA */
 #define MPC52xx_SRAM		(MPC52xx_MBAR + 0x8000)
 #define MPC52xx_SRAM_SIZE	(16*1024)
-#define MPC52xx_SDMA_MAX_TASKS	16
-
-	/* Memory allocation block size */
-#define MPC52xx_SDRAM_UNIT	0x8000		/* 32K byte */
 
 
 /* ======================================================================== */
@@ -137,206 +135,240 @@ struct ocp_def;
 
 /* Memory Mapping Control */
 struct mpc52xx_mmap_ctl {
-	volatile u32	mbar;		/* MMAP_CTRL + 0x00 */
-
-	volatile u32	cs0_start;	/* MMAP_CTRL + 0x04 */
-	volatile u32	cs0_stop;	/* MMAP_CTRL + 0x08 */
-	volatile u32	cs1_start;	/* MMAP_CTRL + 0x0c */
-	volatile u32	cs1_stop;	/* MMAP_CTRL + 0x10 */
-	volatile u32	cs2_start;	/* MMAP_CTRL + 0x14 */
-	volatile u32	cs2_stop;	/* MMAP_CTRL + 0x18 */
-	volatile u32	cs3_start;	/* MMAP_CTRL + 0x1c */
-	volatile u32	cs3_stop;	/* MMAP_CTRL + 0x20 */
-	volatile u32	cs4_start;	/* MMAP_CTRL + 0x24 */
-	volatile u32	cs4_stop;	/* MMAP_CTRL + 0x28 */
-	volatile u32	cs5_start;	/* MMAP_CTRL + 0x2c */
-	volatile u32	cs5_stop;	/* MMAP_CTRL + 0x30 */
-
-	volatile u32	sdram0;		/* MMAP_CTRL + 0x34 */
-	volatile u32	sdram1;		/* MMAP_CTRL + 0X38 */
-
-	volatile u32	reserved[4];	/* MMAP_CTRL + 0x3c .. 0x48 */
-
-	volatile u32	boot_start;	/* MMAP_CTRL + 0x4c */
-	volatile u32	boot_stop;	/* MMAP_CTRL + 0x50 */
-	
-	volatile u32	ipbi_ws_ctrl;	/* MMAP_CTRL + 0x54 */
-	
-	volatile u32	cs6_start;	/* MMAP_CTRL + 0x58 */
-	volatile u32	cs6_stop;	/* MMAP_CTRL + 0x5c */
-	volatile u32	cs7_start;	/* MMAP_CTRL + 0x60 */
-	volatile u32	cs7_stop;	/* MMAP_CTRL + 0x60 */
+	u32	mbar;		/* MMAP_CTRL + 0x00 */
+
+	u32	cs0_start;	/* MMAP_CTRL + 0x04 */
+	u32	cs0_stop;	/* MMAP_CTRL + 0x08 */
+	u32	cs1_start;	/* MMAP_CTRL + 0x0c */
+	u32	cs1_stop;	/* MMAP_CTRL + 0x10 */
+	u32	cs2_start;	/* MMAP_CTRL + 0x14 */
+	u32	cs2_stop;	/* MMAP_CTRL + 0x18 */
+	u32	cs3_start;	/* MMAP_CTRL + 0x1c */
+	u32	cs3_stop;	/* MMAP_CTRL + 0x20 */
+	u32	cs4_start;	/* MMAP_CTRL + 0x24 */
+	u32	cs4_stop;	/* MMAP_CTRL + 0x28 */
+	u32	cs5_start;	/* MMAP_CTRL + 0x2c */
+	u32	cs5_stop;	/* MMAP_CTRL + 0x30 */
+
+	u32	sdram0;		/* MMAP_CTRL + 0x34 */
+	u32	sdram1;		/* MMAP_CTRL + 0X38 */
+
+	u32	reserved[4];	/* MMAP_CTRL + 0x3c .. 0x48 */
+
+	u32	boot_start;	/* MMAP_CTRL + 0x4c */
+	u32	boot_stop;	/* MMAP_CTRL + 0x50 */
+
+	u32	ipbi_ws_ctrl;	/* MMAP_CTRL + 0x54 */
+
+	u32	cs6_start;	/* MMAP_CTRL + 0x58 */
+	u32	cs6_stop;	/* MMAP_CTRL + 0x5c */
+	u32	cs7_start;	/* MMAP_CTRL + 0x60 */
+	u32	cs7_stop;	/* MMAP_CTRL + 0x60 */
+};
+
+/* SDRAM control */
+struct mpc52xx_sdram {
+	u32	mode;		/* SDRAM + 0x00 */
+	u32	ctrl;		/* SDRAM + 0x04 */
+	u32	config1;	/* SDRAM + 0x08 */
+	u32	config2;	/* SDRAM + 0x0c */
 };
 
 /* Interrupt controller */
 struct mpc52xx_intr {
-	volatile u32	per_mask;	/* INTR + 0x00 */
-	volatile u32	per_pri1;	/* INTR + 0x04 */
-	volatile u32	per_pri2;	/* INTR + 0x08 */
-	volatile u32	per_pri3;	/* INTR + 0x0c */
-	volatile u32	ctrl;		/* INTR + 0x10 */
-	volatile u32	main_mask;	/* INTR + 0x14 */
-	volatile u32	main_pri1;	/* INTR + 0x18 */
-	volatile u32	main_pri2;	/* INTR + 0x1c */
-	volatile u32	reserved1;	/* INTR + 0x20 */
-	volatile u32	enc_status;	/* INTR + 0x24 */
-	volatile u32	crit_status;	/* INTR + 0x28 */
-	volatile u32	main_status;	/* INTR + 0x2c */
-	volatile u32	per_status;	/* INTR + 0x30 */
-	volatile u32	reserved2;	/* INTR + 0x34 */
-	volatile u32	per_error;	/* INTR + 0x38 */
+	u32	per_mask;	/* INTR + 0x00 */
+	u32	per_pri1;	/* INTR + 0x04 */
+	u32	per_pri2;	/* INTR + 0x08 */
+	u32	per_pri3;	/* INTR + 0x0c */
+	u32	ctrl;		/* INTR + 0x10 */
+	u32	main_mask;	/* INTR + 0x14 */
+	u32	main_pri1;	/* INTR + 0x18 */
+	u32	main_pri2;	/* INTR + 0x1c */
+	u32	reserved1;	/* INTR + 0x20 */
+	u32	enc_status;	/* INTR + 0x24 */
+	u32	crit_status;	/* INTR + 0x28 */
+	u32	main_status;	/* INTR + 0x2c */
+	u32	per_status;	/* INTR + 0x30 */
+	u32	reserved2;	/* INTR + 0x34 */
+	u32	per_error;	/* INTR + 0x38 */
 };
 
 /* SDMA */
 struct mpc52xx_sdma {
-	volatile u32	taskBar;	/* SDMA + 0x00 */
-	volatile u32	currentPointer;	/* SDMA + 0x04 */
-	volatile u32	endPointer;	/* SDMA + 0x08 */
-	volatile u32	variablePointer;/* SDMA + 0x0c */
-
-	volatile u8	IntVect1;	/* SDMA + 0x10 */
-	volatile u8	IntVect2;	/* SDMA + 0x11 */
-	volatile u16	PtdCntrl;	/* SDMA + 0x12 */
-
-	volatile u32	IntPend;	/* SDMA + 0x14 */
-	volatile u32	IntMask;	/* SDMA + 0x18 */
-	
-	volatile u16	tcr[16];	/* SDMA + 0x1c .. 0x3a */
-
-	volatile u8	ipr[31];	/* SDMA + 0x3c .. 5b */
-
-	volatile u32	res1;		/* SDMA + 0x5c */
-	volatile u32	task_size0;	/* SDMA + 0x60 */
-	volatile u32	task_size1;	/* SDMA + 0x64 */
-	volatile u32	MDEDebug;	/* SDMA + 0x68 */
-	volatile u32	ADSDebug;	/* SDMA + 0x6c */
-	volatile u32	Value1;		/* SDMA + 0x70 */
-	volatile u32	Value2;		/* SDMA + 0x74 */
-	volatile u32	Control;	/* SDMA + 0x78 */
-	volatile u32	Status;		/* SDMA + 0x7c */
+	u32	taskBar;	/* SDMA + 0x00 */
+	u32	currentPointer;	/* SDMA + 0x04 */
+	u32	endPointer;	/* SDMA + 0x08 */
+	u32	variablePointer;/* SDMA + 0x0c */
+
+	u8	IntVect1;	/* SDMA + 0x10 */
+	u8	IntVect2;	/* SDMA + 0x11 */
+	u16	PtdCntrl;	/* SDMA + 0x12 */
+
+	u32	IntPend;	/* SDMA + 0x14 */
+	u32	IntMask;	/* SDMA + 0x18 */
+
+	u16	tcr[16];	/* SDMA + 0x1c .. 0x3a */
+
+	u8	ipr[32];	/* SDMA + 0x3c .. 5b */
+
+	u32	cReqSelect;	/* SDMA + 0x5c */
+	u32	task_size0;	/* SDMA + 0x60 */
+	u32	task_size1;	/* SDMA + 0x64 */
+	u32	MDEDebug;	/* SDMA + 0x68 */
+	u32	ADSDebug;	/* SDMA + 0x6c */
+	u32	Value1;		/* SDMA + 0x70 */
+	u32	Value2;		/* SDMA + 0x74 */
+	u32	Control;	/* SDMA + 0x78 */
+	u32	Status;		/* SDMA + 0x7c */
+	u32	PTDDebug;	/* SDMA + 0x80 */
 };
 
 /* GPT */
 struct mpc52xx_gpt {
-	volatile u32	mode;		/* GPTx + 0x00 */
-	volatile u32	count;		/* GPTx + 0x04 */
-	volatile u32	pwm;		/* GPTx + 0x08 */
-	volatile u32	status;		/* GPTx + 0X0c */
+	u32	mode;		/* GPTx + 0x00 */
+	u32	count;		/* GPTx + 0x04 */
+	u32	pwm;		/* GPTx + 0x08 */
+	u32	status;		/* GPTx + 0X0c */
 };
 
 /* RTC */
 struct mpc52xx_rtc {
-	volatile u32	time_set;	/* RTC + 0x00 */
-	volatile u32	date_set;	/* RTC + 0x04 */
-	volatile u32	stopwatch;	/* RTC + 0x08 */
-	volatile u32	int_enable;	/* RTC + 0x0c */
-	volatile u32	time;		/* RTC + 0x10 */
-	volatile u32	date;		/* RTC + 0x14 */
-	volatile u32	stopwatch_intr;	/* RTC + 0x18 */
-	volatile u32	bus_error;	/* RTC + 0x1c */
-	volatile u32	dividers;	/* RTC + 0x20 */
+	u32	time_set;	/* RTC + 0x00 */
+	u32	date_set;	/* RTC + 0x04 */
+	u32	stopwatch;	/* RTC + 0x08 */
+	u32	int_enable;	/* RTC + 0x0c */
+	u32	time;		/* RTC + 0x10 */
+	u32	date;		/* RTC + 0x14 */
+	u32	stopwatch_intr;	/* RTC + 0x18 */
+	u32	bus_error;	/* RTC + 0x1c */
+	u32	dividers;	/* RTC + 0x20 */
 };
 
 /* GPIO */
 struct mpc52xx_gpio {
-	volatile u32	port_config;	/* GPIO + 0x00 */
-	volatile u32	simple_gpioe;	/* GPIO + 0x04 */
-	volatile u32	simple_ode;	/* GPIO + 0x08 */
-	volatile u32	simple_ddr;	/* GPIO + 0x0c */
-	volatile u32	simple_dvo;	/* GPIO + 0x10 */
-	volatile u32	simple_ival;	/* GPIO + 0x14 */
-	volatile u8	outo_gpioe;	/* GPIO + 0x18 */
-	volatile u8	reserved1[3];	/* GPIO + 0x19 */
-	volatile u8	outo_dvo;	/* GPIO + 0x1c */
-	volatile u8	reserved2[3];	/* GPIO + 0x1d */
-	volatile u8	sint_gpioe;	/* GPIO + 0x20 */
-	volatile u8	reserved3[3];	/* GPIO + 0x21 */
-	volatile u8	sint_ode;	/* GPIO + 0x24 */
-	volatile u8	reserved4[3];	/* GPIO + 0x25 */
-	volatile u8	sint_ddr;	/* GPIO + 0x28 */
-	volatile u8	reserved5[3];	/* GPIO + 0x29 */
-	volatile u8	sint_dvo;	/* GPIO + 0x2c */
-	volatile u8	reserved6[3];	/* GPIO + 0x2d */
-	volatile u8	sint_inten;	/* GPIO + 0x30 */
-	volatile u8	reserved7[3];	/* GPIO + 0x31 */
-	volatile u16	sint_itype;	/* GPIO + 0x34 */
-	volatile u16	reserved8;	/* GPIO + 0x36 */
-	volatile u8	gpio_control;	/* GPIO + 0x38 */
-	volatile u8	reserved9[3];	/* GPIO + 0x39 */
-	volatile u8	sint_istat;	/* GPIO + 0x3c */
-	volatile u8	sint_ival;	/* GPIO + 0x3d */
-	volatile u8	bus_errs;	/* GPIO + 0x3e */
-	volatile u8	reserved10;	/* GPIO + 0x3f */
+	u32	port_config;	/* GPIO + 0x00 */
+	u32	simple_gpioe;	/* GPIO + 0x04 */
+	u32	simple_ode;	/* GPIO + 0x08 */
+	u32	simple_ddr;	/* GPIO + 0x0c */
+	u32	simple_dvo;	/* GPIO + 0x10 */
+	u32	simple_ival;	/* GPIO + 0x14 */
+	u8	outo_gpioe;	/* GPIO + 0x18 */
+	u8	reserved1[3];	/* GPIO + 0x19 */
+	u8	outo_dvo;	/* GPIO + 0x1c */
+	u8	reserved2[3];	/* GPIO + 0x1d */
+	u8	sint_gpioe;	/* GPIO + 0x20 */
+	u8	reserved3[3];	/* GPIO + 0x21 */
+	u8	sint_ode;	/* GPIO + 0x24 */
+	u8	reserved4[3];	/* GPIO + 0x25 */
+	u8	sint_ddr;	/* GPIO + 0x28 */
+	u8	reserved5[3];	/* GPIO + 0x29 */
+	u8	sint_dvo;	/* GPIO + 0x2c */
+	u8	reserved6[3];	/* GPIO + 0x2d */
+	u8	sint_inten;	/* GPIO + 0x30 */
+	u8	reserved7[3];	/* GPIO + 0x31 */
+	u16	sint_itype;	/* GPIO + 0x34 */
+	u16	reserved8;	/* GPIO + 0x36 */
+	u8	gpio_control;	/* GPIO + 0x38 */
+	u8	reserved9[3];	/* GPIO + 0x39 */
+	u8	sint_istat;	/* GPIO + 0x3c */
+	u8	sint_ival;	/* GPIO + 0x3d */
+	u8	bus_errs;	/* GPIO + 0x3e */
+	u8	reserved10;	/* GPIO + 0x3f */
 };
 
 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD	4
 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD	5
 #define MPC52xx_GPIO_PCI_DIS			(1<<15)
 
+/* GPIO with WakeUp*/
+struct mpc52xx_gpio_wkup {
+	u8	wkup_gpioe;	/* GPIO_WKUP + 0x00 */
+	u8	reserved1[3];	/* GPIO_WKUP + 0x03 */
+	u8	wkup_ode;	/* GPIO_WKUP + 0x04 */
+	u8	reserved2[3];	/* GPIO_WKUP + 0x05 */
+	u8	wkup_ddr;	/* GPIO_WKUP + 0x08 */
+	u8	reserved3[3];	/* GPIO_WKUP + 0x09 */
+	u8	wkup_dvo;	/* GPIO_WKUP + 0x0C */
+	u8	reserved4[3];	/* GPIO_WKUP + 0x0D */
+	u8	wkup_inten;	/* GPIO_WKUP + 0x10 */
+	u8	reserved5[3];	/* GPIO_WKUP + 0x11 */
+	u8	wkup_iinten;	/* GPIO_WKUP + 0x14 */
+	u8	reserved6[3];	/* GPIO_WKUP + 0x15 */
+	u16	wkup_itype;	/* GPIO_WKUP + 0x18 */
+	u8	reserved7[2];	/* GPIO_WKUP + 0x1A */
+	u8	wkup_maste;	/* GPIO_WKUP + 0x1C */
+	u8	reserved8[3];	/* GPIO_WKUP + 0x1D */
+	u8	wkup_ival;	/* GPIO_WKUP + 0x20 */
+	u8	reserved9[3];	/* GPIO_WKUP + 0x21 */
+	u8	wkup_istat;	/* GPIO_WKUP + 0x24 */
+	u8	reserved10[3];	/* GPIO_WKUP + 0x25 */
+};
+
 /* XLB Bus control */
 struct mpc52xx_xlb {
-	volatile u8 reserved[0x40];
-	volatile u32 config;		/* XLB + 0x40 */
-	volatile u32 version;		/* XLB + 0x44 */
-	volatile u32 status;		/* XLB + 0x48 */
-	volatile u32 int_enable;	/* XLB + 0x4c */
-	volatile u32 addr_capture;	/* XLB + 0x50 */
-	volatile u32 bus_sig_capture;	/* XLB + 0x54 */
-	volatile u32 addr_timeout;	/* XLB + 0x58 */
-	volatile u32 data_timeout;	/* XLB + 0x5c */
-	volatile u32 bus_act_timeout;	/* XLB + 0x60 */
-	volatile u32 master_pri_enable;	/* XLB + 0x64 */
-	volatile u32 master_priority;	/* XLB + 0x68 */
-	volatile u32 base_address;	/* XLB + 0x6c */
-	volatile u32 snoop_window;	/* XLB + 0x70 */
+	u8	reserved[0x40];
+	u32	config;			/* XLB + 0x40 */
+	u32	version;		/* XLB + 0x44 */
+	u32	status;			/* XLB + 0x48 */
+	u32	int_enable;		/* XLB + 0x4c */
+	u32	addr_capture;		/* XLB + 0x50 */
+	u32	bus_sig_capture;	/* XLB + 0x54 */
+	u32	addr_timeout;		/* XLB + 0x58 */
+	u32	data_timeout;		/* XLB + 0x5c */
+	u32	bus_act_timeout;	/* XLB + 0x60 */
+	u32	master_pri_enable;	/* XLB + 0x64 */
+	u32	master_priority;	/* XLB + 0x68 */
+	u32	base_address;		/* XLB + 0x6c */
+	u32	snoop_window;		/* XLB + 0x70 */
 };
 
+#define MPC52xx_XLB_CFG_SNOOP		(1 << 15)
 
 /* Clock Distribution control */
 struct mpc52xx_cdm {
-	volatile u32	jtag_id;	/* MBAR_CDM + 0x00  reg0 read only */
-	volatile u32	rstcfg;		/* MBAR_CDM + 0x04  reg1 read only */
-	volatile u32	breadcrumb;	/* MBAR_CDM + 0x08  reg2 */
-
-	volatile u8	mem_clk_sel;	/* MBAR_CDM + 0x0c  reg3 byte0 */
-	volatile u8	xlb_clk_sel;	/* MBAR_CDM + 0x0d  reg3 byte1 read only */
-	volatile u8	ipb_clk_sel;	/* MBAR_CDM + 0x0e  reg3 byte2 */
-	volatile u8	pci_clk_sel;	/* MBAR_CDM + 0x0f  reg3 byte3 */
-
-	volatile u8	ext_48mhz_en;	/* MBAR_CDM + 0x10  reg4 byte0 */
-	volatile u8	fd_enable;	/* MBAR_CDM + 0x11  reg4 byte1 */
-	volatile u16	fd_counters;	/* MBAR_CDM + 0x12  reg4 byte2,3 */
-
-	volatile u32	clk_enables;	/* MBAR_CDM + 0x14  reg5 */
-
-	volatile u8	osc_disable;	/* MBAR_CDM + 0x18  reg6 byte0 */
-	volatile u8	reserved0[3];	/* MBAR_CDM + 0x19  reg6 byte1,2,3 */
-
-	volatile u8	ccs_sleep_enable;/* MBAR_CDM + 0x1c  reg7 byte0 */
-	volatile u8	osc_sleep_enable;/* MBAR_CDM + 0x1d  reg7 byte1 */
-	volatile u8	reserved1;	/* MBAR_CDM + 0x1e  reg7 byte2 */
-	volatile u8	ccs_qreq_test;	/* MBAR_CDM + 0x1f  reg7 byte3 */
-
-	volatile u8	soft_reset;	/* MBAR_CDM + 0x20  u8 byte0 */
-	volatile u8	no_ckstp;	/* MBAR_CDM + 0x21  u8 byte0 */
-	volatile u8	reserved2[2];	/* MBAR_CDM + 0x22  u8 byte1,2,3 */
-
-	volatile u8	pll_lock;	/* MBAR_CDM + 0x24  reg9 byte0 */
-	volatile u8	pll_looselock;	/* MBAR_CDM + 0x25  reg9 byte1 */
-	volatile u8	pll_sm_lockwin;	/* MBAR_CDM + 0x26  reg9 byte2 */
-	volatile u8	reserved3;	/* MBAR_CDM + 0x27  reg9 byte3 */
-
-	volatile u16	reserved4;	/* MBAR_CDM + 0x28  reg10 byte0,1 */
-	volatile u16	mclken_div_psc1;/* MBAR_CDM + 0x2a  reg10 byte2,3 */
-    
-	volatile u16	reserved5;	/* MBAR_CDM + 0x2c  reg11 byte0,1 */
-	volatile u16	mclken_div_psc2;/* MBAR_CDM + 0x2e  reg11 byte2,3 */
-		
-	volatile u16	reserved6;	/* MBAR_CDM + 0x30  reg12 byte0,1 */
-	volatile u16	mclken_div_psc3;/* MBAR_CDM + 0x32  reg12 byte2,3 */
-    
-	volatile u16	reserved7;	/* MBAR_CDM + 0x34  reg13 byte0,1 */
-	volatile u16	mclken_div_psc6;/* MBAR_CDM + 0x36  reg13 byte2,3 */
+	u32	jtag_id;		/* CDM + 0x00  reg0 read only */
+	u32	rstcfg;			/* CDM + 0x04  reg1 read only */
+	u32	breadcrumb;		/* CDM + 0x08  reg2 */
+
+	u8	mem_clk_sel;		/* CDM + 0x0c  reg3 byte0 */
+	u8	xlb_clk_sel;		/* CDM + 0x0d  reg3 byte1 read only */
+	u8	ipb_clk_sel;		/* CDM + 0x0e  reg3 byte2 */
+	u8	pci_clk_sel;		/* CDM + 0x0f  reg3 byte3 */
+
+	u8	ext_48mhz_en;		/* CDM + 0x10  reg4 byte0 */
+	u8	fd_enable;		/* CDM + 0x11  reg4 byte1 */
+	u16	fd_counters;		/* CDM + 0x12  reg4 byte2,3 */
+
+	u32	clk_enables;		/* CDM + 0x14  reg5 */
+
+	u8	osc_disable;		/* CDM + 0x18  reg6 byte0 */
+	u8	reserved0[3];		/* CDM + 0x19  reg6 byte1,2,3 */
+
+	u8	ccs_sleep_enable;	/* CDM + 0x1c  reg7 byte0 */
+	u8	osc_sleep_enable;	/* CDM + 0x1d  reg7 byte1 */
+	u8	reserved1;		/* CDM + 0x1e  reg7 byte2 */
+	u8	ccs_qreq_test;		/* CDM + 0x1f  reg7 byte3 */
+
+	u8	soft_reset;		/* CDM + 0x20  u8 byte0 */
+	u8	no_ckstp;		/* CDM + 0x21  u8 byte0 */
+	u8	reserved2[2];		/* CDM + 0x22  u8 byte1,2,3 */
+
+	u8	pll_lock;		/* CDM + 0x24  reg9 byte0 */
+	u8	pll_looselock;		/* CDM + 0x25  reg9 byte1 */
+	u8	pll_sm_lockwin;		/* CDM + 0x26  reg9 byte2 */
+	u8	reserved3;		/* CDM + 0x27  reg9 byte3 */
+
+	u16	reserved4;		/* CDM + 0x28  reg10 byte0,1 */
+	u16	mclken_div_psc1;	/* CDM + 0x2a  reg10 byte2,3 */
+
+	u16	reserved5;		/* CDM + 0x2c  reg11 byte0,1 */
+	u16	mclken_div_psc2;	/* CDM + 0x2e  reg11 byte2,3 */
+
+	u16	reserved6;		/* CDM + 0x30  reg12 byte0,1 */
+	u16	mclken_div_psc3;	/* CDM + 0x32  reg12 byte2,3 */
+
+	u16	reserved7;		/* CDM + 0x34  reg13 byte0,1 */
+	u16	mclken_div_psc6;	/* CDM + 0x36  reg13 byte2,3 */
 };
 
 #endif /* __ASSEMBLY__ */

include/asm-ppc/mpc52xx_psc.h

@@ -19,8 +19,8 @@
  * kind, whether express or implied.
  */
 
-#ifndef __MPC52xx_PSC_H__
-#define __MPC52xx_PSC_H__
+#ifndef __ASM_MPC52xx_PSC_H__
+#define __ASM_MPC52xx_PSC_H__
 
 #include <asm/types.h>
 
@@ -95,97 +95,97 @@
 
 /* Structure of the hardware registers */
 struct mpc52xx_psc {
-	volatile u8		mode;		/* PSC + 0x00 */
-	volatile u8		reserved0[3];
-	union {					/* PSC + 0x04 */
-		volatile u16	status;
-		volatile u16	clock_select;
+	u8		mode;		/* PSC + 0x00 */
+	u8		reserved0[3];
+	union {				/* PSC + 0x04 */
+		u16	status;
+		u16	clock_select;
 	} sr_csr;
 #define mpc52xx_psc_status	sr_csr.status
-#define mpc52xx_psc_clock_select	sr_csr.clock_select
-	volatile u16		reserved1;
-	volatile u8		command;	/* PSC + 0x08 */
-volatile u8		reserved2[3];
-	union {					/* PSC + 0x0c */
-		volatile u8	buffer_8;
-		volatile u16	buffer_16;
-		volatile u32	buffer_32;
+#define mpc52xx_psc_clock_select sr_csr.clock_select
+	u16		reserved1;
+	u8		command;	/* PSC + 0x08 */
+	u8		reserved2[3];
+	union {				/* PSC + 0x0c */
+		u8	buffer_8;
+		u16	buffer_16;
+		u32	buffer_32;
 	} buffer;
 #define mpc52xx_psc_buffer_8	buffer.buffer_8
 #define mpc52xx_psc_buffer_16	buffer.buffer_16
 #define mpc52xx_psc_buffer_32	buffer.buffer_32
-	union {					/* PSC + 0x10 */
-		volatile u8	ipcr;
-		volatile u8	acr;
+	union {				/* PSC + 0x10 */
+		u8	ipcr;
+		u8	acr;
 	} ipcr_acr;
 #define mpc52xx_psc_ipcr	ipcr_acr.ipcr
 #define mpc52xx_psc_acr		ipcr_acr.acr
-	volatile u8		reserved3[3];
-	union {					/* PSC + 0x14 */
-		volatile u16	isr;
-		volatile u16	imr;
+	u8		reserved3[3];
+	union {				/* PSC + 0x14 */
+		u16	isr;
+		u16	imr;
 	} isr_imr;
 #define mpc52xx_psc_isr		isr_imr.isr
 #define mpc52xx_psc_imr		isr_imr.imr
-	volatile u16		reserved4;
-	volatile u8		ctur;		/* PSC + 0x18 */
-	volatile u8		reserved5[3];
-	volatile u8		ctlr;		/* PSC + 0x1c */
-	volatile u8		reserved6[3];
-	volatile u16		ccr;		/* PSC + 0x20 */
-	volatile u8		reserved7[14];
-	volatile u8		ivr;		/* PSC + 0x30 */
-	volatile u8		reserved8[3];
-	volatile u8		ip;		/* PSC + 0x34 */
-	volatile u8		reserved9[3];
-	volatile u8		op1;		/* PSC + 0x38 */
-	volatile u8		reserved10[3];
-	volatile u8		op0;		/* PSC + 0x3c */
-	volatile u8		reserved11[3];
-	volatile u32		sicr;		/* PSC + 0x40 */
-	volatile u8		ircr1;		/* PSC + 0x44 */
-	volatile u8		reserved13[3];
-	volatile u8		ircr2;		/* PSC + 0x44 */
-	volatile u8		reserved14[3];
-	volatile u8		irsdr;		/* PSC + 0x4c */
-	volatile u8		reserved15[3];
-	volatile u8		irmdr;		/* PSC + 0x50 */
-	volatile u8		reserved16[3];
-	volatile u8		irfdr;		/* PSC + 0x54 */
-	volatile u8		reserved17[3];
-	volatile u16		rfnum;		/* PSC + 0x58 */
-	volatile u16		reserved18;
-	volatile u16		tfnum;		/* PSC + 0x5c */
-	volatile u16		reserved19;
-	volatile u32		rfdata;		/* PSC + 0x60 */
-	volatile u16		rfstat;		/* PSC + 0x64 */
-	volatile u16		reserved20;
-	volatile u8		rfcntl;		/* PSC + 0x68 */
-	volatile u8		reserved21[5];
-	volatile u16		rfalarm;	/* PSC + 0x6e */
-	volatile u16		reserved22;
-	volatile u16		rfrptr;		/* PSC + 0x72 */
-	volatile u16		reserved23;
-	volatile u16		rfwptr;		/* PSC + 0x76 */
-	volatile u16		reserved24;
-	volatile u16		rflrfptr;	/* PSC + 0x7a */
-	volatile u16		reserved25;
-	volatile u16		rflwfptr;	/* PSC + 0x7e */
-	volatile u32		tfdata;		/* PSC + 0x80 */
-	volatile u16		tfstat;		/* PSC + 0x84 */
-	volatile u16		reserved26;
-	volatile u8		tfcntl;		/* PSC + 0x88 */
-	volatile u8		reserved27[5];
-	volatile u16		tfalarm;	/* PSC + 0x8e */
-	volatile u16		reserved28;
-	volatile u16		tfrptr;		/* PSC + 0x92 */
-	volatile u16		reserved29;
-	volatile u16		tfwptr;		/* PSC + 0x96 */
-	volatile u16		reserved30;
-	volatile u16		tflrfptr;	/* PSC + 0x9a */
-	volatile u16		reserved31;
-	volatile u16		tflwfptr;	/* PSC + 0x9e */
+	u16		reserved4;
+	u8		ctur;		/* PSC + 0x18 */
+	u8		reserved5[3];
+	u8		ctlr;		/* PSC + 0x1c */
+	u8		reserved6[3];
+	u16		ccr;		/* PSC + 0x20 */
+	u8		reserved7[14];
+	u8		ivr;		/* PSC + 0x30 */
+	u8		reserved8[3];
+	u8		ip;		/* PSC + 0x34 */
+	u8		reserved9[3];
+	u8		op1;		/* PSC + 0x38 */
+	u8		reserved10[3];
+	u8		op0;		/* PSC + 0x3c */
+	u8		reserved11[3];
+	u32		sicr;		/* PSC + 0x40 */
+	u8		ircr1;		/* PSC + 0x44 */
+	u8		reserved13[3];
+	u8		ircr2;		/* PSC + 0x44 */
+	u8		reserved14[3];
+	u8		irsdr;		/* PSC + 0x4c */
+	u8		reserved15[3];
+	u8		irmdr;		/* PSC + 0x50 */
+	u8		reserved16[3];
+	u8		irfdr;		/* PSC + 0x54 */
+	u8		reserved17[3];
+	u16		rfnum;		/* PSC + 0x58 */
+	u16		reserved18;
+	u16		tfnum;		/* PSC + 0x5c */
+	u16		reserved19;
+	u32		rfdata;		/* PSC + 0x60 */
+	u16		rfstat;		/* PSC + 0x64 */
+	u16		reserved20;
+	u8		rfcntl;		/* PSC + 0x68 */
+	u8		reserved21[5];
+	u16		rfalarm;	/* PSC + 0x6e */
+	u16		reserved22;
+	u16		rfrptr;		/* PSC + 0x72 */
+	u16		reserved23;
+	u16		rfwptr;		/* PSC + 0x76 */
+	u16		reserved24;
+	u16		rflrfptr;	/* PSC + 0x7a */
+	u16		reserved25;
+	u16		rflwfptr;	/* PSC + 0x7e */
+	u32		tfdata;		/* PSC + 0x80 */
+	u16		tfstat;		/* PSC + 0x84 */
+	u16		reserved26;
+	u8		tfcntl;		/* PSC + 0x88 */
+	u8		reserved27[5];
+	u16		tfalarm;	/* PSC + 0x8e */
+	u16		reserved28;
+	u16		tfrptr;		/* PSC + 0x92 */
+	u16		reserved29;
+	u16		tfwptr;		/* PSC + 0x96 */
+	u16		reserved30;
+	u16		tflrfptr;	/* PSC + 0x9a */
+	u16		reserved31;
+	u16		tflwfptr;	/* PSC + 0x9e */
 };
 
 
-#endif  /* __MPC52xx_PSC_H__ */
+#endif  /* __ASM_MPC52xx_PSC_H__ */