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Commit eec262d1 authored by Mark Brown's avatar Mark Brown
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Merge remote-tracking branch 'spi/for-5.12' into spi-next

parents 110bc220 d2275139
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Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
View file @ eec262d1
......@@ -25,6 +25,7 @@ properties:
- enum:
- allwinner,sun8i-r40-spi
- allwinner,sun50i-h6-spi
- allwinner,sun50i-h616-spi
- const: allwinner,sun8i-h3-spi
reg:
......
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt → Documentation/devicetree/bindings/spi/cadence-quadspi.txt
View file @ eec262d1
......@@ -5,6 +5,7 @@ Required properties:
Generic default - "cdns,qspi-nor".
For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
- reg : Contains two entries, each of which is a tuple consisting of a
physical address and length. The first entry is the address and
length of the controller register set. The second entry is the
......
Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml 0 → 100644
View file @ eec262d1
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Tegra Quad SPI Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jonathan Hunter <jonathanh@nvidia.com>
allOf:
- $ref: "spi-controller.yaml#"
properties:
compatible:
enum:
- nvidia,tegra210-qspi
- nvidia,tegra186-qspi
- nvidia,tegra194-qspi
reg:
maxItems: 1
interrupts:
maxItems: 1
clock-names:
items:
- const: qspi
- const: qspi_out
clocks:
maxItems: 2
resets:
maxItems: 1
dmas:
maxItems: 2
dma-names:
items:
- const: rx
- const: tx
patternProperties:
"@[0-9a-f]+":
type: object
properties:
spi-rx-bus-width:
enum: [1, 2, 4]
spi-tx-bus-width:
enum: [1, 2, 4]
nvidia,tx-clk-tap-delay:
description:
Delays the clock going out to device with this tap value.
Tap value varies based on platform design trace lengths from Tegra
QSPI to corresponding slave device.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 31
nvidia,rx-clk-tap-delay:
description:
Delays the clock coming in from the device with this tap value.
Tap value varies based on platform design trace lengths from Tegra
QSPI to corresponding slave device.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 255
required:
- reg
required:
- compatible
- reg
- interrupts
- clock-names
- clocks
- resets
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/reset/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
spi@70410000 {
compatible = "nvidia,tegra210-qspi";
reg = <0x70410000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_QSPI>,
<&tegra_car TEGRA210_CLK_QSPI_PM>;
clock-names = "qspi", "qspi_out";
resets = <&tegra_car 211>;
dmas = <&apbdma 5>, <&apbdma 5>;
dma-names = "rx", "tx";
flash@0 {
compatible = "spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
nvidia,tx-clk-tap-delay = <0>;
nvidia,rx-clk-tap-delay = <0>;
};
};
Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml 0 → 100644
View file @ eec262d1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/realtek,rtl-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek RTL838x/RTL839x SPI controller
maintainers:
- Bert Vermeulen <bert@biot.com>
- Birger Koblitz <mail@birger-koblitz.de>
allOf:
- $ref: "spi-controller.yaml#"
properties:
compatible:
oneOf:
- const: realtek,rtl8380-spi
- const: realtek,rtl8382-spi
- const: realtek,rtl8391-spi
- const: realtek,rtl8392-spi
- const: realtek,rtl8393-spi
reg:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
spi: spi@1200 {
compatible = "realtek,rtl8382-spi";
reg = <0x1200 0x100>;
#address-cells = <1>;
#size-cells = <0>;
};
Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml
View file @ eec262d1
......@@ -47,6 +47,7 @@ properties:
- renesas,msiof-r8a77980 # R-Car V3H
- renesas,msiof-r8a77990 # R-Car E3
- renesas,msiof-r8a77995 # R-Car D3
- renesas,msiof-r8a779a0 # R-Car V3U
- const: renesas,rcar-gen3-msiof # generic R-Car Gen3 and RZ/G2
# compatible device
- items:
......
Documentation/devicetree/bindings/spi/spi-controller.yaml
View file @ eec262d1
......@@ -152,8 +152,9 @@ patternProperties:
spi-rx-bus-width:
description:
Bus width to the SPI bus used for read transfers.
If 0 is provided, then no RX will be possible on this device.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 4, 8]
enum: [0, 1, 2, 4, 8]
default: 1
spi-rx-delay-us:
......@@ -163,8 +164,9 @@ patternProperties:
spi-tx-bus-width:
description:
Bus width to the SPI bus used for write transfers.
If 0 is provided, then no TX will be possible on this device.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 4, 8]
enum: [0, 1, 2, 4, 8]
default: 1
spi-tx-delay-us:
......
Documentation/devicetree/bindings/spi/spi-sirf.txt deleted 100644 → 0
View file @ 110bc220
* CSR SiRFprimaII Serial Peripheral Interface
Required properties:
- compatible : Should be "sirf,prima2-spi", "sirf,prima2-usp"
or "sirf,atlas7-usp"
- reg : Offset and length of the register set for the device
- interrupts : Should contain SPI interrupt
- resets: phandle to the reset controller asserting this device in
reset
See ../reset/reset.txt for details.
- dmas : Must contain an entry for each entry in clock-names.
See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
- rx
- tx
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- #address-cells: Number of cells required to define a chip select
address on the SPI bus. Should be set to 1.
- #size-cells: Should be zero.
Optional properties:
- spi-max-frequency: Specifies maximum SPI clock frequency,
Units - Hz. Definition as per
Documentation/devicetree/bindings/spi/spi-bus.txt
- cs-gpios: should specify GPIOs used for chipselects.
Example:
spi0: spi@b00d0000 {
compatible = "sirf,prima2-spi";
reg = <0xb00d0000 0x10000>;
interrupts = <15>;
dmas = <&dmac1 9>,
<&dmac1 4>;
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clks 19>;
resets = <&rstc 26>;
};
MAINTAINERS
View file @ eec262d1
......@@ -17502,6 +17502,14 @@ M: Laxman Dewangan <ldewangan@nvidia.com>
S: Supported
F: drivers/spi/spi-tegra*
TEGRA QUAD SPI DRIVER
M: Thierry Reding <thierry.reding@gmail.com>
M: Jonathan Hunter <jonathanh@nvidia.com>
M: Sowjanya Komatineni <skomatineni@nvidia.com>
L: linux-tegra@vger.kernel.org
S: Maintained
F: drivers/spi/spi-tegra210-quad.c
TEGRA VIDEO DRIVER
M: Thierry Reding <thierry.reding@gmail.com>
M: Jonathan Hunter <jonathanh@nvidia.com>
......
drivers/spi/Kconfig
View file @ eec262d1
......@@ -203,7 +203,7 @@ config SPI_CADENCE
config SPI_CADENCE_QUADSPI
tristate "Cadence Quad SPI controller"
depends on OF && (ARM || ARM64 || COMPILE_TEST)
depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)
help
Enable support for the Cadence Quad SPI Flash controller.
......@@ -292,13 +292,6 @@ config SPI_DLN2
This driver can also be built as a module. If so, the module
will be called spi-dln2.
config SPI_EFM32
tristate "EFM32 SPI controller"
depends on OF && ARM && (ARCH_EFM32 || COMPILE_TEST)
select SPI_BITBANG
help
Driver for the spi controller found on Energy Micro's EFM32 SoCs.
config SPI_EP93XX
tristate "Cirrus Logic EP93xx SPI controller"
depends on ARCH_EP93XX || COMPILE_TEST
......@@ -650,7 +643,7 @@ config SPI_RPCIF
tristate "Renesas RPC-IF SPI driver"
depends on RENESAS_RPCIF
help
SPI driver for Renesas R-Car Gen3 RPC-IF.
SPI driver for Renesas R-Car Gen3 or RZ/G2 RPC-IF.
config SPI_RSPI
tristate "Renesas RSPI/QSPI controller"
......@@ -751,13 +744,6 @@ config SPI_SIFIVE
help
This exposes the SPI controller IP from SiFive.
config SPI_SIRF
tristate "CSR SiRFprimaII SPI controller"
depends on SIRF_DMA
select SPI_BITBANG
help
SPI driver for CSR SiRFprimaII SoCs
config SPI_SLAVE_MT27XX
tristate "MediaTek SPI slave device"
depends on ARCH_MEDIATEK || COMPILE_TEST
......@@ -843,6 +829,15 @@ config SPI_MXS
help
SPI driver for Freescale MXS devices.
config SPI_TEGRA210_QUAD
tristate "NVIDIA Tegra QSPI Controller"
depends on ARCH_TEGRA || COMPILE_TEST
depends on RESET_CONTROLLER
help
QSPI driver for NVIDIA Tegra QSPI Controller interface. This
controller is different from the SPI controller and is available
on Tegra SoCs starting from Tegra210.
config SPI_TEGRA114
tristate "NVIDIA Tegra114 SPI Controller"
depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
......@@ -885,12 +880,6 @@ config SPI_TOPCLIFF_PCH
This driver also supports the ML7213/ML7223/ML7831, a companion chip
for the Atom E6xx series and compatible with the Intel EG20T PCH.
config SPI_TXX9
tristate "Toshiba TXx9 SPI controller"
depends on GPIOLIB && (CPU_TX49XX || COMPILE_TEST)
help
SPI driver for Toshiba TXx9 MIPS SoCs
config SPI_UNIPHIER
tristate "Socionext UniPhier SPI Controller"
depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
......
drivers/spi/Makefile
View file @ eec262d1
......@@ -42,7 +42,6 @@ spi-dw-$(CONFIG_SPI_DW_DMA) += spi-dw-dma.o
obj-$(CONFIG_SPI_DW_BT1) += spi-dw-bt1.o
obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
obj-$(CONFIG_SPI_DW_PCI) += spi-dw-pci.o
obj-$(CONFIG_SPI_EFM32) += spi-efm32.o
obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
obj-$(CONFIG_SPI_FSI) += spi-fsi.o
......@@ -94,6 +93,7 @@ obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o
obj-$(CONFIG_SPI_QUP) += spi-qup.o
obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o
obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o
obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
......@@ -105,7 +105,6 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o
obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
obj-$(CONFIG_SPI_SIRF) += spi-sirf.o
obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o
obj-$(CONFIG_SPI_SPRD) += spi-sprd.o
obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o
......@@ -115,6 +114,7 @@ obj-$(CONFIG_SPI_ST_SSC4) += spi-st-ssc4.o
obj-$(CONFIG_SPI_SUN4I) += spi-sun4i.o
obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
obj-$(CONFIG_SPI_SYNQUACER) += spi-synquacer.o
obj-$(CONFIG_SPI_TEGRA210_QUAD) += spi-tegra210-quad.o
obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o
obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o
obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o
......@@ -122,7 +122,6 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
spi-thunderx-objs := spi-cavium.o spi-cavium-thunderx.o
obj-$(CONFIG_SPI_THUNDERX) += spi-thunderx.o
obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
obj-$(CONFIG_SPI_UNIPHIER) += spi-uniphier.o
obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o
obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
......
drivers/spi/atmel-quadspi.c
View file @ eec262d1
......@@ -657,6 +657,7 @@ static int __maybe_unused atmel_qspi_suspend(struct device *dev)
struct spi_controller *ctrl = dev_get_drvdata(dev);
struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
clk_disable_unprepare(aq->qspick);
clk_disable_unprepare(aq->pclk);
......
drivers/spi/spi-atmel.c
View file @ eec262d1
......@@ -1590,7 +1590,7 @@ static int atmel_spi_probe(struct platform_device *pdev)
if (ret == 0) {
as->use_dma = true;
} else if (ret == -EPROBE_DEFER) {
return ret;
goto out_unmap_regs;
}
} else if (as->caps.has_pdc_support) {
as->use_pdc = true;
......
drivers/spi/spi-au1550.c
View file @ eec262d1
......@@ -26,7 +26,7 @@
#include <asm/mach-au1x00/au1550_spi.h>
static unsigned usedma = 1;
static unsigned int usedma = 1;
module_param(usedma, uint, 0644);
/*
......@@ -43,9 +43,9 @@ struct au1550_spi {
volatile psc_spi_t __iomem *regs;
int irq;
unsigned len;
unsigned tx_count;
unsigned rx_count;
unsigned int len;
unsigned int tx_count;
unsigned int rx_count;
const u8 *tx;
u8 *rx;
......@@ -56,14 +56,14 @@ struct au1550_spi {
struct completion master_done;
unsigned usedma;
unsigned int usedma;
u32 dma_tx_id;
u32 dma_rx_id;
u32 dma_tx_ch;
u32 dma_rx_ch;
u8 *dma_rx_tmpbuf;
unsigned dma_rx_tmpbuf_size;
unsigned int dma_rx_tmpbuf_size;
u32 dma_rx_tmpbuf_addr;
struct spi_master *master;
......@@ -74,8 +74,7 @@ struct au1550_spi {
/* we use an 8-bit memory device for dma transfers to/from spi fifo */
static dbdev_tab_t au1550_spi_mem_dbdev =
{
static dbdev_tab_t au1550_spi_mem_dbdev = {
.dev_id = DBDMA_MEM_CHAN,
.dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
.dev_tsize = 0,
......@@ -99,7 +98,7 @@ static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
* BRG valid range is 4..63
* DIV valid range is 0..3
*/
static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned int speed_hz)
{
u32 mainclk_hz = hw->pdata->mainclk_hz;
u32 div, brg;
......@@ -161,7 +160,7 @@ static void au1550_spi_reset_fifos(struct au1550_spi *hw)
static void au1550_spi_chipsel(struct spi_device *spi, int value)
{
struct au1550_spi *hw = spi_master_get_devdata(spi->master);
unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
u32 cfg, stat;
switch (value) {
......@@ -221,7 +220,7 @@ static void au1550_spi_chipsel(struct spi_device *spi, int value)
static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
{
struct au1550_spi *hw = spi_master_get_devdata(spi->master);
unsigned bpw, hz;
unsigned int bpw, hz;
u32 cfg, stat;
if (t) {
......@@ -276,7 +275,7 @@ static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
* spi master done event irq is not generated unless rx fifo is empty (emptied)
* so we need rx tmp buffer to use for rx dma if user does not provide one
*/
static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned int size)
{
hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
if (!hw->dma_rx_tmpbuf)
......@@ -399,10 +398,10 @@ static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
DMA_FROM_DEVICE);
}
/* unmap buffers if mapped above */
if (t->rx_buf && t->rx_dma == 0 )
if (t->rx_buf && t->rx_dma == 0)
dma_unmap_single(hw->dev, dma_rx_addr, t->len,
DMA_FROM_DEVICE);
if (t->tx_buf && t->tx_dma == 0 )
if (t->tx_buf && t->tx_dma == 0)
dma_unmap_single(hw->dev, dma_tx_addr, t->len,
DMA_TO_DEVICE);
......@@ -447,8 +446,8 @@ static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
"dma transfer: receive FIFO overflow!\n");
else
dev_err(hw->dev,
"dma transfer: unexpected SPI error "
"(event=0x%x stat=0x%x)!\n", evnt, stat);
"dma transfer: unexpected SPI error (event=0x%x stat=0x%x)!\n",
evnt, stat);
complete(&hw->master_done);
return IRQ_HANDLED;
......@@ -493,12 +492,12 @@ static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
wmb(); /* drain writebuffer */ \
}
AU1550_SPI_RX_WORD(8,0xff)
AU1550_SPI_RX_WORD(16,0xffff)
AU1550_SPI_RX_WORD(32,0xffffff)
AU1550_SPI_TX_WORD(8,0xff)
AU1550_SPI_TX_WORD(16,0xffff)
AU1550_SPI_TX_WORD(32,0xffffff)
AU1550_SPI_RX_WORD(8, 0xff)
AU1550_SPI_RX_WORD(16, 0xffff)
AU1550_SPI_RX_WORD(32, 0xffffff)
AU1550_SPI_TX_WORD(8, 0xff)
AU1550_SPI_TX_WORD(16, 0xffff)
AU1550_SPI_TX_WORD(32, 0xffffff)
static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
{
......@@ -567,8 +566,8 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
au1550_spi_mask_ack_all(hw);
au1550_spi_reset_fifos(hw);
dev_err(hw->dev,
"pio transfer: unexpected SPI error "
"(event=0x%x stat=0x%x)!\n", evnt, stat);
"pio transfer: unexpected SPI error (event=0x%x stat=0x%x)!\n",
evnt, stat);
complete(&hw->master_done);
return IRQ_HANDLED;
}
......@@ -636,12 +635,14 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
{
struct au1550_spi *hw = spi_master_get_devdata(spi->master);
return hw->txrx_bufs(spi, t);
}
static irqreturn_t au1550_spi_irq(int irq, void *dev)
{
struct au1550_spi *hw = dev;
return hw->irq_callback(hw);
}
......@@ -872,6 +873,7 @@ static int au1550_spi_probe(struct platform_device *pdev)
{
int min_div = (2 << 0) * (2 * (4 + 1));
int max_div = (2 << 3) * (2 * (63 + 1));
master->max_speed_hz = hw->pdata->mainclk_hz / min_div;
master->min_speed_hz =
hw->pdata->mainclk_hz / (max_div + 1) + 1;
......@@ -972,8 +974,7 @@ static int __init au1550_spi_init(void)
if (usedma) {
ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
if (!ddma_memid)
printk(KERN_ERR "au1550-spi: cannot add memory"
"dbdma device\n");
printk(KERN_ERR "au1550-spi: cannot add memory dbdma device\n");
}
return platform_driver_register(&au1550_spi_drv);
}
......
drivers/spi/spi-bcm-qspi.c
View file @ eec262d1
......@@ -881,7 +881,7 @@ static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi,
* when using flex mode we need to send
* the upper address byte to bspi
*/
if (bcm_qspi_bspi_ver_three(qspi) == false) {
if (!bcm_qspi_bspi_ver_three(qspi)) {
addr = from & 0xff000000;
bcm_qspi_write(qspi, BSPI,
BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr);
......
drivers/spi/spi-bcm2835.c
View file @ eec262d1
......@@ -386,7 +386,7 @@ static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
/* Transfer complete - reset SPI HW */
bcm2835_spi_reset_hw(bs);
/* wake up the framework */
complete(&bs->ctlr->xfer_completion);
spi_finalize_current_transfer(bs->ctlr);
}
return IRQ_HANDLED;
......@@ -608,7 +608,7 @@ static void bcm2835_spi_dma_rx_done(void *data)
bcm2835_spi_reset_hw(bs);
/* and mark as completed */;
complete(&ctlr->xfer_completion);
spi_finalize_current_transfer(ctlr);
}
/**
......@@ -640,7 +640,7 @@ static void bcm2835_spi_dma_tx_done(void *data)
bcm2835_spi_undo_prologue(bs);
bcm2835_spi_reset_hw(bs);
complete(&ctlr->xfer_completion);
spi_finalize_current_transfer(ctlr);
}
/**
......@@ -1307,6 +1307,8 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
return dev_err_probe(&pdev->dev, PTR_ERR(bs->clk),
"could not get clk\n");
ctlr->max_speed_hz = clk_get_rate(bs->clk) / 2;
bs->irq = platform_get_irq(pdev, 0);
if (bs->irq <= 0)
return bs->irq ? bs->irq : -ENODEV;
......
drivers/spi/spi-bcm2835aux.c
View file @ eec262d1
......@@ -254,7 +254,7 @@ static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
/* and if rx_len is 0 then disable interrupts and wake up completion */
if (!bs->rx_len) {
bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
complete(&master->xfer_completion);
spi_finalize_current_transfer(master);
}
return IRQ_HANDLED;
......
drivers/spi/spi-cadence-quadspi.c
View file @ eec262d1
......@@ -52,6 +52,7 @@ struct cqspi_flash_pdata {
u8 inst_width;
u8 addr_width;
u8 data_width;
bool dtr;
u8 cs;
};
......@@ -75,6 +76,7 @@ struct cqspi_st {
bool is_decoded_cs;
u32 fifo_depth;
u32 fifo_width;
u32 num_chipselect;
bool rclk_en;
u32 trigger_address;
u32 wr_delay;
......@@ -111,6 +113,8 @@ struct cqspi_driver_platdata {
#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
#define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
#define CQSPI_REG_CONFIG_BAUD_LSB 19
#define CQSPI_REG_CONFIG_DTR_PROTO BIT(24)
#define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30)
#define CQSPI_REG_CONFIG_IDLE_LSB 31
#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
#define CQSPI_REG_CONFIG_BAUD_MASK 0xF
......@@ -173,6 +177,9 @@ struct cqspi_driver_platdata {
#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
#define CQSPI_REG_WR_COMPLETION_CTRL 0x38
#define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14)
#define CQSPI_REG_IRQSTATUS 0x40
#define CQSPI_REG_IRQMASK 0x44
......@@ -188,6 +195,7 @@ struct cqspi_driver_platdata {
#define CQSPI_REG_CMDCTRL 0x90
#define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
......@@ -198,6 +206,7 @@ struct cqspi_driver_platdata {
#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
#define CQSPI_REG_INDIRECTWR 0x70
#define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
......@@ -214,6 +223,14 @@ struct cqspi_driver_platdata {
#define CQSPI_REG_CMDWRITEDATALOWER 0xA8
#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
#define CQSPI_REG_POLLING_STATUS 0xB0
#define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16
#define CQSPI_REG_OP_EXT_LOWER 0xE0
#define CQSPI_REG_OP_EXT_READ_LSB 24
#define CQSPI_REG_OP_EXT_WRITE_LSB 16
#define CQSPI_REG_OP_EXT_STIG_LSB 0
/* Interrupt status bits */
#define CQSPI_REG_IRQ_MODE_ERR BIT(0)
#define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
......@@ -288,6 +305,80 @@ static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata)
return rdreg;
}
static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr)
{
unsigned int dummy_clk;
dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
if (dtr)
dummy_clk /= 2;
return dummy_clk;
}
static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
const struct spi_mem_op *op)
{
f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
f_pdata->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr;
switch (op->data.buswidth) {
case 0:
break;
case 1:
f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
break;
case 2:
f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
break;
case 4:
f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
break;
case 8:
f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
break;
default:
return -EINVAL;
}
/* Right now we only support 8-8-8 DTR mode. */
if (f_pdata->dtr) {
switch (op->cmd.buswidth) {
case 0:
break;
case 8:
f_pdata->inst_width = CQSPI_INST_TYPE_OCTAL;
break;
default:
return -EINVAL;
}
switch (op->addr.buswidth) {
case 0:
break;
case 8:
f_pdata->addr_width = CQSPI_INST_TYPE_OCTAL;
break;
default:
return -EINVAL;
}
switch (op->data.buswidth) {
case 0:
break;
case 8:
f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
break;
default:
return -EINVAL;
}
}
return 0;
}
static int cqspi_wait_idle(struct cqspi_st *cqspi)
{
const unsigned int poll_idle_retry = 3;
......@@ -345,19 +436,85 @@ static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
return cqspi_wait_idle(cqspi);
}
static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata,
const struct spi_mem_op *op,
unsigned int shift)
{
struct cqspi_st *cqspi = f_pdata->cqspi;
void __iomem *reg_base = cqspi->iobase;
unsigned int reg;
u8 ext;
if (op->cmd.nbytes != 2)
return -EINVAL;
/* Opcode extension is the LSB. */
ext = op->cmd.opcode & 0xff;
reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);
reg &= ~(0xff << shift);
reg |= ext << shift;
writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
return 0;
}
static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
const struct spi_mem_op *op, unsigned int shift,
bool enable)
{
struct cqspi_st *cqspi = f_pdata->cqspi;
void __iomem *reg_base = cqspi->iobase;
unsigned int reg;
int ret;
reg = readl(reg_base + CQSPI_REG_CONFIG);
/*
* We enable dual byte opcode here. The callers have to set up the
* extension opcode based on which type of operation it is.
*/
if (enable) {
reg |= CQSPI_REG_CONFIG_DTR_PROTO;
reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
/* Set up command opcode extension. */
ret = cqspi_setup_opcode_ext(f_pdata, op, shift);
if (ret)
return ret;
} else {
reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
}
writel(reg, reg_base + CQSPI_REG_CONFIG);
return cqspi_wait_idle(cqspi);
}
static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
const struct spi_mem_op *op)
{
struct cqspi_st *cqspi = f_pdata->cqspi;
void __iomem *reg_base = cqspi->iobase;
u8 *rxbuf = op->data.buf.in;
u8 opcode = op->cmd.opcode;
u8 opcode;
size_t n_rx = op->data.nbytes;
unsigned int rdreg;
unsigned int reg;
unsigned int dummy_clk;
size_t read_len;
int status;
status = cqspi_set_protocol(f_pdata, op);
if (status)
return status;
status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
f_pdata->dtr);
if (status)
return status;
if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
dev_err(&cqspi->pdev->dev,
"Invalid input argument, len %zu rxbuf 0x%p\n",
......@@ -365,11 +522,24 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata,
return -EINVAL;
}
if (f_pdata->dtr)
opcode = op->cmd.opcode >> 8;
else
opcode = op->cmd.opcode;
reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
rdreg = cqspi_calc_rdreg(f_pdata);
writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
return -EOPNOTSUPP;
if (dummy_clk)
reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
<< CQSPI_REG_CMDCTRL_DUMMY_LSB;
reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
/* 0 means 1 byte. */
......@@ -401,12 +571,22 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
{
struct cqspi_st *cqspi = f_pdata->cqspi;
void __iomem *reg_base = cqspi->iobase;
const u8 opcode = op->cmd.opcode;
u8 opcode;
const u8 *txbuf = op->data.buf.out;
size_t n_tx = op->data.nbytes;
unsigned int reg;
unsigned int data;
size_t write_len;
int ret;
ret = cqspi_set_protocol(f_pdata, op);
if (ret)
return ret;
ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB,
f_pdata->dtr);
if (ret)
return ret;
if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) {
dev_err(&cqspi->pdev->dev,
......@@ -415,6 +595,14 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata,
return -EINVAL;
}
reg = cqspi_calc_rdreg(f_pdata);
writel(reg, reg_base + CQSPI_REG_RD_INSTR);
if (f_pdata->dtr)
opcode = op->cmd.opcode >> 8;
else
opcode = op->cmd.opcode;
reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
if (op->addr.nbytes) {
......@@ -454,14 +642,27 @@ static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata,
void __iomem *reg_base = cqspi->iobase;
unsigned int dummy_clk = 0;
unsigned int reg;
int ret;
u8 opcode;
ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB,
f_pdata->dtr);
if (ret)
return ret;
reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
if (f_pdata->dtr)
opcode = op->cmd.opcode >> 8;
else
opcode = op->cmd.opcode;
reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
reg |= cqspi_calc_rdreg(f_pdata);
/* Setup dummy clock cycles */
dummy_clk = op->dummy.nbytes * 8;
dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr);
if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
dummy_clk = CQSPI_DUMMY_CLKS_MAX;
return -EOPNOTSUPP;
if (dummy_clk)
reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
......@@ -573,15 +774,43 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
const struct spi_mem_op *op)
{
unsigned int reg;
int ret;
struct cqspi_st *cqspi = f_pdata->cqspi;
void __iomem *reg_base = cqspi->iobase;
u8 opcode;
ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB,
f_pdata->dtr);
if (ret)
return ret;
if (f_pdata->dtr)
opcode = op->cmd.opcode >> 8;
else
opcode = op->cmd.opcode;
/* Set opcode. */
reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
writel(reg, reg_base + CQSPI_REG_WR_INSTR);
reg = cqspi_calc_rdreg(f_pdata);
writel(reg, reg_base + CQSPI_REG_RD_INSTR);
if (f_pdata->dtr) {
/*
* Some flashes like the cypress Semper flash expect a 4-byte
* dummy address with the Read SR command in DTR mode, but this
* controller does not support sending address with the Read SR
* command. So, disable write completion polling on the
* controller's side. spi-nor will take care of polling the
* status register.
*/
reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
}
reg = readl(reg_base + CQSPI_REG_SIZE);
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
reg |= (op->addr.nbytes - 1);
......@@ -835,35 +1064,6 @@ static void cqspi_configure(struct cqspi_flash_pdata *f_pdata,
cqspi_controller_enable(cqspi, 1);
}
static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
const struct spi_mem_op *op)
{
f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
if (op->data.dir == SPI_MEM_DATA_IN) {
switch (op->data.buswidth) {
case 1:
f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
break;
case 2:
f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
break;
case 4:
f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
break;
case 8:
f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
break;
default:
return -EINVAL;
}
}
return 0;
}
static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
const struct spi_mem_op *op)
{
......@@ -881,7 +1081,16 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata,
if (ret)
return ret;
if (cqspi->use_direct_mode && ((to + len) <= cqspi->ahb_size)) {
/*
* Some flashes like the Cypress Semper flash expect a dummy 4-byte
* address (all 0s) with the read status register command in DTR mode.
* But this controller does not support sending dummy address bytes to
* the flash when it is polling the write completion register in DTR
* mode. So, we can not use direct mode when in DTR mode for writing
* data.
*/
if (!f_pdata->dtr && cqspi->use_direct_mode &&
((to + len) <= cqspi->ahb_size)) {
memcpy_toio(cqspi->ahb_base + to, buf, len);
return cqspi_wait_idle(cqspi);
}
......@@ -942,7 +1151,7 @@ static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata,
dma_async_issue_pending(cqspi->rx_chan);
if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
msecs_to_jiffies(len))) {
msecs_to_jiffies(max_t(size_t, len, 500)))) {
dmaengine_terminate_sync(cqspi->rx_chan);
dev_err(dev, "DMA wait_for_completion_timeout\n");
ret = -ETIMEDOUT;
......@@ -1010,6 +1219,26 @@ static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
return ret;
}
static bool cqspi_supports_mem_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
bool all_true, all_false;
all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr &&
op->data.dtr;
all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
!op->data.dtr;
/* Mixed DTR modes not supported. */
if (!(all_true || all_false))
return false;
if (all_true)
return spi_mem_dtr_supports_op(mem, op);
else
return spi_mem_default_supports_op(mem, op);
}
static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
struct cqspi_flash_pdata *f_pdata,
struct device_node *np)
......@@ -1070,6 +1299,9 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
return -ENXIO;
}
if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
return 0;
......@@ -1101,10 +1333,12 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
/* Enable Direct Access Controller */
reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
/* Disable direct access controller */
if (!cqspi->use_direct_mode) {
reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
}
cqspi_controller_enable(cqspi, 1);
}
......@@ -1138,6 +1372,7 @@ static const char *cqspi_get_name(struct spi_mem *mem)
static const struct spi_controller_mem_ops cqspi_mem_ops = {
.exec_op = cqspi_exec_mem_op,
.get_name = cqspi_get_name,
.supports_op = cqspi_supports_mem_op,
};
static int cqspi_setup_flash(struct cqspi_st *cqspi)
......@@ -1279,13 +1514,14 @@ static int cqspi_probe(struct platform_device *pdev)
reset_control_deassert(rstc_ocp);
cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
master->max_speed_hz = cqspi->master_ref_clk_hz;
ddata = of_device_get_match_data(dev);
if (ddata) {
if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
cqspi->master_ref_clk_hz);
if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL)
master->mode_bits |= SPI_RX_OCTAL;
master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
cqspi->use_direct_mode = true;
}
......@@ -1302,6 +1538,8 @@ static int cqspi_probe(struct platform_device *pdev)
cqspi->current_cs = -1;
cqspi->sclk = 0;
master->num_chipselect = cqspi->num_chipselect;
ret = cqspi_setup_flash(cqspi);
if (ret) {
dev_err(dev, "failed to setup flash parameters %d\n", ret);
......@@ -1390,6 +1628,10 @@ static const struct cqspi_driver_platdata am654_ospi = {
.quirks = CQSPI_NEEDS_WR_DELAY,
};
static const struct cqspi_driver_platdata intel_lgm_qspi = {
.quirks = CQSPI_DISABLE_DAC_MODE,
};
static const struct of_device_id cqspi_dt_ids[] = {
{
.compatible = "cdns,qspi-nor",
......@@ -1403,6 +1645,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
.compatible = "ti,am654-ospi",
.data = &am654_ospi,
},
{
.compatible = "intel,lgm-qspi",
.data = &intel_lgm_qspi,
},
{ /* end of table */ }
};
......@@ -1427,3 +1673,4 @@ MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");
drivers/spi/spi-clps711x.c
View file @ eec262d1
......@@ -104,7 +104,7 @@ static int spi_clps711x_probe(struct platform_device *pdev)
master->use_gpio_descriptors = true;
master->bus_num = -1;
master->mode_bits = SPI_CPHA | SPI_CS_HIGH;
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8);
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8);
master->dev.of_node = pdev->dev.of_node;
master->prepare_message = spi_clps711x_prepare_message;
master->transfer_one = spi_clps711x_transfer_one;
......
drivers/spi/spi-efm32.c deleted 100644 → 0
View file @ 110bc220
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012-2013 Uwe Kleine-Koenig for Pengutronix
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_data/efm32-spi.h>
#include <linux/of.h>
#define DRIVER_NAME "efm32-spi"
#define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask)
#define REG_CTRL 0x00
#define REG_CTRL_SYNC 0x0001
#define REG_CTRL_CLKPOL 0x0100
#define REG_CTRL_CLKPHA 0x0200
#define REG_CTRL_MSBF 0x0400
#define REG_CTRL_TXBIL 0x1000
#define REG_FRAME 0x04
#define REG_FRAME_DATABITS__MASK 0x000f
#define REG_FRAME_DATABITS(n) ((n) - 3)
#define REG_CMD 0x0c
#define REG_CMD_RXEN 0x0001
#define REG_CMD_RXDIS 0x0002
#define REG_CMD_TXEN 0x0004
#define REG_CMD_TXDIS 0x0008
#define REG_CMD_MASTEREN 0x0010
#define REG_STATUS 0x10
#define REG_STATUS_TXENS 0x0002
#define REG_STATUS_TXC 0x0020
#define REG_STATUS_TXBL 0x0040
#define REG_STATUS_RXDATAV 0x0080
#define REG_CLKDIV 0x14
#define REG_RXDATAX 0x18
#define REG_RXDATAX_RXDATA__MASK 0x01ff
#define REG_RXDATAX_PERR 0x4000
#define REG_RXDATAX_FERR 0x8000
#define REG_TXDATA 0x34
#define REG_IF 0x40
#define REG_IF_TXBL 0x0002
#define REG_IF_RXDATAV 0x0004
#define REG_IFS 0x44
#define REG_IFC 0x48
#define REG_IEN 0x4c
#define REG_ROUTE 0x54
#define REG_ROUTE_RXPEN 0x0001
#define REG_ROUTE_TXPEN 0x0002
#define REG_ROUTE_CLKPEN 0x0008
#define REG_ROUTE_LOCATION__MASK 0x0700
#define REG_ROUTE_LOCATION(n) MASK_VAL(REG_ROUTE_LOCATION__MASK, (n))
struct efm32_spi_ddata {
struct spi_bitbang bitbang;
spinlock_t lock;
struct clk *clk;
void __iomem *base;
unsigned int rxirq, txirq;
struct efm32_spi_pdata pdata;
/* irq data */
struct completion done;
const u8 *tx_buf;
u8 *rx_buf;
unsigned tx_len, rx_len;
};
#define ddata_to_dev(ddata) (&(ddata->bitbang.master->dev))
#define efm32_spi_vdbg(ddata, format, arg...) \
dev_vdbg(ddata_to_dev(ddata), format, ##arg)
static void efm32_spi_write32(struct efm32_spi_ddata *ddata,
u32 value, unsigned offset)
{
writel_relaxed(value, ddata->base + offset);
}
static u32 efm32_spi_read32(struct efm32_spi_ddata *ddata, unsigned offset)
{
return readl_relaxed(ddata->base + offset);
}
static int efm32_spi_setup_transfer(struct spi_device *spi,
struct spi_transfer *t)
{
struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
unsigned bpw = t->bits_per_word ?: spi->bits_per_word;
unsigned speed = t->speed_hz ?: spi->max_speed_hz;
unsigned long clkfreq = clk_get_rate(ddata->clk);
u32 clkdiv;
efm32_spi_write32(ddata, REG_CTRL_SYNC | REG_CTRL_MSBF |
(spi->mode & SPI_CPHA ? REG_CTRL_CLKPHA : 0) |
(spi->mode & SPI_CPOL ? REG_CTRL_CLKPOL : 0), REG_CTRL);
efm32_spi_write32(ddata,
REG_FRAME_DATABITS(bpw), REG_FRAME);
if (2 * speed >= clkfreq)
clkdiv = 0;
else
clkdiv = 64 * (DIV_ROUND_UP(2 * clkfreq, speed) - 4);
if (clkdiv > (1U << 21))
return -EINVAL;
efm32_spi_write32(ddata, clkdiv, REG_CLKDIV);
efm32_spi_write32(ddata, REG_CMD_MASTEREN, REG_CMD);
efm32_spi_write32(ddata, REG_CMD_RXEN | REG_CMD_TXEN, REG_CMD);
return 0;
}
static void efm32_spi_tx_u8(struct efm32_spi_ddata *ddata)
{
u8 val = 0;
if (ddata->tx_buf) {
val = *ddata->tx_buf;
ddata->tx_buf++;
}
ddata->tx_len--;
efm32_spi_write32(ddata, val, REG_TXDATA);
efm32_spi_vdbg(ddata, "%s: tx 0x%x\n", __func__, val);
}
static void efm32_spi_rx_u8(struct efm32_spi_ddata *ddata)
{
u32 rxdata = efm32_spi_read32(ddata, REG_RXDATAX);
efm32_spi_vdbg(ddata, "%s: rx 0x%x\n", __func__, rxdata);
if (ddata->rx_buf) {
*ddata->rx_buf = rxdata;
ddata->rx_buf++;
}
ddata->rx_len--;
}
static void efm32_spi_filltx(struct efm32_spi_ddata *ddata)
{
while (ddata->tx_len &&
ddata->tx_len + 2 > ddata->rx_len &&
efm32_spi_read32(ddata, REG_STATUS) & REG_STATUS_TXBL) {
efm32_spi_tx_u8(ddata);
}
}
static int efm32_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
{
struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master);
int ret = -EBUSY;
spin_lock_irq(&ddata->lock);
if (ddata->tx_buf || ddata->rx_buf)
goto out_unlock;
ddata->tx_buf = t->tx_buf;
ddata->rx_buf = t->rx_buf;
ddata->tx_len = ddata->rx_len =
t->len * DIV_ROUND_UP(t->bits_per_word, 8);
efm32_spi_filltx(ddata);
reinit_completion(&ddata->done);
efm32_spi_write32(ddata, REG_IF_TXBL | REG_IF_RXDATAV, REG_IEN);
spin_unlock_irq(&ddata->lock);
wait_for_completion(&ddata->done);
spin_lock_irq(&ddata->lock);
ret = t->len - max(ddata->tx_len, ddata->rx_len);
efm32_spi_write32(ddata, 0, REG_IEN);
ddata->tx_buf = ddata->rx_buf = NULL;
out_unlock:
spin_unlock_irq(&ddata->lock);
return ret;
}
static irqreturn_t efm32_spi_rxirq(int irq, void *data)
{
struct efm32_spi_ddata *ddata = data;
irqreturn_t ret = IRQ_NONE;
spin_lock(&ddata->lock);
while (ddata->rx_len > 0 &&
efm32_spi_read32(ddata, REG_STATUS) &
REG_STATUS_RXDATAV) {
efm32_spi_rx_u8(ddata);
ret = IRQ_HANDLED;
}
if (!ddata->rx_len) {
u32 ien = efm32_spi_read32(ddata, REG_IEN);
ien &= ~REG_IF_RXDATAV;
efm32_spi_write32(ddata, ien, REG_IEN);
complete(&ddata->done);
}
spin_unlock(&ddata->lock);
return ret;
}
static irqreturn_t efm32_spi_txirq(int irq, void *data)
{
struct efm32_spi_ddata *ddata = data;
efm32_spi_vdbg(ddata,
"%s: txlen = %u, rxlen = %u, if=0x%08x, stat=0x%08x\n",
__func__, ddata->tx_len, ddata->rx_len,
efm32_spi_read32(ddata, REG_IF),
efm32_spi_read32(ddata, REG_STATUS));
spin_lock(&ddata->lock);
efm32_spi_filltx(ddata);
efm32_spi_vdbg(ddata, "%s: txlen = %u, rxlen = %u\n",
__func__, ddata->tx_len, ddata->rx_len);
if (!ddata->tx_len) {
u32 ien = efm32_spi_read32(ddata, REG_IEN);
ien &= ~REG_IF_TXBL;
efm32_spi_write32(ddata, ien, REG_IEN);
efm32_spi_vdbg(ddata, "disable TXBL\n");
}
spin_unlock(&ddata->lock);
return IRQ_HANDLED;
}
static u32 efm32_spi_get_configured_location(struct efm32_spi_ddata *ddata)
{
u32 reg = efm32_spi_read32(ddata, REG_ROUTE);
return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK);
}
static void efm32_spi_probe_dt(struct platform_device *pdev,
struct spi_master *master, struct efm32_spi_ddata *ddata)
{
struct device_node *np = pdev->dev.of_node;
u32 location;
int ret;
ret = of_property_read_u32(np, "energymicro,location", &location);
if (ret)
/* fall back to wrongly namespaced property */
ret = of_property_read_u32(np, "efm32,location", &location);
if (ret)
/* fall back to old and (wrongly) generic property "location" */
ret = of_property_read_u32(np, "location", &location);
if (!ret) {
dev_dbg(&pdev->dev, "using location %u\n", location);
} else {
/* default to location configured in hardware */
location = efm32_spi_get_configured_location(ddata);
dev_info(&pdev->dev, "fall back to location %u\n", location);
}
ddata->pdata.location = location;
}
static int efm32_spi_probe(struct platform_device *pdev)
{
struct efm32_spi_ddata *ddata;
struct resource *res;
int ret;
struct spi_master *master;
struct device_node *np = pdev->dev.of_node;
if (!np)
return -EINVAL;
master = spi_alloc_master(&pdev->dev, sizeof(*ddata));
if (!master) {
dev_dbg(&pdev->dev,
"failed to allocate spi master controller\n");
return -ENOMEM;
}
platform_set_drvdata(pdev, master);
master->dev.of_node = pdev->dev.of_node;
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
master->use_gpio_descriptors = true;
ddata = spi_master_get_devdata(master);
ddata->bitbang.master = master;
ddata->bitbang.setup_transfer = efm32_spi_setup_transfer;
ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs;
spin_lock_init(&ddata->lock);
init_completion(&ddata->done);
ddata->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(ddata->clk)) {
ret = PTR_ERR(ddata->clk);
dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
goto err;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
ret = -ENODEV;
dev_err(&pdev->dev, "failed to determine base address\n");
goto err;
}
if (resource_size(res) < 0x60) {
ret = -EINVAL;
dev_err(&pdev->dev, "memory resource too small\n");
goto err;
}
ddata->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(ddata->base)) {
ret = PTR_ERR(ddata->base);
goto err;
}
ret = platform_get_irq(pdev, 0);
if (ret <= 0)
goto err;
ddata->rxirq = ret;
ret = platform_get_irq(pdev, 1);
if (ret <= 0)
ret = ddata->rxirq + 1;
ddata->txirq = ret;
ret = clk_prepare_enable(ddata->clk);
if (ret < 0) {
dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
goto err;
}
efm32_spi_probe_dt(pdev, master, ddata);
efm32_spi_write32(ddata, 0, REG_IEN);
efm32_spi_write32(ddata, REG_ROUTE_TXPEN | REG_ROUTE_RXPEN |
REG_ROUTE_CLKPEN |
REG_ROUTE_LOCATION(ddata->pdata.location), REG_ROUTE);
ret = request_irq(ddata->rxirq, efm32_spi_rxirq,
0, DRIVER_NAME " rx", ddata);
if (ret) {
dev_err(&pdev->dev, "failed to register rxirq (%d)\n", ret);
goto err_disable_clk;
}
ret = request_irq(ddata->txirq, efm32_spi_txirq,
0, DRIVER_NAME " tx", ddata);
if (ret) {
dev_err(&pdev->dev, "failed to register txirq (%d)\n", ret);
goto err_free_rx_irq;
}
ret = spi_bitbang_start(&ddata->bitbang);
if (ret) {
dev_err(&pdev->dev, "spi_bitbang_start failed (%d)\n", ret);
free_irq(ddata->txirq, ddata);
err_free_rx_irq:
free_irq(ddata->rxirq, ddata);
err_disable_clk:
clk_disable_unprepare(ddata->clk);
err:
spi_master_put(master);
}
return ret;
}
static int efm32_spi_remove(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
struct efm32_spi_ddata *ddata = spi_master_get_devdata(master);
spi_bitbang_stop(&ddata->bitbang);
efm32_spi_write32(ddata, 0, REG_IEN);
free_irq(ddata->txirq, ddata);
free_irq(ddata->rxirq, ddata);
clk_disable_unprepare(ddata->clk);
spi_master_put(master);
return 0;
}
static const struct of_device_id efm32_spi_dt_ids[] = {
{
.compatible = "energymicro,efm32-spi",
}, {
/* doesn't follow the "vendor,device" scheme, don't use */
.compatible = "efm32,spi",
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, efm32_spi_dt_ids);
static struct platform_driver efm32_spi_driver = {
.probe = efm32_spi_probe,
.remove = efm32_spi_remove,
.driver = {
.name = DRIVER_NAME,
.of_match_table = efm32_spi_dt_ids,
},
};
module_platform_driver(efm32_spi_driver);
MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
MODULE_DESCRIPTION("EFM32 SPI driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
drivers/spi/spi-hisi-sfc-v3xx.c
View file @ eec262d1
......@@ -19,6 +19,8 @@
#define HISI_SFC_V3XX_VERSION (0x1f8)
#define HISI_SFC_V3XX_GLB_CFG (0x100)
#define HISI_SFC_V3XX_GLB_CFG_CS0_ADDR_MODE BIT(2)
#define HISI_SFC_V3XX_RAW_INT_STAT (0x120)
#define HISI_SFC_V3XX_INT_STAT (0x124)
#define HISI_SFC_V3XX_INT_MASK (0x128)
......@@ -75,6 +77,7 @@ struct hisi_sfc_v3xx_host {
void __iomem *regbase;
int max_cmd_dword;
struct completion *completion;
u8 address_mode;
int irq;
};
......@@ -168,10 +171,18 @@ static int hisi_sfc_v3xx_adjust_op_size(struct spi_mem *mem,
static bool hisi_sfc_v3xx_supports_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
struct spi_device *spi = mem->spi;
struct hisi_sfc_v3xx_host *host;
host = spi_controller_get_devdata(spi->master);
if (op->data.buswidth > 4 || op->dummy.buswidth > 4 ||
op->addr.buswidth > 4 || op->cmd.buswidth > 4)
return false;
if (op->addr.nbytes != host->address_mode && op->addr.nbytes)
return false;
return spi_mem_default_supports_op(mem, op);
}
......@@ -416,7 +427,7 @@ static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct hisi_sfc_v3xx_host *host;
struct spi_controller *ctlr;
u32 version;
u32 version, glb_config;
int ret;
ctlr = spi_alloc_master(&pdev->dev, sizeof(*host));
......@@ -463,16 +474,24 @@ static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
ctlr->num_chipselect = 1;
ctlr->mem_ops = &hisi_sfc_v3xx_mem_ops;
/*
* The address mode of the controller is either 3 or 4,
* which is indicated by the address mode bit in
* the global config register. The register is read only
* for the OS driver.
*/
glb_config = readl(host->regbase + HISI_SFC_V3XX_GLB_CFG);
if (glb_config & HISI_SFC_V3XX_GLB_CFG_CS0_ADDR_MODE)
host->address_mode = 4;
else
host->address_mode = 3;
version = readl(host->regbase + HISI_SFC_V3XX_VERSION);
switch (version) {
case 0x351:
if (version >= 0x351)
host->max_cmd_dword = 64;
break;
default:
else
host->max_cmd_dword = 16;
break;
}
ret = devm_spi_register_controller(dev, ctlr);
if (ret)
......
drivers/spi/spi-imx.c
View file @ eec262d1
......@@ -1685,7 +1685,7 @@ static int spi_imx_probe(struct platform_device *pdev)
master->dev.of_node = pdev->dev.of_node;
ret = spi_bitbang_start(&spi_imx->bitbang);
if (ret) {
dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
dev_err_probe(&pdev->dev, ret, "bitbang start failed\n");
goto out_bitbang_start;
}
......
drivers/spi/spi-mem.c
View file @ eec262d1
......@@ -137,8 +137,8 @@ static int spi_check_buswidth_req(struct spi_mem *mem, u8 buswidth, bool tx)
return -ENOTSUPP;
}
bool spi_mem_default_supports_op(struct spi_mem *mem,
const struct spi_mem_op *op)
static bool spi_mem_check_buswidth(struct spi_mem *mem,
const struct spi_mem_op *op)
{
if (spi_check_buswidth_req(mem, op->cmd.buswidth, true))
return false;
......@@ -156,13 +156,29 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
op->data.dir == SPI_MEM_DATA_OUT))
return false;
return true;
}
bool spi_mem_dtr_supports_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
if (op->cmd.nbytes != 2)
return false;
return spi_mem_check_buswidth(mem, op);
}
EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op);
bool spi_mem_default_supports_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
return false;
if (op->cmd.nbytes != 1)
return false;
return true;
return spi_mem_check_buswidth(mem, op);
}
EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
......@@ -354,6 +370,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1;
xfers[xferpos].len = op->dummy.nbytes;
xfers[xferpos].tx_nbits = op->dummy.buswidth;
xfers[xferpos].dummy_data = 1;
spi_message_add_tail(&xfers[xferpos], &msg);
xferpos++;
totalxferlen += op->dummy.nbytes;
......
drivers/spi/spi-mpc52xx.c
View file @ eec262d1
......@@ -248,7 +248,9 @@ static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
ms->len--;
if (ms->len == 0) {
ms->timestamp = get_tbl();
ms->timestamp += ms->transfer->delay_usecs * tb_ticks_per_usec;
if (ms->transfer->delay.unit == SPI_DELAY_UNIT_USECS)
ms->timestamp += ms->transfer->delay.value *
tb_ticks_per_usec;
ms->state = mpc52xx_spi_fsmstate_wait;
return FSM_CONTINUE;
}
......
drivers/spi/spi-mt65xx.c
View file @ eec262d1
......@@ -287,7 +287,7 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
static void mtk_spi_prepare_transfer(struct spi_master *master,
struct spi_transfer *xfer)
{
u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
u32 spi_clk_hz, div, sck_time, reg_val;
struct mtk_spi *mdata = spi_master_get_devdata(master);
spi_clk_hz = clk_get_rate(mdata->spi_clk);
......@@ -297,32 +297,25 @@ static void mtk_spi_prepare_transfer(struct spi_master *master,
div = 1;
sck_time = (div + 1) / 2;
cs_time = sck_time * 2;
if (mdata->dev_comp->enhance_timing) {
reg_val = (((sck_time - 1) & 0xffff)
reg_val = readl(mdata->base + SPI_CFG2_REG);
reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET);
reg_val |= (((sck_time - 1) & 0xffff)
<< SPI_CFG2_SCK_HIGH_OFFSET);
reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET);
reg_val |= (((sck_time - 1) & 0xffff)
<< SPI_CFG2_SCK_LOW_OFFSET);
writel(reg_val, mdata->base + SPI_CFG2_REG);
reg_val = (((cs_time - 1) & 0xffff)
<< SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
reg_val |= (((cs_time - 1) & 0xffff)
<< SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
writel(reg_val, mdata->base + SPI_CFG0_REG);
} else {
reg_val = (((sck_time - 1) & 0xff)
reg_val = readl(mdata->base + SPI_CFG0_REG);
reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET);
reg_val |= (((sck_time - 1) & 0xff)
<< SPI_CFG0_SCK_HIGH_OFFSET);
reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET);
reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
writel(reg_val, mdata->base + SPI_CFG0_REG);
}
reg_val = readl(mdata->base + SPI_CFG1_REG);
reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
writel(reg_val, mdata->base + SPI_CFG1_REG);
}
static void mtk_spi_setup_packet(struct spi_master *master)
......@@ -513,6 +506,52 @@ static bool mtk_spi_can_dma(struct spi_master *master,
(unsigned long)xfer->rx_buf % 4 == 0);
}
static int mtk_spi_set_hw_cs_timing(struct spi_device *spi,
struct spi_delay *setup,
struct spi_delay *hold,
struct spi_delay *inactive)
{
struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
u16 setup_dly, hold_dly, inactive_dly;
u32 reg_val;
if ((setup && setup->unit != SPI_DELAY_UNIT_SCK) ||
(hold && hold->unit != SPI_DELAY_UNIT_SCK) ||
(inactive && inactive->unit != SPI_DELAY_UNIT_SCK)) {
dev_err(&spi->dev,
"Invalid delay unit, should be SPI_DELAY_UNIT_SCK\n");
return -EINVAL;
}
setup_dly = setup ? setup->value : 1;
hold_dly = hold ? hold->value : 1;
inactive_dly = inactive ? inactive->value : 1;
reg_val = readl(mdata->base + SPI_CFG0_REG);
if (mdata->dev_comp->enhance_timing) {
reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
reg_val |= (((hold_dly - 1) & 0xffff)
<< SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
reg_val |= (((setup_dly - 1) & 0xffff)
<< SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
} else {
reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
reg_val |= (((hold_dly - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
reg_val |= (((setup_dly - 1) & 0xff)
<< SPI_CFG0_CS_SETUP_OFFSET);
}
writel(reg_val, mdata->base + SPI_CFG0_REG);
reg_val = readl(mdata->base + SPI_CFG1_REG);
reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
reg_val |= (((inactive_dly - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
writel(reg_val, mdata->base + SPI_CFG1_REG);
return 0;
}
static int mtk_spi_setup(struct spi_device *spi)
{
struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
......@@ -644,6 +683,7 @@ static int mtk_spi_probe(struct platform_device *pdev)
master->transfer_one = mtk_spi_transfer_one;
master->can_dma = mtk_spi_can_dma;
master->setup = mtk_spi_setup;
master->set_cs_timing = mtk_spi_set_hw_cs_timing;
of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
if (!of_id) {
......
drivers/spi/spi-orion.c
View file @ eec262d1
......@@ -96,10 +96,16 @@ struct orion_spi {
struct clk *clk;
struct clk *axi_clk;
const struct orion_spi_dev *devdata;
struct device *dev;
struct orion_child_options child[ORION_NUM_CHIPSELECTS];
};
#ifdef CONFIG_PM
static int orion_spi_runtime_suspend(struct device *dev);
static int orion_spi_runtime_resume(struct device *dev);
#endif
static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
{
return orion_spi->base + reg;
......@@ -369,8 +375,15 @@ orion_spi_write_read_8bit(struct spi_device *spi,
{
void __iomem *tx_reg, *rx_reg, *int_reg;
struct orion_spi *orion_spi;
bool cs_single_byte;
cs_single_byte = spi->mode & SPI_CS_WORD;
orion_spi = spi_master_get_devdata(spi->master);
if (cs_single_byte)
orion_spi_set_cs(spi, 0);
tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
......@@ -384,6 +397,11 @@ orion_spi_write_read_8bit(struct spi_device *spi,
writel(0, tx_reg);
if (orion_spi_wait_till_ready(orion_spi) < 0) {
if (cs_single_byte) {
orion_spi_set_cs(spi, 1);
/* Satisfy some SLIC devices requirements */
udelay(4);
}
dev_err(&spi->dev, "TXS timed out\n");
return -1;
}
......@@ -391,6 +409,12 @@ orion_spi_write_read_8bit(struct spi_device *spi,
if (rx_buf && *rx_buf)
*(*rx_buf)++ = readl(rx_reg);
if (cs_single_byte) {
orion_spi_set_cs(spi, 1);
/* Satisfy some SLIC devices requirements */
udelay(4);
}
return 1;
}
......@@ -401,6 +425,11 @@ orion_spi_write_read_16bit(struct spi_device *spi,
void __iomem *tx_reg, *rx_reg, *int_reg;
struct orion_spi *orion_spi;
if (spi->mode & SPI_CS_WORD) {
dev_err(&spi->dev, "SPI_CS_WORD is only supported for 8 bit words\n");
return -1;
}
orion_spi = spi_master_get_devdata(spi->master);
tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
......@@ -440,12 +469,13 @@ orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
orion_spi = spi_master_get_devdata(spi->master);
/*
* Use SPI direct write mode if base address is available. Otherwise
* fall back to PIO mode for this transfer.
* Use SPI direct write mode if base address is available
* and SPI_CS_WORD flag is not set.
* Otherwise fall back to PIO mode for this transfer.
*/
vaddr = orion_spi->child[cs].direct_access.vaddr;
if (vaddr && xfer->tx_buf && word_len == 8) {
if (vaddr && xfer->tx_buf && word_len == 8 && (spi->mode & SPI_CS_WORD) == 0) {
unsigned int cnt = count / 4;
unsigned int rem = count % 4;
......@@ -507,7 +537,21 @@ static int orion_spi_transfer_one(struct spi_master *master,
static int orion_spi_setup(struct spi_device *spi)
{
return orion_spi_setup_transfer(spi, NULL);
int ret;
#ifdef CONFIG_PM
struct orion_spi *orion_spi = spi_master_get_devdata(spi->master);
struct device *dev = orion_spi->dev;
orion_spi_runtime_resume(dev);
#endif
ret = orion_spi_setup_transfer(spi, NULL);
#ifdef CONFIG_PM
orion_spi_runtime_suspend(dev);
#endif
return ret;
}
static int orion_spi_reset(struct orion_spi *orion_spi)
......@@ -616,7 +660,7 @@ static int orion_spi_probe(struct platform_device *pdev)
}
/* we support all 4 SPI modes and LSB first option */
master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_CS_WORD;
master->set_cs = orion_spi_set_cs;
master->transfer_one = orion_spi_transfer_one;
master->num_chipselect = ORION_NUM_CHIPSELECTS;
......@@ -630,6 +674,7 @@ static int orion_spi_probe(struct platform_device *pdev)
spi = spi_master_get_devdata(master);
spi->master = master;
spi->dev = &pdev->dev;
of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
......
drivers/spi/spi-pxa2xx.c
View file @ eec262d1
......@@ -1492,6 +1492,10 @@ static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
{ PCI_VDEVICE(INTEL, 0x43ab), LPSS_CNL_SSP },
{ PCI_VDEVICE(INTEL, 0x43fb), LPSS_CNL_SSP },
{ PCI_VDEVICE(INTEL, 0x43fd), LPSS_CNL_SSP },
/* ADL-P */
{ PCI_VDEVICE(INTEL, 0x51aa), LPSS_CNL_SSP },
{ PCI_VDEVICE(INTEL, 0x51ab), LPSS_CNL_SSP },
{ PCI_VDEVICE(INTEL, 0x51fb), LPSS_CNL_SSP },
/* APL */
{ PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
{ PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
......
drivers/spi/spi-qcom-qspi.c
View file @ eec262d1
......@@ -511,8 +511,7 @@ static int qcom_qspi_probe(struct platform_device *pdev)
ret = platform_get_irq(pdev, 0);
if (ret < 0)
return ret;
ret = devm_request_irq(dev, ret, qcom_qspi_irq,
IRQF_TRIGGER_HIGH, dev_name(dev), ctrl);
ret = devm_request_irq(dev, ret, qcom_qspi_irq, 0, dev_name(dev), ctrl);
if (ret) {
dev_err(dev, "Failed to request irq %d\n", ret);
return ret;
......
drivers/spi/spi-realtek-rtl.c 0 → 100644
View file @ eec262d1
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mod_devicetable.h>
#include <linux/spi/spi.h>
struct rtspi {
void __iomem *base;
};
/* SPI Flash Configuration Register */
#define RTL_SPI_SFCR 0x00
#define RTL_SPI_SFCR_RBO BIT(28)
#define RTL_SPI_SFCR_WBO BIT(27)
/* SPI Flash Control and Status Register */
#define RTL_SPI_SFCSR 0x08
#define RTL_SPI_SFCSR_CSB0 BIT(31)
#define RTL_SPI_SFCSR_CSB1 BIT(30)
#define RTL_SPI_SFCSR_RDY BIT(27)
#define RTL_SPI_SFCSR_CS BIT(24)
#define RTL_SPI_SFCSR_LEN_MASK ~(0x03 << 28)
#define RTL_SPI_SFCSR_LEN1 (0x00 << 28)
#define RTL_SPI_SFCSR_LEN4 (0x03 << 28)
/* SPI Flash Data Register */
#define RTL_SPI_SFDR 0x0c
#define REG(x) (rtspi->base + x)
static void rt_set_cs(struct spi_device *spi, bool active)
{
struct rtspi *rtspi = spi_controller_get_devdata(spi->controller);
u32 value;
/* CS0 bit is active low */
value = readl(REG(RTL_SPI_SFCSR));
if (active)
value |= RTL_SPI_SFCSR_CSB0;
else
value &= ~RTL_SPI_SFCSR_CSB0;
writel(value, REG(RTL_SPI_SFCSR));
}
static void set_size(struct rtspi *rtspi, int size)
{
u32 value;
value = readl(REG(RTL_SPI_SFCSR));
value &= RTL_SPI_SFCSR_LEN_MASK;
if (size == 4)
value |= RTL_SPI_SFCSR_LEN4;
else if (size == 1)
value |= RTL_SPI_SFCSR_LEN1;
writel(value, REG(RTL_SPI_SFCSR));
}
static inline void wait_ready(struct rtspi *rtspi)
{
while (!(readl(REG(RTL_SPI_SFCSR)) & RTL_SPI_SFCSR_RDY))
cpu_relax();
}
static void send4(struct rtspi *rtspi, const u32 *buf)
{
wait_ready(rtspi);
set_size(rtspi, 4);
writel(*buf, REG(RTL_SPI_SFDR));
}
static void send1(struct rtspi *rtspi, const u8 *buf)
{
wait_ready(rtspi);
set_size(rtspi, 1);
writel(buf[0] << 24, REG(RTL_SPI_SFDR));
}
static void rcv4(struct rtspi *rtspi, u32 *buf)
{
wait_ready(rtspi);
set_size(rtspi, 4);
*buf = readl(REG(RTL_SPI_SFDR));
}
static void rcv1(struct rtspi *rtspi, u8 *buf)
{
wait_ready(rtspi);
set_size(rtspi, 1);
*buf = readl(REG(RTL_SPI_SFDR)) >> 24;
}
static int transfer_one(struct spi_controller *ctrl, struct spi_device *spi,
struct spi_transfer *xfer)
{
struct rtspi *rtspi = spi_controller_get_devdata(ctrl);
void *rx_buf;
const void *tx_buf;
int cnt;
tx_buf = xfer->tx_buf;
rx_buf = xfer->rx_buf;
cnt = xfer->len;
if (tx_buf) {
while (cnt >= 4) {
send4(rtspi, tx_buf);
tx_buf += 4;
cnt -= 4;
}
while (cnt) {
send1(rtspi, tx_buf);
tx_buf++;
cnt--;
}
} else if (rx_buf) {
while (cnt >= 4) {
rcv4(rtspi, rx_buf);
rx_buf += 4;
cnt -= 4;
}
while (cnt) {
rcv1(rtspi, rx_buf);
rx_buf++;
cnt--;
}
}
spi_finalize_current_transfer(ctrl);
return 0;
}
static void init_hw(struct rtspi *rtspi)
{
u32 value;
/* Turn on big-endian byte ordering */
value = readl(REG(RTL_SPI_SFCR));
value |= RTL_SPI_SFCR_RBO | RTL_SPI_SFCR_WBO;
writel(value, REG(RTL_SPI_SFCR));
value = readl(REG(RTL_SPI_SFCSR));
/* Permanently disable CS1, since it's never used */
value |= RTL_SPI_SFCSR_CSB1;
/* Select CS0 for use */
value &= RTL_SPI_SFCSR_CS;
writel(value, REG(RTL_SPI_SFCSR));
}
static int realtek_rtl_spi_probe(struct platform_device *pdev)
{
struct spi_controller *ctrl;
struct rtspi *rtspi;
int err;
ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*rtspi));
if (!ctrl) {
dev_err(&pdev->dev, "Error allocating SPI controller\n");
return -ENOMEM;
}
platform_set_drvdata(pdev, ctrl);
rtspi = spi_controller_get_devdata(ctrl);
rtspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(rtspi->base)) {
dev_err(&pdev->dev, "Could not map SPI register address");
return -ENOMEM;
}
init_hw(rtspi);
ctrl->dev.of_node = pdev->dev.of_node;
ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
ctrl->set_cs = rt_set_cs;
ctrl->transfer_one = transfer_one;
err = devm_spi_register_controller(&pdev->dev, ctrl);
if (err) {
dev_err(&pdev->dev, "Could not register SPI controller\n");
return -ENODEV;
}
return 0;
}
static const struct of_device_id realtek_rtl_spi_of_ids[] = {
{ .compatible = "realtek,rtl8380-spi" },
{ .compatible = "realtek,rtl8382-spi" },
{ .compatible = "realtek,rtl8391-spi" },
{ .compatible = "realtek,rtl8392-spi" },
{ .compatible = "realtek,rtl8393-spi" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, realtek_rtl_spi_of_ids);
static struct platform_driver realtek_rtl_spi_driver = {
.probe = realtek_rtl_spi_probe,
.driver = {
.name = "realtek-rtl-spi",
.of_match_table = realtek_rtl_spi_of_ids,
},
};
module_platform_driver(realtek_rtl_spi_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
MODULE_DESCRIPTION("Realtek RTL SPI driver");
drivers/spi/spi-rockchip.c
View file @ eec262d1
......@@ -566,7 +566,7 @@ static int rockchip_spi_slave_abort(struct spi_controller *ctlr)
struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
rs->slave_abort = true;
complete(&ctlr->xfer_completion);
spi_finalize_current_transfer(ctlr);
return 0;
}
......
drivers/spi/spi-rpc-if.c
View file @ eec262d1
......@@ -176,15 +176,14 @@ static int rpcif_spi_remove(struct platform_device *pdev)
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int rpcif_spi_suspend(struct device *dev)
static int __maybe_unused rpcif_spi_suspend(struct device *dev)
{
struct spi_controller *ctlr = dev_get_drvdata(dev);
return spi_controller_suspend(ctlr);
}
static int rpcif_spi_resume(struct device *dev)
static int __maybe_unused rpcif_spi_resume(struct device *dev)
{
struct spi_controller *ctlr = dev_get_drvdata(dev);
......@@ -192,17 +191,15 @@ static int rpcif_spi_resume(struct device *dev)
}
static SIMPLE_DEV_PM_OPS(rpcif_spi_pm_ops, rpcif_spi_suspend, rpcif_spi_resume);
#define DEV_PM_OPS (&rpcif_spi_pm_ops)
#else
#define DEV_PM_OPS NULL
#endif
static struct platform_driver rpcif_spi_driver = {
.probe = rpcif_spi_probe,
.remove = rpcif_spi_remove,
.driver = {
.name = "rpc-if-spi",
.pm = DEV_PM_OPS,
#ifdef CONFIG_PM_SLEEP
.pm = &rpcif_spi_pm_ops,
#endif
},
};
module_platform_driver(rpcif_spi_driver);
......
drivers/spi/spi-sh-msiof.c
View file @ eec262d1
......@@ -259,11 +259,13 @@ static const u32 sh_msiof_spi_div_array[] = {
};
static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
unsigned long parent_rate, u32 spi_hz)
struct spi_transfer *t)
{
unsigned long parent_rate = clk_get_rate(p->clk);
unsigned int div_pow = p->min_div_pow;
u32 spi_hz = t->speed_hz;
unsigned long div;
u32 brps, scr;
unsigned int div_pow = p->min_div_pow;
if (!spi_hz || !parent_rate) {
WARN(1, "Invalid clock rate parameters %lu and %u\n",
......@@ -292,6 +294,8 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
brps = 32;
}
t->effective_speed_hz = parent_rate / (brps << div_pow);
scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps);
sh_msiof_write(p, SITSCR, scr);
if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
......@@ -923,7 +927,7 @@ static int sh_msiof_transfer_one(struct spi_controller *ctlr,
/* setup clocks (clock already enabled in chipselect()) */
if (!spi_controller_is_slave(p->ctlr))
sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
sh_msiof_spi_set_clk_regs(p, t);
while (ctlr->dma_tx && len > 15) {
/*
......@@ -1258,6 +1262,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
const struct sh_msiof_chipdata *chipdata;
struct sh_msiof_spi_info *info;
struct sh_msiof_spi_priv *p;
unsigned long clksrc;
int i;
int ret;
......@@ -1333,6 +1338,9 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
/* init controller code */
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
clksrc = clk_get_rate(p->clk);
ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, 1024);
ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, 1 << p->min_div_pow);
ctlr->flags = chipdata->ctlr_flags;
ctlr->bus_num = pdev->id;
ctlr->num_chipselect = p->info->num_chipselect;
......
drivers/spi/spi-sirf.c deleted 100644 → 0
View file @ 110bc220
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SPI bus driver for CSR SiRFprimaII
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/of_gpio.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/dmaengine.h>
#include <linux/dma-direction.h>
#include <linux/dma-mapping.h>
#include <linux/reset.h>
#define DRIVER_NAME "sirfsoc_spi"
/* SPI CTRL register defines */
#define SIRFSOC_SPI_SLV_MODE BIT(16)
#define SIRFSOC_SPI_CMD_MODE BIT(17)
#define SIRFSOC_SPI_CS_IO_OUT BIT(18)
#define SIRFSOC_SPI_CS_IO_MODE BIT(19)
#define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20)
#define SIRFSOC_SPI_CS_IDLE_STAT BIT(21)
#define SIRFSOC_SPI_TRAN_MSB BIT(22)
#define SIRFSOC_SPI_DRV_POS_EDGE BIT(23)
#define SIRFSOC_SPI_CS_HOLD_TIME BIT(24)
#define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25)
#define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26)
#define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26)
#define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26)
#define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26)
#define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28)
#define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30)
#define SIRFSOC_SPI_MUL_DAT_MODE BIT(31)
/* Interrupt Enable */
#define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0)
#define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1)
#define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2)
#define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3)
#define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4)
#define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5)
#define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6)
#define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
#define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8)
#define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9)
#define SIRFSOC_SPI_FRM_END_INT_EN BIT(10)
/* Interrupt status */
#define SIRFSOC_SPI_RX_DONE BIT(0)
#define SIRFSOC_SPI_TX_DONE BIT(1)
#define SIRFSOC_SPI_RX_OFLOW BIT(2)
#define SIRFSOC_SPI_TX_UFLOW BIT(3)
#define SIRFSOC_SPI_RX_IO_DMA BIT(4)
#define SIRFSOC_SPI_RX_FIFO_FULL BIT(6)
#define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7)
#define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8)
#define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9)
#define SIRFSOC_SPI_FRM_END BIT(10)
/* TX RX enable */
#define SIRFSOC_SPI_RX_EN BIT(0)
#define SIRFSOC_SPI_TX_EN BIT(1)
#define SIRFSOC_SPI_CMD_TX_EN BIT(2)
#define SIRFSOC_SPI_IO_MODE_SEL BIT(0)
#define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2)
/* FIFO OPs */
#define SIRFSOC_SPI_FIFO_RESET BIT(0)
#define SIRFSOC_SPI_FIFO_START BIT(1)
/* FIFO CTRL */
#define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0)
#define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0)
#define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0)
/* USP related */
#define SIRFSOC_USP_SYNC_MODE BIT(0)
#define SIRFSOC_USP_SLV_MODE BIT(1)
#define SIRFSOC_USP_LSB BIT(4)
#define SIRFSOC_USP_EN BIT(5)
#define SIRFSOC_USP_RXD_FALLING_EDGE BIT(6)
#define SIRFSOC_USP_TXD_FALLING_EDGE BIT(7)
#define SIRFSOC_USP_CS_HIGH_VALID BIT(9)
#define SIRFSOC_USP_SCLK_IDLE_STAT BIT(11)
#define SIRFSOC_USP_TFS_IO_MODE BIT(14)
#define SIRFSOC_USP_TFS_IO_INPUT BIT(19)
#define SIRFSOC_USP_RXD_DELAY_LEN_MASK 0xFF
#define SIRFSOC_USP_TXD_DELAY_LEN_MASK 0xFF
#define SIRFSOC_USP_RXD_DELAY_OFFSET 0
#define SIRFSOC_USP_TXD_DELAY_OFFSET 8
#define SIRFSOC_USP_RXD_DELAY_LEN 1
#define SIRFSOC_USP_TXD_DELAY_LEN 1
#define SIRFSOC_USP_CLK_DIVISOR_OFFSET 21
#define SIRFSOC_USP_CLK_DIVISOR_MASK 0x3FF
#define SIRFSOC_USP_CLK_10_11_MASK 0x3
#define SIRFSOC_USP_CLK_10_11_OFFSET 30
#define SIRFSOC_USP_CLK_12_15_MASK 0xF
#define SIRFSOC_USP_CLK_12_15_OFFSET 24
#define SIRFSOC_USP_TX_DATA_OFFSET 0
#define SIRFSOC_USP_TX_SYNC_OFFSET 8
#define SIRFSOC_USP_TX_FRAME_OFFSET 16
#define SIRFSOC_USP_TX_SHIFTER_OFFSET 24
#define SIRFSOC_USP_TX_DATA_MASK 0xFF
#define SIRFSOC_USP_TX_SYNC_MASK 0xFF
#define SIRFSOC_USP_TX_FRAME_MASK 0xFF
#define SIRFSOC_USP_TX_SHIFTER_MASK 0x1F
#define SIRFSOC_USP_RX_DATA_OFFSET 0
#define SIRFSOC_USP_RX_FRAME_OFFSET 8
#define SIRFSOC_USP_RX_SHIFTER_OFFSET 16
#define SIRFSOC_USP_RX_DATA_MASK 0xFF
#define SIRFSOC_USP_RX_FRAME_MASK 0xFF
#define SIRFSOC_USP_RX_SHIFTER_MASK 0x1F
#define SIRFSOC_USP_CS_HIGH_VALUE BIT(1)
#define SIRFSOC_SPI_FIFO_SC_OFFSET 0
#define SIRFSOC_SPI_FIFO_LC_OFFSET 10
#define SIRFSOC_SPI_FIFO_HC_OFFSET 20
#define SIRFSOC_SPI_FIFO_FULL_MASK(s) (1 << ((s)->fifo_full_offset))
#define SIRFSOC_SPI_FIFO_EMPTY_MASK(s) (1 << ((s)->fifo_full_offset + 1))
#define SIRFSOC_SPI_FIFO_THD_MASK(s) ((s)->fifo_size - 1)
#define SIRFSOC_SPI_FIFO_THD_OFFSET 2
#define SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(s, val) \
((val) & (s)->fifo_level_chk_mask)
enum sirf_spi_type {
SIRF_REAL_SPI,
SIRF_USP_SPI_P2,
SIRF_USP_SPI_A7,
};
/*
* only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
* due to the limitation of dma controller
*/
#define ALIGNED(x) (!((u32)x & 0x3))
#define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
#define SIRFSOC_MAX_CMD_BYTES 4
#define SIRFSOC_SPI_DEFAULT_FRQ 1000000
struct sirf_spi_register {
/*SPI and USP-SPI common*/
u32 tx_rx_en;
u32 int_en;
u32 int_st;
u32 tx_dma_io_ctrl;
u32 tx_dma_io_len;
u32 txfifo_ctrl;
u32 txfifo_level_chk;
u32 txfifo_op;
u32 txfifo_st;
u32 txfifo_data;
u32 rx_dma_io_ctrl;
u32 rx_dma_io_len;
u32 rxfifo_ctrl;
u32 rxfifo_level_chk;
u32 rxfifo_op;
u32 rxfifo_st;
u32 rxfifo_data;
/*SPI self*/
u32 spi_ctrl;
u32 spi_cmd;
u32 spi_dummy_delay_ctrl;
/*USP-SPI self*/
u32 usp_mode1;
u32 usp_mode2;
u32 usp_tx_frame_ctrl;
u32 usp_rx_frame_ctrl;
u32 usp_pin_io_data;
u32 usp_risc_dsp_mode;
u32 usp_async_param_reg;
u32 usp_irda_x_mode_div;
u32 usp_sm_cfg;
u32 usp_int_en_clr;
};
static const struct sirf_spi_register real_spi_register = {
.tx_rx_en = 0x8,
.int_en = 0xc,
.int_st = 0x10,
.tx_dma_io_ctrl = 0x100,
.tx_dma_io_len = 0x104,
.txfifo_ctrl = 0x108,
.txfifo_level_chk = 0x10c,
.txfifo_op = 0x110,
.txfifo_st = 0x114,
.txfifo_data = 0x118,
.rx_dma_io_ctrl = 0x120,
.rx_dma_io_len = 0x124,
.rxfifo_ctrl = 0x128,
.rxfifo_level_chk = 0x12c,
.rxfifo_op = 0x130,
.rxfifo_st = 0x134,
.rxfifo_data = 0x138,
.spi_ctrl = 0x0,
.spi_cmd = 0x4,
.spi_dummy_delay_ctrl = 0x144,
};
static const struct sirf_spi_register usp_spi_register = {
.tx_rx_en = 0x10,
.int_en = 0x14,
.int_st = 0x18,
.tx_dma_io_ctrl = 0x100,
.tx_dma_io_len = 0x104,
.txfifo_ctrl = 0x108,
.txfifo_level_chk = 0x10c,
.txfifo_op = 0x110,
.txfifo_st = 0x114,
.txfifo_data = 0x118,
.rx_dma_io_ctrl = 0x120,
.rx_dma_io_len = 0x124,
.rxfifo_ctrl = 0x128,
.rxfifo_level_chk = 0x12c,
.rxfifo_op = 0x130,
.rxfifo_st = 0x134,
.rxfifo_data = 0x138,
.usp_mode1 = 0x0,
.usp_mode2 = 0x4,
.usp_tx_frame_ctrl = 0x8,
.usp_rx_frame_ctrl = 0xc,
.usp_pin_io_data = 0x1c,
.usp_risc_dsp_mode = 0x20,
.usp_async_param_reg = 0x24,
.usp_irda_x_mode_div = 0x28,
.usp_sm_cfg = 0x2c,
.usp_int_en_clr = 0x140,
};
struct sirfsoc_spi {
struct spi_bitbang bitbang;
struct completion rx_done;
struct completion tx_done;
void __iomem *base;
u32 ctrl_freq; /* SPI controller clock speed */
struct clk *clk;
/* rx & tx bufs from the spi_transfer */
const void *tx;
void *rx;
/* place received word into rx buffer */
void (*rx_word) (struct sirfsoc_spi *);
/* get word from tx buffer for sending */
void (*tx_word) (struct sirfsoc_spi *);
/* number of words left to be tranmitted/received */
unsigned int left_tx_word;
unsigned int left_rx_word;
/* rx & tx DMA channels */
struct dma_chan *rx_chan;
struct dma_chan *tx_chan;
dma_addr_t src_start;
dma_addr_t dst_start;
int word_width; /* in bytes */
/*
* if tx size is not more than 4 and rx size is NULL, use
* command model
*/
bool tx_by_cmd;
bool hw_cs;
enum sirf_spi_type type;
const struct sirf_spi_register *regs;
unsigned int fifo_size;
/* fifo empty offset is (fifo full offset + 1)*/
unsigned int fifo_full_offset;
/* fifo_level_chk_mask is (fifo_size/4 - 1) */
unsigned int fifo_level_chk_mask;
unsigned int dat_max_frm_len;
};
struct sirf_spi_comp_data {
const struct sirf_spi_register *regs;
enum sirf_spi_type type;
unsigned int dat_max_frm_len;
unsigned int fifo_size;
void (*hwinit)(struct sirfsoc_spi *sspi);
};
static void sirfsoc_usp_hwinit(struct sirfsoc_spi *sspi)
{
/* reset USP and let USP can operate */
writel(readl(sspi->base + sspi->regs->usp_mode1) &
~SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1);
writel(readl(sspi->base + sspi->regs->usp_mode1) |
SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1);
}
static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
{
u32 data;
u8 *rx = sspi->rx;
data = readl(sspi->base + sspi->regs->rxfifo_data);
if (rx) {
*rx++ = (u8) data;
sspi->rx = rx;
}
sspi->left_rx_word--;
}
static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
{
u32 data = 0;
const u8 *tx = sspi->tx;
if (tx) {
data = *tx++;
sspi->tx = tx;
}
writel(data, sspi->base + sspi->regs->txfifo_data);
sspi->left_tx_word--;
}
static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
{
u32 data;
u16 *rx = sspi->rx;
data = readl(sspi->base + sspi->regs->rxfifo_data);
if (rx) {
*rx++ = (u16) data;
sspi->rx = rx;
}
sspi->left_rx_word--;
}
static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
{
u32 data = 0;
const u16 *tx = sspi->tx;
if (tx) {
data = *tx++;
sspi->tx = tx;
}
writel(data, sspi->base + sspi->regs->txfifo_data);
sspi->left_tx_word--;
}
static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
{
u32 data;
u32 *rx = sspi->rx;
data = readl(sspi->base + sspi->regs->rxfifo_data);
if (rx) {
*rx++ = (u32) data;
sspi->rx = rx;
}
sspi->left_rx_word--;
}
static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
{
u32 data = 0;
const u32 *tx = sspi->tx;
if (tx) {
data = *tx++;
sspi->tx = tx;
}
writel(data, sspi->base + sspi->regs->txfifo_data);
sspi->left_tx_word--;
}
static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
{
struct sirfsoc_spi *sspi = dev_id;
u32 spi_stat;
spi_stat = readl(sspi->base + sspi->regs->int_st);
if (sspi->tx_by_cmd && sspi->type == SIRF_REAL_SPI
&& (spi_stat & SIRFSOC_SPI_FRM_END)) {
complete(&sspi->tx_done);
writel(0x0, sspi->base + sspi->regs->int_en);
writel(readl(sspi->base + sspi->regs->int_st),
sspi->base + sspi->regs->int_st);
return IRQ_HANDLED;
}
/* Error Conditions */
if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
spi_stat & SIRFSOC_SPI_TX_UFLOW) {
complete(&sspi->tx_done);
complete(&sspi->rx_done);
switch (sspi->type) {
case SIRF_REAL_SPI:
case SIRF_USP_SPI_P2:
writel(0x0, sspi->base + sspi->regs->int_en);
break;
case SIRF_USP_SPI_A7:
writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
break;
}
writel(readl(sspi->base + sspi->regs->int_st),
sspi->base + sspi->regs->int_st);
return IRQ_HANDLED;
}
if (spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY)
complete(&sspi->tx_done);
while (!(readl(sspi->base + sspi->regs->int_st) &
SIRFSOC_SPI_RX_IO_DMA))
cpu_relax();
complete(&sspi->rx_done);
switch (sspi->type) {
case SIRF_REAL_SPI:
case SIRF_USP_SPI_P2:
writel(0x0, sspi->base + sspi->regs->int_en);
break;
case SIRF_USP_SPI_A7:
writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
break;
}
writel(readl(sspi->base + sspi->regs->int_st),
sspi->base + sspi->regs->int_st);
return IRQ_HANDLED;
}
static void spi_sirfsoc_dma_fini_callback(void *data)
{
struct completion *dma_complete = data;
complete(dma_complete);
}
static void spi_sirfsoc_cmd_transfer(struct spi_device *spi,
struct spi_transfer *t)
{
struct sirfsoc_spi *sspi;
int timeout = t->len * 10;
u32 cmd;
sspi = spi_master_get_devdata(spi->master);
writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op);
memcpy(&cmd, sspi->tx, t->len);
if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
cmd = cpu_to_be32(cmd) >>
((SIRFSOC_MAX_CMD_BYTES - t->len) * 8);
if (sspi->word_width == 2 && t->len == 4 &&
(!(spi->mode & SPI_LSB_FIRST)))
cmd = ((cmd & 0xffff) << 16) | (cmd >> 16);
writel(cmd, sspi->base + sspi->regs->spi_cmd);
writel(SIRFSOC_SPI_FRM_END_INT_EN,
sspi->base + sspi->regs->int_en);
writel(SIRFSOC_SPI_CMD_TX_EN,
sspi->base + sspi->regs->tx_rx_en);
if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
dev_err(&spi->dev, "cmd transfer timeout\n");
return;
}
sspi->left_rx_word -= t->len;
}
static void spi_sirfsoc_dma_transfer(struct spi_device *spi,
struct spi_transfer *t)
{
struct sirfsoc_spi *sspi;
struct dma_async_tx_descriptor *rx_desc, *tx_desc;
int timeout = t->len * 10;
sspi = spi_master_get_devdata(spi->master);
writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op);
writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
switch (sspi->type) {
case SIRF_REAL_SPI:
writel(SIRFSOC_SPI_FIFO_START,
sspi->base + sspi->regs->rxfifo_op);
writel(SIRFSOC_SPI_FIFO_START,
sspi->base + sspi->regs->txfifo_op);
writel(0, sspi->base + sspi->regs->int_en);
break;
case SIRF_USP_SPI_P2:
writel(0x0, sspi->base + sspi->regs->rxfifo_op);
writel(0x0, sspi->base + sspi->regs->txfifo_op);
writel(0, sspi->base + sspi->regs->int_en);
break;
case SIRF_USP_SPI_A7:
writel(0x0, sspi->base + sspi->regs->rxfifo_op);
writel(0x0, sspi->base + sspi->regs->txfifo_op);
writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
break;
}
writel(readl(sspi->base + sspi->regs->int_st),
sspi->base + sspi->regs->int_st);
if (sspi->left_tx_word < sspi->dat_max_frm_len) {
switch (sspi->type) {
case SIRF_REAL_SPI:
writel(readl(sspi->base + sspi->regs->spi_ctrl) |
SIRFSOC_SPI_ENA_AUTO_CLR |
SIRFSOC_SPI_MUL_DAT_MODE,
sspi->base + sspi->regs->spi_ctrl);
writel(sspi->left_tx_word - 1,
sspi->base + sspi->regs->tx_dma_io_len);
writel(sspi->left_tx_word - 1,
sspi->base + sspi->regs->rx_dma_io_len);
break;
case SIRF_USP_SPI_P2:
case SIRF_USP_SPI_A7:
/*USP simulate SPI, tx/rx_dma_io_len indicates bytes*/
writel(sspi->left_tx_word * sspi->word_width,
sspi->base + sspi->regs->tx_dma_io_len);
writel(sspi->left_tx_word * sspi->word_width,
sspi->base + sspi->regs->rx_dma_io_len);
break;
}
} else {
if (sspi->type == SIRF_REAL_SPI)
writel(readl(sspi->base + sspi->regs->spi_ctrl),
sspi->base + sspi->regs->spi_ctrl);
writel(0, sspi->base + sspi->regs->tx_dma_io_len);
writel(0, sspi->base + sspi->regs->rx_dma_io_len);
}
sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len,
(t->tx_buf != t->rx_buf) ?
DMA_FROM_DEVICE : DMA_BIDIRECTIONAL);
rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
sspi->dst_start, t->len, DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
rx_desc->callback = spi_sirfsoc_dma_fini_callback;
rx_desc->callback_param = &sspi->rx_done;
sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len,
(t->tx_buf != t->rx_buf) ?
DMA_TO_DEVICE : DMA_BIDIRECTIONAL);
tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
sspi->src_start, t->len, DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
tx_desc->callback = spi_sirfsoc_dma_fini_callback;
tx_desc->callback_param = &sspi->tx_done;
dmaengine_submit(tx_desc);
dmaengine_submit(rx_desc);
dma_async_issue_pending(sspi->tx_chan);
dma_async_issue_pending(sspi->rx_chan);
writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
sspi->base + sspi->regs->tx_rx_en);
if (sspi->type == SIRF_USP_SPI_P2 ||
sspi->type == SIRF_USP_SPI_A7) {
writel(SIRFSOC_SPI_FIFO_START,
sspi->base + sspi->regs->rxfifo_op);
writel(SIRFSOC_SPI_FIFO_START,
sspi->base + sspi->regs->txfifo_op);
}
if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
dev_err(&spi->dev, "transfer timeout\n");
dmaengine_terminate_all(sspi->rx_chan);
} else
sspi->left_rx_word = 0;
/*
* we only wait tx-done event if transferring by DMA. for PIO,
* we get rx data by writing tx data, so if rx is done, tx has
* done earlier
*/
if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
dev_err(&spi->dev, "transfer timeout\n");
if (sspi->type == SIRF_USP_SPI_P2 ||
sspi->type == SIRF_USP_SPI_A7)
writel(0, sspi->base + sspi->regs->tx_rx_en);
dmaengine_terminate_all(sspi->tx_chan);
}
dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
/* TX, RX FIFO stop */
writel(0, sspi->base + sspi->regs->rxfifo_op);
writel(0, sspi->base + sspi->regs->txfifo_op);
if (sspi->left_tx_word >= sspi->dat_max_frm_len)
writel(0, sspi->base + sspi->regs->tx_rx_en);
if (sspi->type == SIRF_USP_SPI_P2 ||
sspi->type == SIRF_USP_SPI_A7)
writel(0, sspi->base + sspi->regs->tx_rx_en);
}
static void spi_sirfsoc_pio_transfer(struct spi_device *spi,
struct spi_transfer *t)
{
struct sirfsoc_spi *sspi;
int timeout = t->len * 10;
unsigned int data_units;
sspi = spi_master_get_devdata(spi->master);
do {
writel(SIRFSOC_SPI_FIFO_RESET,
sspi->base + sspi->regs->rxfifo_op);
writel(SIRFSOC_SPI_FIFO_RESET,
sspi->base + sspi->regs->txfifo_op);
switch (sspi->type) {
case SIRF_USP_SPI_P2:
writel(0x0, sspi->base + sspi->regs->rxfifo_op);
writel(0x0, sspi->base + sspi->regs->txfifo_op);
writel(0, sspi->base + sspi->regs->int_en);
writel(readl(sspi->base + sspi->regs->int_st),
sspi->base + sspi->regs->int_st);
writel(min((sspi->left_tx_word * sspi->word_width),
sspi->fifo_size),
sspi->base + sspi->regs->tx_dma_io_len);
writel(min((sspi->left_rx_word * sspi->word_width),
sspi->fifo_size),
sspi->base + sspi->regs->rx_dma_io_len);
break;
case SIRF_USP_SPI_A7:
writel(0x0, sspi->base + sspi->regs->rxfifo_op);
writel(0x0, sspi->base + sspi->regs->txfifo_op);
writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr);
writel(readl(sspi->base + sspi->regs->int_st),
sspi->base + sspi->regs->int_st);
writel(min((sspi->left_tx_word * sspi->word_width),
sspi->fifo_size),
sspi->base + sspi->regs->tx_dma_io_len);
writel(min((sspi->left_rx_word * sspi->word_width),
sspi->fifo_size),
sspi->base + sspi->regs->rx_dma_io_len);
break;
case SIRF_REAL_SPI:
writel(SIRFSOC_SPI_FIFO_START,
sspi->base + sspi->regs->rxfifo_op);
writel(SIRFSOC_SPI_FIFO_START,
sspi->base + sspi->regs->txfifo_op);
writel(0, sspi->base + sspi->regs->int_en);
writel(readl(sspi->base + sspi->regs->int_st),
sspi->base + sspi->regs->int_st);
writel(readl(sspi->base + sspi->regs->spi_ctrl) |
SIRFSOC_SPI_MUL_DAT_MODE |
SIRFSOC_SPI_ENA_AUTO_CLR,
sspi->base + sspi->regs->spi_ctrl);
data_units = sspi->fifo_size / sspi->word_width;
writel(min(sspi->left_tx_word, data_units) - 1,
sspi->base + sspi->regs->tx_dma_io_len);
writel(min(sspi->left_rx_word, data_units) - 1,
sspi->base + sspi->regs->rx_dma_io_len);
break;
}
while (!((readl(sspi->base + sspi->regs->txfifo_st)
& SIRFSOC_SPI_FIFO_FULL_MASK(sspi))) &&
sspi->left_tx_word)
sspi->tx_word(sspi);
writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN |
SIRFSOC_SPI_TX_UFLOW_INT_EN |
SIRFSOC_SPI_RX_OFLOW_INT_EN |
SIRFSOC_SPI_RX_IO_DMA_INT_EN,
sspi->base + sspi->regs->int_en);
writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN,
sspi->base + sspi->regs->tx_rx_en);
if (sspi->type == SIRF_USP_SPI_P2 ||
sspi->type == SIRF_USP_SPI_A7) {
writel(SIRFSOC_SPI_FIFO_START,
sspi->base + sspi->regs->rxfifo_op);
writel(SIRFSOC_SPI_FIFO_START,
sspi->base + sspi->regs->txfifo_op);
}
if (!wait_for_completion_timeout(&sspi->tx_done, timeout) ||
!wait_for_completion_timeout(&sspi->rx_done, timeout)) {
dev_err(&spi->dev, "transfer timeout\n");
if (sspi->type == SIRF_USP_SPI_P2 ||
sspi->type == SIRF_USP_SPI_A7)
writel(0, sspi->base + sspi->regs->tx_rx_en);
break;
}
while (!((readl(sspi->base + sspi->regs->rxfifo_st)
& SIRFSOC_SPI_FIFO_EMPTY_MASK(sspi))) &&
sspi->left_rx_word)
sspi->rx_word(sspi);
if (sspi->type == SIRF_USP_SPI_P2 ||
sspi->type == SIRF_USP_SPI_A7)
writel(0, sspi->base + sspi->regs->tx_rx_en);
writel(0, sspi->base + sspi->regs->rxfifo_op);
writel(0, sspi->base + sspi->regs->txfifo_op);
} while (sspi->left_tx_word != 0 || sspi->left_rx_word != 0);
}
static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
{
struct sirfsoc_spi *sspi;
sspi = spi_master_get_devdata(spi->master);
sspi->tx = t->tx_buf;
sspi->rx = t->rx_buf;
sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
reinit_completion(&sspi->rx_done);
reinit_completion(&sspi->tx_done);
/*
* in the transfer, if transfer data using command register with rx_buf
* null, just fill command data into command register and wait for its
* completion.
*/
if (sspi->type == SIRF_REAL_SPI && sspi->tx_by_cmd)
spi_sirfsoc_cmd_transfer(spi, t);
else if (IS_DMA_VALID(t))
spi_sirfsoc_dma_transfer(spi, t);
else
spi_sirfsoc_pio_transfer(spi, t);
return t->len - sspi->left_rx_word * sspi->word_width;
}
static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
{
struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
if (sspi->hw_cs) {
u32 regval;
switch (sspi->type) {
case SIRF_REAL_SPI:
regval = readl(sspi->base + sspi->regs->spi_ctrl);
switch (value) {
case BITBANG_CS_ACTIVE:
if (spi->mode & SPI_CS_HIGH)
regval |= SIRFSOC_SPI_CS_IO_OUT;
else
regval &= ~SIRFSOC_SPI_CS_IO_OUT;
break;
case BITBANG_CS_INACTIVE:
if (spi->mode & SPI_CS_HIGH)
regval &= ~SIRFSOC_SPI_CS_IO_OUT;
else
regval |= SIRFSOC_SPI_CS_IO_OUT;
break;
}
writel(regval, sspi->base + sspi->regs->spi_ctrl);
break;
case SIRF_USP_SPI_P2:
case SIRF_USP_SPI_A7:
regval = readl(sspi->base +
sspi->regs->usp_pin_io_data);
switch (value) {
case BITBANG_CS_ACTIVE:
if (spi->mode & SPI_CS_HIGH)
regval |= SIRFSOC_USP_CS_HIGH_VALUE;
else
regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE);
break;
case BITBANG_CS_INACTIVE:
if (spi->mode & SPI_CS_HIGH)
regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE);
else
regval |= SIRFSOC_USP_CS_HIGH_VALUE;
break;
}
writel(regval,
sspi->base + sspi->regs->usp_pin_io_data);
break;
}
} else {
switch (value) {
case BITBANG_CS_ACTIVE:
gpio_direction_output(spi->cs_gpio,
spi->mode & SPI_CS_HIGH ? 1 : 0);
break;
case BITBANG_CS_INACTIVE:
gpio_direction_output(spi->cs_gpio,
spi->mode & SPI_CS_HIGH ? 0 : 1);
break;
}
}
}
static int spi_sirfsoc_config_mode(struct spi_device *spi)
{
struct sirfsoc_spi *sspi;
u32 regval, usp_mode1;
sspi = spi_master_get_devdata(spi->master);
regval = readl(sspi->base + sspi->regs->spi_ctrl);
usp_mode1 = readl(sspi->base + sspi->regs->usp_mode1);
if (!(spi->mode & SPI_CS_HIGH)) {
regval |= SIRFSOC_SPI_CS_IDLE_STAT;
usp_mode1 &= ~SIRFSOC_USP_CS_HIGH_VALID;
} else {
regval &= ~SIRFSOC_SPI_CS_IDLE_STAT;
usp_mode1 |= SIRFSOC_USP_CS_HIGH_VALID;
}
if (!(spi->mode & SPI_LSB_FIRST)) {
regval |= SIRFSOC_SPI_TRAN_MSB;
usp_mode1 &= ~SIRFSOC_USP_LSB;
} else {
regval &= ~SIRFSOC_SPI_TRAN_MSB;
usp_mode1 |= SIRFSOC_USP_LSB;
}
if (spi->mode & SPI_CPOL) {
regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
usp_mode1 |= SIRFSOC_USP_SCLK_IDLE_STAT;
} else {
regval &= ~SIRFSOC_SPI_CLK_IDLE_STAT;
usp_mode1 &= ~SIRFSOC_USP_SCLK_IDLE_STAT;
}
/*
* Data should be driven at least 1/2 cycle before the fetch edge
* to make sure that data gets stable at the fetch edge.
*/
if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
(!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA))) {
regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
usp_mode1 |= (SIRFSOC_USP_TXD_FALLING_EDGE |
SIRFSOC_USP_RXD_FALLING_EDGE);
} else {
regval |= SIRFSOC_SPI_DRV_POS_EDGE;
usp_mode1 &= ~(SIRFSOC_USP_RXD_FALLING_EDGE |
SIRFSOC_USP_TXD_FALLING_EDGE);
}
writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) <<
SIRFSOC_SPI_FIFO_SC_OFFSET) |
(SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size / 2) <<
SIRFSOC_SPI_FIFO_LC_OFFSET) |
(SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, 2) <<
SIRFSOC_SPI_FIFO_HC_OFFSET),
sspi->base + sspi->regs->txfifo_level_chk);
writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, 2) <<
SIRFSOC_SPI_FIFO_SC_OFFSET) |
(SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size / 2) <<
SIRFSOC_SPI_FIFO_LC_OFFSET) |
(SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) <<
SIRFSOC_SPI_FIFO_HC_OFFSET),
sspi->base + sspi->regs->rxfifo_level_chk);
/*
* it should never set to hardware cs mode because in hardware cs mode,
* cs signal can't controlled by driver.
*/
switch (sspi->type) {
case SIRF_REAL_SPI:
regval |= SIRFSOC_SPI_CS_IO_MODE;
writel(regval, sspi->base + sspi->regs->spi_ctrl);
break;
case SIRF_USP_SPI_P2:
case SIRF_USP_SPI_A7:
usp_mode1 |= SIRFSOC_USP_SYNC_MODE;
usp_mode1 |= SIRFSOC_USP_TFS_IO_MODE;
usp_mode1 &= ~SIRFSOC_USP_TFS_IO_INPUT;
writel(usp_mode1, sspi->base + sspi->regs->usp_mode1);
break;
}
return 0;
}
static int
spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
struct sirfsoc_spi *sspi;
u8 bits_per_word = 0;
int hz = 0;
u32 regval, txfifo_ctrl, rxfifo_ctrl, tx_frm_ctl, rx_frm_ctl, usp_mode2;
sspi = spi_master_get_devdata(spi->master);
bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
usp_mode2 = regval = (sspi->ctrl_freq / (2 * hz)) - 1;
if (regval > 0xFFFF || regval < 0) {
dev_err(&spi->dev, "Speed %d not supported\n", hz);
return -EINVAL;
}
switch (bits_per_word) {
case 8:
regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
sspi->rx_word = spi_sirfsoc_rx_word_u8;
sspi->tx_word = spi_sirfsoc_tx_word_u8;
break;
case 12:
case 16:
regval |= (bits_per_word == 12) ?
SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
sspi->rx_word = spi_sirfsoc_rx_word_u16;
sspi->tx_word = spi_sirfsoc_tx_word_u16;
break;
case 32:
regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
sspi->rx_word = spi_sirfsoc_rx_word_u32;
sspi->tx_word = spi_sirfsoc_tx_word_u32;
break;
default:
dev_err(&spi->dev, "bpw %d not supported\n", bits_per_word);
return -EINVAL;
}
sspi->word_width = DIV_ROUND_UP(bits_per_word, 8);
txfifo_ctrl = (((sspi->fifo_size / 2) &
SIRFSOC_SPI_FIFO_THD_MASK(sspi))
<< SIRFSOC_SPI_FIFO_THD_OFFSET) |
(sspi->word_width >> 1);
rxfifo_ctrl = (((sspi->fifo_size / 2) &
SIRFSOC_SPI_FIFO_THD_MASK(sspi))
<< SIRFSOC_SPI_FIFO_THD_OFFSET) |
(sspi->word_width >> 1);
writel(txfifo_ctrl, sspi->base + sspi->regs->txfifo_ctrl);
writel(rxfifo_ctrl, sspi->base + sspi->regs->rxfifo_ctrl);
if (sspi->type == SIRF_USP_SPI_P2 ||
sspi->type == SIRF_USP_SPI_A7) {
tx_frm_ctl = 0;
tx_frm_ctl |= ((bits_per_word - 1) & SIRFSOC_USP_TX_DATA_MASK)
<< SIRFSOC_USP_TX_DATA_OFFSET;
tx_frm_ctl |= ((bits_per_word + 1 + SIRFSOC_USP_TXD_DELAY_LEN
- 1) & SIRFSOC_USP_TX_SYNC_MASK) <<
SIRFSOC_USP_TX_SYNC_OFFSET;
tx_frm_ctl |= ((bits_per_word + 1 + SIRFSOC_USP_TXD_DELAY_LEN
+ 2 - 1) & SIRFSOC_USP_TX_FRAME_MASK) <<
SIRFSOC_USP_TX_FRAME_OFFSET;
tx_frm_ctl |= ((bits_per_word - 1) &
SIRFSOC_USP_TX_SHIFTER_MASK) <<
SIRFSOC_USP_TX_SHIFTER_OFFSET;
rx_frm_ctl = 0;
rx_frm_ctl |= ((bits_per_word - 1) & SIRFSOC_USP_RX_DATA_MASK)
<< SIRFSOC_USP_RX_DATA_OFFSET;
rx_frm_ctl |= ((bits_per_word + 1 + SIRFSOC_USP_RXD_DELAY_LEN
+ 2 - 1) & SIRFSOC_USP_RX_FRAME_MASK) <<
SIRFSOC_USP_RX_FRAME_OFFSET;
rx_frm_ctl |= ((bits_per_word - 1)
& SIRFSOC_USP_RX_SHIFTER_MASK) <<
SIRFSOC_USP_RX_SHIFTER_OFFSET;
writel(tx_frm_ctl | (((usp_mode2 >> 10) &
SIRFSOC_USP_CLK_10_11_MASK) <<
SIRFSOC_USP_CLK_10_11_OFFSET),
sspi->base + sspi->regs->usp_tx_frame_ctrl);
writel(rx_frm_ctl | (((usp_mode2 >> 12) &
SIRFSOC_USP_CLK_12_15_MASK) <<
SIRFSOC_USP_CLK_12_15_OFFSET),
sspi->base + sspi->regs->usp_rx_frame_ctrl);
writel(readl(sspi->base + sspi->regs->usp_mode2) |
((usp_mode2 & SIRFSOC_USP_CLK_DIVISOR_MASK) <<
SIRFSOC_USP_CLK_DIVISOR_OFFSET) |
(SIRFSOC_USP_RXD_DELAY_LEN <<
SIRFSOC_USP_RXD_DELAY_OFFSET) |
(SIRFSOC_USP_TXD_DELAY_LEN <<
SIRFSOC_USP_TXD_DELAY_OFFSET),
sspi->base + sspi->regs->usp_mode2);
}
if (sspi->type == SIRF_REAL_SPI)
writel(regval, sspi->base + sspi->regs->spi_ctrl);
spi_sirfsoc_config_mode(spi);
if (sspi->type == SIRF_REAL_SPI) {
if (t && t->tx_buf && !t->rx_buf &&
(t->len <= SIRFSOC_MAX_CMD_BYTES)) {
sspi->tx_by_cmd = true;
writel(readl(sspi->base + sspi->regs->spi_ctrl) |
(SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) |
SIRFSOC_SPI_CMD_MODE),
sspi->base + sspi->regs->spi_ctrl);
} else {
sspi->tx_by_cmd = false;
writel(readl(sspi->base + sspi->regs->spi_ctrl) &
~SIRFSOC_SPI_CMD_MODE,
sspi->base + sspi->regs->spi_ctrl);
}
}
if (IS_DMA_VALID(t)) {
/* Enable DMA mode for RX, TX */
writel(0, sspi->base + sspi->regs->tx_dma_io_ctrl);
writel(SIRFSOC_SPI_RX_DMA_FLUSH,
sspi->base + sspi->regs->rx_dma_io_ctrl);
} else {
/* Enable IO mode for RX, TX */
writel(SIRFSOC_SPI_IO_MODE_SEL,
sspi->base + sspi->regs->tx_dma_io_ctrl);
writel(SIRFSOC_SPI_IO_MODE_SEL,
sspi->base + sspi->regs->rx_dma_io_ctrl);
}
return 0;
}
static int spi_sirfsoc_setup(struct spi_device *spi)
{
struct sirfsoc_spi *sspi;
int ret = 0;
sspi = spi_master_get_devdata(spi->master);
if (spi->cs_gpio == -ENOENT)
sspi->hw_cs = true;
else {
sspi->hw_cs = false;
if (!spi_get_ctldata(spi)) {
void *cs = kmalloc(sizeof(int), GFP_KERNEL);
if (!cs) {
ret = -ENOMEM;
goto exit;
}
ret = gpio_is_valid(spi->cs_gpio);
if (!ret) {
dev_err(&spi->dev, "no valid gpio\n");
ret = -ENOENT;
goto exit;
}
ret = gpio_request(spi->cs_gpio, DRIVER_NAME);
if (ret) {
dev_err(&spi->dev, "failed to request gpio\n");
goto exit;
}
spi_set_ctldata(spi, cs);
}
}
spi_sirfsoc_config_mode(spi);
spi_sirfsoc_chipselect(spi, BITBANG_CS_INACTIVE);
exit:
return ret;
}
static void spi_sirfsoc_cleanup(struct spi_device *spi)
{
if (spi_get_ctldata(spi)) {
gpio_free(spi->cs_gpio);
kfree(spi_get_ctldata(spi));
}
}
static const struct sirf_spi_comp_data sirf_real_spi = {
.regs = &real_spi_register,
.type = SIRF_REAL_SPI,
.dat_max_frm_len = 64 * 1024,
.fifo_size = 256,
};
static const struct sirf_spi_comp_data sirf_usp_spi_p2 = {
.regs = &usp_spi_register,
.type = SIRF_USP_SPI_P2,
.dat_max_frm_len = 1024 * 1024,
.fifo_size = 128,
.hwinit = sirfsoc_usp_hwinit,
};
static const struct sirf_spi_comp_data sirf_usp_spi_a7 = {
.regs = &usp_spi_register,
.type = SIRF_USP_SPI_A7,
.dat_max_frm_len = 1024 * 1024,
.fifo_size = 512,
.hwinit = sirfsoc_usp_hwinit,
};
static const struct of_device_id spi_sirfsoc_of_match[] = {
{ .compatible = "sirf,prima2-spi", .data = &sirf_real_spi},
{ .compatible = "sirf,prima2-usp-spi", .data = &sirf_usp_spi_p2},
{ .compatible = "sirf,atlas7-usp-spi", .data = &sirf_usp_spi_a7},
{}
};
MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
static int spi_sirfsoc_probe(struct platform_device *pdev)
{
struct sirfsoc_spi *sspi;
struct spi_master *master;
const struct sirf_spi_comp_data *spi_comp_data;
int irq;
int ret;
const struct of_device_id *match;
ret = device_reset(&pdev->dev);
if (ret) {
dev_err(&pdev->dev, "SPI reset failed!\n");
return ret;
}
master = spi_alloc_master(&pdev->dev, sizeof(*sspi));
if (!master) {
dev_err(&pdev->dev, "Unable to allocate SPI master\n");
return -ENOMEM;
}
match = of_match_node(spi_sirfsoc_of_match, pdev->dev.of_node);
platform_set_drvdata(pdev, master);
sspi = spi_master_get_devdata(master);
sspi->fifo_full_offset = ilog2(sspi->fifo_size);
spi_comp_data = match->data;
sspi->regs = spi_comp_data->regs;
sspi->type = spi_comp_data->type;
sspi->fifo_level_chk_mask = (sspi->fifo_size / 4) - 1;
sspi->dat_max_frm_len = spi_comp_data->dat_max_frm_len;
sspi->fifo_size = spi_comp_data->fifo_size;
sspi->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(sspi->base)) {
ret = PTR_ERR(sspi->base);
goto free_master;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
ret = -ENXIO;
goto free_master;
}
ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
DRIVER_NAME, sspi);
if (ret)
goto free_master;
sspi->bitbang.master = master;
sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
sspi->bitbang.master->setup = spi_sirfsoc_setup;
sspi->bitbang.master->cleanup = spi_sirfsoc_cleanup;
master->bus_num = pdev->id;
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
master->max_speed_hz = SIRFSOC_SPI_DEFAULT_FRQ;
master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
/* request DMA channels */
sspi->rx_chan = dma_request_chan(&pdev->dev, "rx");
if (IS_ERR(sspi->rx_chan)) {
dev_err(&pdev->dev, "can not allocate rx dma channel\n");
ret = PTR_ERR(sspi->rx_chan);
goto free_master;
}
sspi->tx_chan = dma_request_chan(&pdev->dev, "tx");
if (IS_ERR(sspi->tx_chan)) {
dev_err(&pdev->dev, "can not allocate tx dma channel\n");
ret = PTR_ERR(sspi->tx_chan);
goto free_rx_dma;
}
sspi->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(sspi->clk)) {
ret = PTR_ERR(sspi->clk);
goto free_tx_dma;
}
clk_prepare_enable(sspi->clk);
if (spi_comp_data->hwinit)
spi_comp_data->hwinit(sspi);
sspi->ctrl_freq = clk_get_rate(sspi->clk);
init_completion(&sspi->rx_done);
init_completion(&sspi->tx_done);
ret = spi_bitbang_start(&sspi->bitbang);
if (ret)
goto free_clk;
dev_info(&pdev->dev, "registered, bus number = %d\n", master->bus_num);
return 0;
free_clk:
clk_disable_unprepare(sspi->clk);
clk_put(sspi->clk);
free_tx_dma:
dma_release_channel(sspi->tx_chan);
free_rx_dma:
dma_release_channel(sspi->rx_chan);
free_master:
spi_master_put(master);
return ret;
}
static int spi_sirfsoc_remove(struct platform_device *pdev)
{
struct spi_master *master;
struct sirfsoc_spi *sspi;
master = platform_get_drvdata(pdev);
sspi = spi_master_get_devdata(master);
spi_bitbang_stop(&sspi->bitbang);
clk_disable_unprepare(sspi->clk);
clk_put(sspi->clk);
dma_release_channel(sspi->rx_chan);
dma_release_channel(sspi->tx_chan);
spi_master_put(master);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int spi_sirfsoc_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
int ret;
ret = spi_master_suspend(master);
if (ret)
return ret;
clk_disable(sspi->clk);
return 0;
}
static int spi_sirfsoc_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
clk_enable(sspi->clk);
writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op);
writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op);
writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op);
writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->rxfifo_op);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend,
spi_sirfsoc_resume);
static struct platform_driver spi_sirfsoc_driver = {
.driver = {
.name = DRIVER_NAME,
.pm = &spi_sirfsoc_pm_ops,
.of_match_table = spi_sirfsoc_of_match,
},
.probe = spi_sirfsoc_probe,
.remove = spi_sirfsoc_remove,
};
module_platform_driver(spi_sirfsoc_driver);
MODULE_DESCRIPTION("SiRF SoC SPI master driver");
MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>");
MODULE_AUTHOR("Barry Song <Baohua.Song@csr.com>");
MODULE_AUTHOR("Qipan Li <Qipan.Li@csr.com>");
MODULE_LICENSE("GPL v2");
drivers/spi/spi-stm32.c
View file @ eec262d1
......@@ -5,6 +5,7 @@
// Copyright (C) 2017, STMicroelectronics - All Rights Reserved
// Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
#include <linux/bitfield.h>
#include <linux/debugfs.h>
#include <linux/clk.h>
#include <linux/delay.h>
......@@ -94,27 +95,22 @@
#define STM32H7_SPI_CR1_SSI BIT(12)
/* STM32H7_SPI_CR2 bit fields */
#define STM32H7_SPI_CR2_TSIZE_SHIFT 0
#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
#define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)
/* STM32H7_SPI_CFG1 bit fields */
#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
#define STM32H7_SPI_CFG1_MBR_SHIFT 28
#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
#define STM32H7_SPI_CFG1_MBR_SHIFT 28
#define STM32H7_SPI_CFG1_MBR_MIN 0
#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
/* STM32H7_SPI_CFG2 bit fields */
#define STM32H7_SPI_CFG2_MIDI_SHIFT 4
#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
#define STM32H7_SPI_CFG2_COMM_SHIFT 17
#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
#define STM32H7_SPI_CFG2_SP_SHIFT 19
#define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
#define STM32H7_SPI_CFG2_MASTER BIT(22)
#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
......@@ -140,7 +136,6 @@
#define STM32H7_SPI_SR_OVR BIT(6)
#define STM32H7_SPI_SR_MODF BIT(9)
#define STM32H7_SPI_SR_SUSP BIT(11)
#define STM32H7_SPI_SR_RXPLVL_SHIFT 13
#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
#define STM32H7_SPI_SR_RXWNE BIT(15)
......@@ -167,8 +162,6 @@
#define SPI_3WIRE_TX 3
#define SPI_3WIRE_RX 4
#define SPI_1HZ_NS 1000000000
/*
* use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
* without fifo buffers.
......@@ -268,7 +261,6 @@ struct stm32_spi_cfg {
* @base: virtual memory area
* @clk: hw kernel clock feeding the SPI clock generator
* @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
* @rst: SPI controller reset line
* @lock: prevent I/O concurrent access
* @irq: SPI controller interrupt line
* @fifo_size: size of the embedded fifo in bytes
......@@ -294,7 +286,6 @@ struct stm32_spi {
void __iomem *base;
struct clk *clk;
u32 clk_rate;
struct reset_control *rst;
spinlock_t lock; /* prevent I/O concurrent access */
int irq;
unsigned int fifo_size;
......@@ -417,9 +408,7 @@ static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
STM32H7_SPI_CFG1_DSIZE_SHIFT;
max_bpw += 1;
max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
spin_unlock_irqrestore(&spi->lock, flags);
......@@ -473,34 +462,14 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
*/
static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
{
u32 fthlv, half_fifo, packet;
u32 packet, bpw;
/* data packet should not exceed 1/2 of fifo space */
half_fifo = (spi->fifo_size / 2);
/* data_packet should not exceed transfer length */
if (half_fifo > xfer_len)
packet = xfer_len;
else
packet = half_fifo;
if (spi->cur_bpw <= 8)
fthlv = packet;
else if (spi->cur_bpw <= 16)
fthlv = packet / 2;
else
fthlv = packet / 4;
packet = clamp(xfer_len, 1U, spi->fifo_size / 2);
/* align packet size with data registers access */
if (spi->cur_bpw > 8)
fthlv += (fthlv % 2) ? 1 : 0;
else
fthlv += (fthlv % 4) ? (4 - (fthlv % 4)) : 0;
if (!fthlv)
fthlv = 1;
return fthlv;
bpw = DIV_ROUND_UP(spi->cur_bpw, 8);
return DIV_ROUND_UP(packet, bpw);
}
/**
......@@ -607,8 +576,7 @@ static void stm32f4_spi_read_rx(struct stm32_spi *spi)
static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
{
u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
STM32H7_SPI_SR_RXPLVL_SHIFT;
u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
while ((spi->rx_len > 0) &&
((sr & STM32H7_SPI_SR_RXP) ||
......@@ -635,8 +603,7 @@ static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
}
sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
STM32H7_SPI_SR_RXPLVL_SHIFT;
rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
}
dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
......@@ -928,8 +895,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
mask |= STM32H7_SPI_SR_RXP;
if (!(sr & mask)) {
dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
sr, ier);
dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
sr, ier);
spin_unlock_irqrestore(&spi->lock, flags);
return IRQ_NONE;
}
......@@ -956,15 +923,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
}
if (sr & STM32H7_SPI_SR_OVR) {
dev_warn(spi->dev, "Overrun: received value discarded\n");
if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
stm32h7_spi_read_rxfifo(spi, false);
/*
* If overrun is detected while using DMA, it means that
* something went wrong, so stop the current transfer
*/
if (spi->cur_usedma)
end = true;
dev_err(spi->dev, "Overrun: RX data lost\n");
end = true;
}
if (sr & STM32H7_SPI_SR_EOT) {
......@@ -1028,10 +988,24 @@ static int stm32_spi_prepare_msg(struct spi_master *master,
clrb |= spi->cfg->regs->lsb_first.mask;
dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
spi_dev->mode & SPI_CPOL,
spi_dev->mode & SPI_CPHA,
spi_dev->mode & SPI_LSB_FIRST,
spi_dev->mode & SPI_CS_HIGH);
!!(spi_dev->mode & SPI_CPOL),
!!(spi_dev->mode & SPI_CPHA),
!!(spi_dev->mode & SPI_LSB_FIRST),
!!(spi_dev->mode & SPI_CS_HIGH));
/* On STM32H7, messages should not exceed a maximum size setted
* afterward via the set_number_of_data function. In order to
* ensure that, split large messages into several messages
*/
if (spi->cfg->set_number_of_data) {
int ret;
ret = spi_split_transfers_maxsize(master, msg,
STM32H7_SPI_TSIZE_MAX,
GFP_KERNEL | GFP_DMA);
if (ret)
return ret;
}
spin_lock_irqsave(&spi->lock, flags);
......@@ -1405,15 +1379,13 @@ static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
bpw = spi->cur_bpw - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
STM32H7_SPI_CFG1_DSIZE;
cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
fthlv = spi->cur_fthlv - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
STM32H7_SPI_CFG1_FTHLV;
cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
writel_relaxed(
(readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
......@@ -1431,8 +1403,7 @@ static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
u32 clrb = 0, setb = 0;
clrb |= spi->cfg->regs->br.mask;
setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
spi->cfg->regs->br.mask;
setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
~clrb) | setb,
......@@ -1523,8 +1494,7 @@ static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
}
cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
STM32H7_SPI_CFG2_COMM;
cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_COMM, mode);
writel_relaxed(
(readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
......@@ -1546,15 +1516,16 @@ static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
if ((len > 1) && (spi->cur_midi > 0)) {
u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
(u32)STM32H7_SPI_CFG2_MIDI >>
STM32H7_SPI_CFG2_MIDI_SHIFT);
u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
u32 midi = min_t(u32,
DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
FIELD_GET(STM32H7_SPI_CFG2_MIDI,
STM32H7_SPI_CFG2_MIDI));
dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
sck_period_ns, midi, midi * sck_period_ns);
cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
STM32H7_SPI_CFG2_MIDI;
cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_MIDI, midi);
}
writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
......@@ -1569,14 +1540,8 @@ static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
*/
static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
{
u32 cr2_clrb = 0, cr2_setb = 0;
if (nb_words <= (STM32H7_SPI_CR2_TSIZE >>
STM32H7_SPI_CR2_TSIZE_SHIFT)) {
cr2_clrb |= STM32H7_SPI_CR2_TSIZE;
cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT;
writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) &
~cr2_clrb) | cr2_setb,
if (nb_words <= STM32H7_SPI_TSIZE_MAX) {
writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words),
spi->base + STM32H7_SPI_CR2);
} else {
return -EMSGSIZE;
......@@ -1677,6 +1642,10 @@ static int stm32_spi_transfer_one(struct spi_master *master,
struct stm32_spi *spi = spi_master_get_devdata(master);
int ret;
/* Don't do anything on 0 bytes transfers */
if (transfer->len == 0)
return 0;
spi->tx_buf = transfer->tx_buf;
spi->rx_buf = transfer->rx_buf;
spi->tx_len = spi->tx_buf ? transfer->len : 0;
......@@ -1831,6 +1800,7 @@ static int stm32_spi_probe(struct platform_device *pdev)
struct spi_master *master;
struct stm32_spi *spi;
struct resource *res;
struct reset_control *rst;
int ret;
master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
......@@ -1892,11 +1862,17 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_clk_disable;
}
spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (!IS_ERR(spi->rst)) {
reset_control_assert(spi->rst);
rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
if (rst) {
if (IS_ERR(rst)) {
ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
"failed to get reset\n");
goto err_clk_disable;
}
reset_control_assert(rst);
udelay(2);
reset_control_deassert(spi->rst);
reset_control_deassert(rst);
}
if (spi->cfg->has_fifo)
......@@ -1960,12 +1936,6 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_pm_disable;
}
if (!master->cs_gpiods) {
dev_err(&pdev->dev, "no CS gpios available\n");
ret = -EINVAL;
goto err_pm_disable;
}
dev_info(&pdev->dev, "driver initialized\n");
return 0;
......
drivers/spi/spi-tegra210-quad.c 0 → 100644
View file @ eec262d1
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (C) 2020 NVIDIA CORPORATION.
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/dmapool.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/kthread.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/reset.h>
#include <linux/spi/spi.h>
#define QSPI_COMMAND1 0x000
#define QSPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
#define QSPI_PACKED BIT(5)
#define QSPI_INTERFACE_WIDTH_MASK (0x03 << 7)
#define QSPI_INTERFACE_WIDTH(x) (((x) & 0x03) << 7)
#define QSPI_INTERFACE_WIDTH_SINGLE QSPI_INTERFACE_WIDTH(0)
#define QSPI_INTERFACE_WIDTH_DUAL QSPI_INTERFACE_WIDTH(1)
#define QSPI_INTERFACE_WIDTH_QUAD QSPI_INTERFACE_WIDTH(2)
#define QSPI_SDR_DDR_SEL BIT(9)
#define QSPI_TX_EN BIT(11)
#define QSPI_RX_EN BIT(12)
#define QSPI_CS_SW_VAL BIT(20)
#define QSPI_CS_SW_HW BIT(21)
#define QSPI_CONTROL_MODE_0 (0 << 28)
#define QSPI_CONTROL_MODE_3 (3 << 28)
#define QSPI_CONTROL_MODE_MASK (3 << 28)
#define QSPI_M_S BIT(30)
#define QSPI_PIO BIT(31)
#define QSPI_COMMAND2 0x004
#define QSPI_TX_TAP_DELAY(x) (((x) & 0x3f) << 10)
#define QSPI_RX_TAP_DELAY(x) (((x) & 0xff) << 0)
#define QSPI_CS_TIMING1 0x008
#define QSPI_SETUP_HOLD(setup, hold) (((setup) << 4) | (hold))
#define QSPI_CS_TIMING2 0x00c
#define CYCLES_BETWEEN_PACKETS_0(x) (((x) & 0x1f) << 0)
#define CS_ACTIVE_BETWEEN_PACKETS_0 BIT(5)
#define QSPI_TRANS_STATUS 0x010
#define QSPI_BLK_CNT(val) (((val) >> 0) & 0xffff)
#define QSPI_RDY BIT(30)
#define QSPI_FIFO_STATUS 0x014
#define QSPI_RX_FIFO_EMPTY BIT(0)
#define QSPI_RX_FIFO_FULL BIT(1)
#define QSPI_TX_FIFO_EMPTY BIT(2)
#define QSPI_TX_FIFO_FULL BIT(3)
#define QSPI_RX_FIFO_UNF BIT(4)
#define QSPI_RX_FIFO_OVF BIT(5)
#define QSPI_TX_FIFO_UNF BIT(6)
#define QSPI_TX_FIFO_OVF BIT(7)
#define QSPI_ERR BIT(8)
#define QSPI_TX_FIFO_FLUSH BIT(14)
#define QSPI_RX_FIFO_FLUSH BIT(15)
#define QSPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7f)
#define QSPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7f)
#define QSPI_FIFO_ERROR (QSPI_RX_FIFO_UNF | \
QSPI_RX_FIFO_OVF | \
QSPI_TX_FIFO_UNF | \
QSPI_TX_FIFO_OVF)
#define QSPI_FIFO_EMPTY (QSPI_RX_FIFO_EMPTY | \
QSPI_TX_FIFO_EMPTY)
#define QSPI_TX_DATA 0x018
#define QSPI_RX_DATA 0x01c
#define QSPI_DMA_CTL 0x020
#define QSPI_TX_TRIG(n) (((n) & 0x3) << 15)
#define QSPI_TX_TRIG_1 QSPI_TX_TRIG(0)
#define QSPI_TX_TRIG_4 QSPI_TX_TRIG(1)
#define QSPI_TX_TRIG_8 QSPI_TX_TRIG(2)
#define QSPI_TX_TRIG_16 QSPI_TX_TRIG(3)
#define QSPI_RX_TRIG(n) (((n) & 0x3) << 19)
#define QSPI_RX_TRIG_1 QSPI_RX_TRIG(0)
#define QSPI_RX_TRIG_4 QSPI_RX_TRIG(1)
#define QSPI_RX_TRIG_8 QSPI_RX_TRIG(2)
#define QSPI_RX_TRIG_16 QSPI_RX_TRIG(3)
#define QSPI_DMA_EN BIT(31)
#define QSPI_DMA_BLK 0x024
#define QSPI_DMA_BLK_SET(x) (((x) & 0xffff) << 0)
#define QSPI_TX_FIFO 0x108
#define QSPI_RX_FIFO 0x188
#define QSPI_FIFO_DEPTH 64
#define QSPI_INTR_MASK 0x18c
#define QSPI_INTR_RX_FIFO_UNF_MASK BIT(25)
#define QSPI_INTR_RX_FIFO_OVF_MASK BIT(26)
#define QSPI_INTR_TX_FIFO_UNF_MASK BIT(27)
#define QSPI_INTR_TX_FIFO_OVF_MASK BIT(28)
#define QSPI_INTR_RDY_MASK BIT(29)
#define QSPI_INTR_RX_TX_FIFO_ERR (QSPI_INTR_RX_FIFO_UNF_MASK | \
QSPI_INTR_RX_FIFO_OVF_MASK | \
QSPI_INTR_TX_FIFO_UNF_MASK | \
QSPI_INTR_TX_FIFO_OVF_MASK)
#define QSPI_MISC_REG 0x194
#define QSPI_NUM_DUMMY_CYCLE(x) (((x) & 0xff) << 0)
#define QSPI_DUMMY_CYCLES_MAX 0xff
#define DATA_DIR_TX BIT(0)
#define DATA_DIR_RX BIT(1)
#define QSPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
#define DEFAULT_QSPI_DMA_BUF_LEN (64 * 1024)
struct tegra_qspi_client_data {
int tx_clk_tap_delay;
int rx_clk_tap_delay;
};
struct tegra_qspi {
struct device *dev;
struct spi_master *master;
/* lock to protect data accessed by irq */
spinlock_t lock;
struct clk *clk;
struct reset_control *rst;
void __iomem *base;
phys_addr_t phys;
unsigned int irq;
u32 cur_speed;
unsigned int cur_pos;
unsigned int words_per_32bit;
unsigned int bytes_per_word;
unsigned int curr_dma_words;
unsigned int cur_direction;
unsigned int cur_rx_pos;
unsigned int cur_tx_pos;
unsigned int dma_buf_size;
unsigned int max_buf_size;
bool is_curr_dma_xfer;
struct completion rx_dma_complete;
struct completion tx_dma_complete;
u32 tx_status;
u32 rx_status;
u32 status_reg;
bool is_packed;
bool use_dma;
u32 command1_reg;
u32 dma_control_reg;
u32 def_command1_reg;
u32 def_command2_reg;
u32 spi_cs_timing1;
u32 spi_cs_timing2;
u8 dummy_cycles;
struct completion xfer_completion;
struct spi_transfer *curr_xfer;
struct dma_chan *rx_dma_chan;
u32 *rx_dma_buf;
dma_addr_t rx_dma_phys;
struct dma_async_tx_descriptor *rx_dma_desc;
struct dma_chan *tx_dma_chan;
u32 *tx_dma_buf;
dma_addr_t tx_dma_phys;
struct dma_async_tx_descriptor *tx_dma_desc;
};
static inline u32 tegra_qspi_readl(struct tegra_qspi *tqspi, unsigned long offset)
{
return readl(tqspi->base + offset);
}
static inline void tegra_qspi_writel(struct tegra_qspi *tqspi, u32 value, unsigned long offset)
{
writel(value, tqspi->base + offset);
/* read back register to make sure that register writes completed */
if (offset != QSPI_TX_FIFO)
readl(tqspi->base + QSPI_COMMAND1);
}
static void tegra_qspi_mask_clear_irq(struct tegra_qspi *tqspi)
{
u32 value;
/* write 1 to clear status register */
value = tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS);
tegra_qspi_writel(tqspi, value, QSPI_TRANS_STATUS);
value = tegra_qspi_readl(tqspi, QSPI_INTR_MASK);
if (!(value & QSPI_INTR_RDY_MASK)) {
value |= (QSPI_INTR_RDY_MASK | QSPI_INTR_RX_TX_FIFO_ERR);
tegra_qspi_writel(tqspi, value, QSPI_INTR_MASK);
}
/* clear fifo status error if any */
value = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
if (value & QSPI_ERR)
tegra_qspi_writel(tqspi, QSPI_ERR | QSPI_FIFO_ERROR, QSPI_FIFO_STATUS);
}
static unsigned int
tegra_qspi_calculate_curr_xfer_param(struct tegra_qspi *tqspi, struct spi_transfer *t)
{
unsigned int max_word, max_len, total_fifo_words;
unsigned int remain_len = t->len - tqspi->cur_pos;
unsigned int bits_per_word = t->bits_per_word;
tqspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
/*
* Tegra QSPI controller supports packed or unpacked mode transfers.
* Packed mode is used for data transfers using 8, 16, or 32 bits per
* word with a minimum transfer of 1 word and for all other transfers
* unpacked mode will be used.
*/
if ((bits_per_word == 8 || bits_per_word == 16 ||
bits_per_word == 32) && t->len > 3) {
tqspi->is_packed = true;
tqspi->words_per_32bit = 32 / bits_per_word;
} else {
tqspi->is_packed = false;
tqspi->words_per_32bit = 1;
}
if (tqspi->is_packed) {
max_len = min(remain_len, tqspi->max_buf_size);
tqspi->curr_dma_words = max_len / tqspi->bytes_per_word;
total_fifo_words = (max_len + 3) / 4;
} else {
max_word = (remain_len - 1) / tqspi->bytes_per_word + 1;
max_word = min(max_word, tqspi->max_buf_size / 4);
tqspi->curr_dma_words = max_word;
total_fifo_words = max_word;
}
return total_fifo_words;
}
static unsigned int
tegra_qspi_fill_tx_fifo_from_client_txbuf(struct tegra_qspi *tqspi, struct spi_transfer *t)
{
unsigned int written_words, fifo_words_left, count;
unsigned int len, tx_empty_count, max_n_32bit, i;
u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos;
u32 fifo_status;
fifo_status = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
tx_empty_count = QSPI_TX_FIFO_EMPTY_COUNT(fifo_status);
if (tqspi->is_packed) {
fifo_words_left = tx_empty_count * tqspi->words_per_32bit;
written_words = min(fifo_words_left, tqspi->curr_dma_words);
len = written_words * tqspi->bytes_per_word;
max_n_32bit = DIV_ROUND_UP(len, 4);
for (count = 0; count < max_n_32bit; count++) {
u32 x = 0;
for (i = 0; (i < 4) && len; i++, len--)
x |= (u32)(*tx_buf++) << (i * 8);
tegra_qspi_writel(tqspi, x, QSPI_TX_FIFO);
}
tqspi->cur_tx_pos += written_words * tqspi->bytes_per_word;
} else {
unsigned int write_bytes;
u8 bytes_per_word = tqspi->bytes_per_word;
max_n_32bit = min(tqspi->curr_dma_words, tx_empty_count);
written_words = max_n_32bit;
len = written_words * tqspi->bytes_per_word;
if (len > t->len - tqspi->cur_pos)
len = t->len - tqspi->cur_pos;
write_bytes = len;
for (count = 0; count < max_n_32bit; count++) {
u32 x = 0;
for (i = 0; len && (i < bytes_per_word); i++, len--)
x |= (u32)(*tx_buf++) << (i * 8);
tegra_qspi_writel(tqspi, x, QSPI_TX_FIFO);
}
tqspi->cur_tx_pos += write_bytes;
}
return written_words;
}
static unsigned int
tegra_qspi_read_rx_fifo_to_client_rxbuf(struct tegra_qspi *tqspi, struct spi_transfer *t)
{
u8 *rx_buf = (u8 *)t->rx_buf + tqspi->cur_rx_pos;
unsigned int len, rx_full_count, count, i;
unsigned int read_words = 0;
u32 fifo_status, x;
fifo_status = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
rx_full_count = QSPI_RX_FIFO_FULL_COUNT(fifo_status);
if (tqspi->is_packed) {
len = tqspi->curr_dma_words * tqspi->bytes_per_word;
for (count = 0; count < rx_full_count; count++) {
x = tegra_qspi_readl(tqspi, QSPI_RX_FIFO);
for (i = 0; len && (i < 4); i++, len--)
*rx_buf++ = (x >> i * 8) & 0xff;
}
read_words += tqspi->curr_dma_words;
tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word;
} else {
u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
u8 bytes_per_word = tqspi->bytes_per_word;
unsigned int read_bytes;
len = rx_full_count * bytes_per_word;
if (len > t->len - tqspi->cur_pos)
len = t->len - tqspi->cur_pos;
read_bytes = len;
for (count = 0; count < rx_full_count; count++) {
x = tegra_qspi_readl(tqspi, QSPI_RX_FIFO) & rx_mask;
for (i = 0; len && (i < bytes_per_word); i++, len--)
*rx_buf++ = (x >> (i * 8)) & 0xff;
}
read_words += rx_full_count;
tqspi->cur_rx_pos += read_bytes;
}
return read_words;
}
static void
tegra_qspi_copy_client_txbuf_to_qspi_txbuf(struct tegra_qspi *tqspi, struct spi_transfer *t)
{
dma_sync_single_for_cpu(tqspi->dev, tqspi->tx_dma_phys,
tqspi->dma_buf_size, DMA_TO_DEVICE);
/*
* In packed mode, each word in FIFO may contain multiple packets
* based on bits per word. So all bytes in each FIFO word are valid.
*
* In unpacked mode, each word in FIFO contains single packet and
* based on bits per word any remaining bits in FIFO word will be
* ignored by the hardware and are invalid bits.
*/
if (tqspi->is_packed) {
tqspi->cur_tx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word;
} else {
u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos;
unsigned int i, count, consume, write_bytes;
/*
* Fill tx_dma_buf to contain single packet in each word based
* on bits per word from SPI core tx_buf.
*/
consume = tqspi->curr_dma_words * tqspi->bytes_per_word;
if (consume > t->len - tqspi->cur_pos)
consume = t->len - tqspi->cur_pos;
write_bytes = consume;
for (count = 0; count < tqspi->curr_dma_words; count++) {
u32 x = 0;
for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--)
x |= (u32)(*tx_buf++) << (i * 8);
tqspi->tx_dma_buf[count] = x;
}
tqspi->cur_tx_pos += write_bytes;
}
dma_sync_single_for_device(tqspi->dev, tqspi->tx_dma_phys,
tqspi->dma_buf_size, DMA_TO_DEVICE);
}
static void
tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf(struct tegra_qspi *tqspi, struct spi_transfer *t)
{
dma_sync_single_for_cpu(tqspi->dev, tqspi->rx_dma_phys,
tqspi->dma_buf_size, DMA_FROM_DEVICE);
if (tqspi->is_packed) {
tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word;
} else {
unsigned char *rx_buf = t->rx_buf + tqspi->cur_rx_pos;
u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
unsigned int i, count, consume, read_bytes;
/*
* Each FIFO word contains single data packet.
* Skip invalid bits in each FIFO word based on bits per word
* and align bytes while filling in SPI core rx_buf.
*/
consume = tqspi->curr_dma_words * tqspi->bytes_per_word;
if (consume > t->len - tqspi->cur_pos)
consume = t->len - tqspi->cur_pos;
read_bytes = consume;
for (count = 0; count < tqspi->curr_dma_words; count++) {
u32 x = tqspi->rx_dma_buf[count] & rx_mask;
for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--)
*rx_buf++ = (x >> (i * 8)) & 0xff;
}
tqspi->cur_rx_pos += read_bytes;
}
dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys,
tqspi->dma_buf_size, DMA_FROM_DEVICE);
}
static void tegra_qspi_dma_complete(void *args)
{
struct completion *dma_complete = args;
complete(dma_complete);
}
static int tegra_qspi_start_tx_dma(struct tegra_qspi *tqspi, struct spi_transfer *t, int len)
{
dma_addr_t tx_dma_phys;
reinit_completion(&tqspi->tx_dma_complete);
if (tqspi->is_packed)
tx_dma_phys = t->tx_dma;
else
tx_dma_phys = tqspi->tx_dma_phys;
tqspi->tx_dma_desc = dmaengine_prep_slave_single(tqspi->tx_dma_chan, tx_dma_phys,
len, DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!tqspi->tx_dma_desc) {
dev_err(tqspi->dev, "Unable to get TX descriptor\n");
return -EIO;
}
tqspi->tx_dma_desc->callback = tegra_qspi_dma_complete;
tqspi->tx_dma_desc->callback_param = &tqspi->tx_dma_complete;
dmaengine_submit(tqspi->tx_dma_desc);
dma_async_issue_pending(tqspi->tx_dma_chan);
return 0;
}
static int tegra_qspi_start_rx_dma(struct tegra_qspi *tqspi, struct spi_transfer *t, int len)
{
dma_addr_t rx_dma_phys;
reinit_completion(&tqspi->rx_dma_complete);
if (tqspi->is_packed)
rx_dma_phys = t->rx_dma;
else
rx_dma_phys = tqspi->rx_dma_phys;
tqspi->rx_dma_desc = dmaengine_prep_slave_single(tqspi->rx_dma_chan, rx_dma_phys,
len, DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!tqspi->rx_dma_desc) {
dev_err(tqspi->dev, "Unable to get RX descriptor\n");
return -EIO;
}
tqspi->rx_dma_desc->callback = tegra_qspi_dma_complete;
tqspi->rx_dma_desc->callback_param = &tqspi->rx_dma_complete;
dmaengine_submit(tqspi->rx_dma_desc);
dma_async_issue_pending(tqspi->rx_dma_chan);
return 0;
}
static int tegra_qspi_flush_fifos(struct tegra_qspi *tqspi, bool atomic)
{
void __iomem *addr = tqspi->base + QSPI_FIFO_STATUS;
u32 val;
val = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
if ((val & QSPI_FIFO_EMPTY) == QSPI_FIFO_EMPTY)
return 0;
val |= QSPI_RX_FIFO_FLUSH | QSPI_TX_FIFO_FLUSH;
tegra_qspi_writel(tqspi, val, QSPI_FIFO_STATUS);
if (!atomic)
return readl_relaxed_poll_timeout(addr, val,
(val & QSPI_FIFO_EMPTY) == QSPI_FIFO_EMPTY,
1000, 1000000);
return readl_relaxed_poll_timeout_atomic(addr, val,
(val & QSPI_FIFO_EMPTY) == QSPI_FIFO_EMPTY,
1000, 1000000);
}
static void tegra_qspi_unmask_irq(struct tegra_qspi *tqspi)
{
u32 intr_mask;
intr_mask = tegra_qspi_readl(tqspi, QSPI_INTR_MASK);
intr_mask &= ~(QSPI_INTR_RDY_MASK | QSPI_INTR_RX_TX_FIFO_ERR);
tegra_qspi_writel(tqspi, intr_mask, QSPI_INTR_MASK);
}
static int tegra_qspi_dma_map_xfer(struct tegra_qspi *tqspi, struct spi_transfer *t)
{
u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos;
u8 *rx_buf = (u8 *)t->rx_buf + tqspi->cur_rx_pos;
unsigned int len;
len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4;
if (t->tx_buf) {
t->tx_dma = dma_map_single(tqspi->dev, (void *)tx_buf, len, DMA_TO_DEVICE);
if (dma_mapping_error(tqspi->dev, t->tx_dma))
return -ENOMEM;
}
if (t->rx_buf) {
t->rx_dma = dma_map_single(tqspi->dev, (void *)rx_buf, len, DMA_FROM_DEVICE);
if (dma_mapping_error(tqspi->dev, t->rx_dma)) {
dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE);
return -ENOMEM;
}
}
return 0;
}
static void tegra_qspi_dma_unmap_xfer(struct tegra_qspi *tqspi, struct spi_transfer *t)
{
unsigned int len;
len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4;
dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE);
dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE);
}
static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct spi_transfer *t)
{
struct dma_slave_config dma_sconfig = { 0 };
unsigned int len;
u8 dma_burst;
int ret = 0;
u32 val;
if (tqspi->is_packed) {
ret = tegra_qspi_dma_map_xfer(tqspi, t);
if (ret < 0)
return ret;
}
val = QSPI_DMA_BLK_SET(tqspi->curr_dma_words - 1);
tegra_qspi_writel(tqspi, val, QSPI_DMA_BLK);
tegra_qspi_unmask_irq(tqspi);
if (tqspi->is_packed)
len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4;
else
len = tqspi->curr_dma_words * 4;
/* set attention level based on length of transfer */
val = 0;
if (len & 0xf) {
val |= QSPI_TX_TRIG_1 | QSPI_RX_TRIG_1;
dma_burst = 1;
} else if (((len) >> 4) & 0x1) {
val |= QSPI_TX_TRIG_4 | QSPI_RX_TRIG_4;
dma_burst = 4;
} else {
val |= QSPI_TX_TRIG_8 | QSPI_RX_TRIG_8;
dma_burst = 8;
}
tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL);
tqspi->dma_control_reg = val;
dma_sconfig.device_fc = true;
if (tqspi->cur_direction & DATA_DIR_TX) {
dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO;
dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_sconfig.dst_maxburst = dma_burst;
ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig);
if (ret < 0) {
dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret);
return ret;
}
tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t);
ret = tegra_qspi_start_tx_dma(tqspi, t, len);
if (ret < 0) {
dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret);
return ret;
}
}
if (tqspi->cur_direction & DATA_DIR_RX) {
dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO;
dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_sconfig.src_maxburst = dma_burst;
ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig);
if (ret < 0) {
dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret);
return ret;
}
dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys,
tqspi->dma_buf_size,
DMA_FROM_DEVICE);
ret = tegra_qspi_start_rx_dma(tqspi, t, len);
if (ret < 0) {
dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret);
if (tqspi->cur_direction & DATA_DIR_TX)
dmaengine_terminate_all(tqspi->tx_dma_chan);
return ret;
}
}
tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1);
tqspi->is_curr_dma_xfer = true;
tqspi->dma_control_reg = val;
val |= QSPI_DMA_EN;
tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL);
return ret;
}
static int tegra_qspi_start_cpu_based_transfer(struct tegra_qspi *qspi, struct spi_transfer *t)
{
u32 val;
unsigned int cur_words;
if (qspi->cur_direction & DATA_DIR_TX)
cur_words = tegra_qspi_fill_tx_fifo_from_client_txbuf(qspi, t);
else
cur_words = qspi->curr_dma_words;
val = QSPI_DMA_BLK_SET(cur_words - 1);
tegra_qspi_writel(qspi, val, QSPI_DMA_BLK);
tegra_qspi_unmask_irq(qspi);
qspi->is_curr_dma_xfer = false;
val = qspi->command1_reg;
val |= QSPI_PIO;
tegra_qspi_writel(qspi, val, QSPI_COMMAND1);
return 0;
}
static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi)
{
if (tqspi->tx_dma_buf) {
dma_free_coherent(tqspi->dev, tqspi->dma_buf_size,
tqspi->tx_dma_buf, tqspi->tx_dma_phys);
tqspi->tx_dma_buf = NULL;
}
if (tqspi->tx_dma_chan) {
dma_release_channel(tqspi->tx_dma_chan);
tqspi->tx_dma_chan = NULL;
}
if (tqspi->rx_dma_buf) {
dma_free_coherent(tqspi->dev, tqspi->dma_buf_size,
tqspi->rx_dma_buf, tqspi->rx_dma_phys);
tqspi->rx_dma_buf = NULL;
}
if (tqspi->rx_dma_chan) {
dma_release_channel(tqspi->rx_dma_chan);
tqspi->rx_dma_chan = NULL;
}
}
static int tegra_qspi_init_dma(struct tegra_qspi *tqspi)
{
struct dma_chan *dma_chan;
dma_addr_t dma_phys;
u32 *dma_buf;
int err;
dma_chan = dma_request_chan(tqspi->dev, "rx");
if (IS_ERR(dma_chan)) {
err = PTR_ERR(dma_chan);
goto err_out;
}
tqspi->rx_dma_chan = dma_chan;
dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL);
if (!dma_buf) {
err = -ENOMEM;
goto err_out;
}
tqspi->rx_dma_buf = dma_buf;
tqspi->rx_dma_phys = dma_phys;
dma_chan = dma_request_chan(tqspi->dev, "tx");
if (IS_ERR(dma_chan)) {
err = PTR_ERR(dma_chan);
goto err_out;
}
tqspi->tx_dma_chan = dma_chan;
dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL);
if (!dma_buf) {
err = -ENOMEM;
goto err_out;
}
tqspi->tx_dma_buf = dma_buf;
tqspi->tx_dma_phys = dma_phys;
tqspi->use_dma = true;
return 0;
err_out:
tegra_qspi_deinit_dma(tqspi);
if (err != -EPROBE_DEFER) {
dev_err(tqspi->dev, "cannot use DMA: %d\n", err);
dev_err(tqspi->dev, "falling back to PIO\n");
return 0;
}
return err;
}
static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_transfer *t,
bool is_first_of_msg)
{
struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
struct tegra_qspi_client_data *cdata = spi->controller_data;
u32 command1, command2, speed = t->speed_hz;
u8 bits_per_word = t->bits_per_word;
u32 tx_tap = 0, rx_tap = 0;
int req_mode;
if (speed != tqspi->cur_speed) {
clk_set_rate(tqspi->clk, speed);
tqspi->cur_speed = speed;
}
tqspi->cur_pos = 0;
tqspi->cur_rx_pos = 0;
tqspi->cur_tx_pos = 0;
tqspi->curr_xfer = t;
if (is_first_of_msg) {
tegra_qspi_mask_clear_irq(tqspi);
command1 = tqspi->def_command1_reg;
command1 |= QSPI_BIT_LENGTH(bits_per_word - 1);
command1 &= ~QSPI_CONTROL_MODE_MASK;
req_mode = spi->mode & 0x3;
if (req_mode == SPI_MODE_3)
command1 |= QSPI_CONTROL_MODE_3;
else
command1 |= QSPI_CONTROL_MODE_0;
if (spi->mode & SPI_CS_HIGH)
command1 |= QSPI_CS_SW_VAL;
else
command1 &= ~QSPI_CS_SW_VAL;
tegra_qspi_writel(tqspi, command1, QSPI_COMMAND1);
if (cdata && cdata->tx_clk_tap_delay)
tx_tap = cdata->tx_clk_tap_delay;
if (cdata && cdata->rx_clk_tap_delay)
rx_tap = cdata->rx_clk_tap_delay;
command2 = QSPI_TX_TAP_DELAY(tx_tap) | QSPI_RX_TAP_DELAY(rx_tap);
if (command2 != tqspi->def_command2_reg)
tegra_qspi_writel(tqspi, command2, QSPI_COMMAND2);
} else {
command1 = tqspi->command1_reg;
command1 &= ~QSPI_BIT_LENGTH(~0);
command1 |= QSPI_BIT_LENGTH(bits_per_word - 1);
}
command1 &= ~QSPI_SDR_DDR_SEL;
return command1;
}
static int tegra_qspi_start_transfer_one(struct spi_device *spi,
struct spi_transfer *t, u32 command1)
{
struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
unsigned int total_fifo_words;
u8 bus_width = 0;
int ret;
total_fifo_words = tegra_qspi_calculate_curr_xfer_param(tqspi, t);
command1 &= ~QSPI_PACKED;
if (tqspi->is_packed)
command1 |= QSPI_PACKED;
tegra_qspi_writel(tqspi, command1, QSPI_COMMAND1);
tqspi->cur_direction = 0;
command1 &= ~(QSPI_TX_EN | QSPI_RX_EN);
if (t->rx_buf) {
command1 |= QSPI_RX_EN;
tqspi->cur_direction |= DATA_DIR_RX;
bus_width = t->rx_nbits;
}
if (t->tx_buf) {
command1 |= QSPI_TX_EN;
tqspi->cur_direction |= DATA_DIR_TX;
bus_width = t->tx_nbits;
}
command1 &= ~QSPI_INTERFACE_WIDTH_MASK;
if (bus_width == SPI_NBITS_QUAD)
command1 |= QSPI_INTERFACE_WIDTH_QUAD;
else if (bus_width == SPI_NBITS_DUAL)
command1 |= QSPI_INTERFACE_WIDTH_DUAL;
else
command1 |= QSPI_INTERFACE_WIDTH_SINGLE;
tqspi->command1_reg = command1;
tegra_qspi_writel(tqspi, QSPI_NUM_DUMMY_CYCLE(tqspi->dummy_cycles), QSPI_MISC_REG);
ret = tegra_qspi_flush_fifos(tqspi, false);
if (ret < 0)
return ret;
if (tqspi->use_dma && total_fifo_words > QSPI_FIFO_DEPTH)
ret = tegra_qspi_start_dma_based_transfer(tqspi, t);
else
ret = tegra_qspi_start_cpu_based_transfer(tqspi, t);
return ret;
}
static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_device *spi)
{
struct tegra_qspi_client_data *cdata;
struct device_node *slave_np = spi->dev.of_node;
cdata = kzalloc(sizeof(*cdata), GFP_KERNEL);
if (!cdata)
return NULL;
of_property_read_u32(slave_np, "nvidia,tx-clk-tap-delay",
&cdata->tx_clk_tap_delay);
of_property_read_u32(slave_np, "nvidia,rx-clk-tap-delay",
&cdata->rx_clk_tap_delay);
return cdata;
}
static void tegra_qspi_cleanup(struct spi_device *spi)
{
struct tegra_qspi_client_data *cdata = spi->controller_data;
spi->controller_data = NULL;
kfree(cdata);
}
static int tegra_qspi_setup(struct spi_device *spi)
{
struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
struct tegra_qspi_client_data *cdata = spi->controller_data;
unsigned long flags;
u32 val;
int ret;
ret = pm_runtime_resume_and_get(tqspi->dev);
if (ret < 0) {
dev_err(tqspi->dev, "failed to get runtime PM: %d\n", ret);
return ret;
}
if (!cdata) {
cdata = tegra_qspi_parse_cdata_dt(spi);
spi->controller_data = cdata;
}
spin_lock_irqsave(&tqspi->lock, flags);
/* keep default cs state to inactive */
val = tqspi->def_command1_reg;
if (spi->mode & SPI_CS_HIGH)
val &= ~QSPI_CS_SW_VAL;
else
val |= QSPI_CS_SW_VAL;
tqspi->def_command1_reg = val;
tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
spin_unlock_irqrestore(&tqspi->lock, flags);
pm_runtime_put(tqspi->dev);
return 0;
}
static void tegra_qspi_dump_regs(struct tegra_qspi *tqspi)
{
dev_dbg(tqspi->dev, "============ QSPI REGISTER DUMP ============\n");
dev_dbg(tqspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n",
tegra_qspi_readl(tqspi, QSPI_COMMAND1),
tegra_qspi_readl(tqspi, QSPI_COMMAND2));
dev_dbg(tqspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n",
tegra_qspi_readl(tqspi, QSPI_DMA_CTL),
tegra_qspi_readl(tqspi, QSPI_DMA_BLK));
dev_dbg(tqspi->dev, "INTR_MASK: 0x%08x | MISC: 0x%08x\n",
tegra_qspi_readl(tqspi, QSPI_INTR_MASK),
tegra_qspi_readl(tqspi, QSPI_MISC_REG));
dev_dbg(tqspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n",
tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS),
tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS));
}
static void tegra_qspi_handle_error(struct tegra_qspi *tqspi)
{
dev_err(tqspi->dev, "error in transfer, fifo status 0x%08x\n", tqspi->status_reg);
tegra_qspi_dump_regs(tqspi);
tegra_qspi_flush_fifos(tqspi, true);
reset_control_assert(tqspi->rst);
udelay(2);
reset_control_deassert(tqspi->rst);
}
static void tegra_qspi_transfer_end(struct spi_device *spi)
{
struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master);
int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
if (cs_val)
tqspi->command1_reg |= QSPI_CS_SW_VAL;
else
tqspi->command1_reg &= ~QSPI_CS_SW_VAL;
tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1);
tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
}
static int tegra_qspi_transfer_one_message(struct spi_master *master, struct spi_message *msg)
{
struct tegra_qspi *tqspi = spi_master_get_devdata(master);
struct spi_device *spi = msg->spi;
struct spi_transfer *transfer;
bool is_first_msg = true;
int ret;
msg->status = 0;
msg->actual_length = 0;
tqspi->tx_status = 0;
tqspi->rx_status = 0;
list_for_each_entry(transfer, &msg->transfers, transfer_list) {
struct spi_transfer *xfer = transfer;
u8 dummy_bytes = 0;
u32 cmd1;
tqspi->dummy_cycles = 0;
/*
* Tegra QSPI hardware supports dummy bytes transfer after actual transfer
* bytes based on programmed dummy clock cycles in the QSPI_MISC register.
* So, check if the next transfer is dummy data transfer and program dummy
* clock cycles along with the current transfer and skip next transfer.
*/
if (!list_is_last(&xfer->transfer_list, &msg->transfers)) {
struct spi_transfer *next_xfer;
next_xfer = list_next_entry(xfer, transfer_list);
if (next_xfer->dummy_data) {
u32 dummy_cycles = next_xfer->len * 8 / next_xfer->tx_nbits;
if (dummy_cycles <= QSPI_DUMMY_CYCLES_MAX) {
tqspi->dummy_cycles = dummy_cycles;
dummy_bytes = next_xfer->len;
transfer = next_xfer;
}
}
}
reinit_completion(&tqspi->xfer_completion);
cmd1 = tegra_qspi_setup_transfer_one(spi, xfer, is_first_msg);
ret = tegra_qspi_start_transfer_one(spi, xfer, cmd1);
if (ret < 0) {
dev_err(tqspi->dev, "failed to start transfer: %d\n", ret);
goto complete_xfer;
}
is_first_msg = false;
ret = wait_for_completion_timeout(&tqspi->xfer_completion,
QSPI_DMA_TIMEOUT);
if (WARN_ON(ret == 0)) {
dev_err(tqspi->dev, "transfer timeout: %d\n", ret);
if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_TX))
dmaengine_terminate_all(tqspi->tx_dma_chan);
if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_RX))
dmaengine_terminate_all(tqspi->rx_dma_chan);
tegra_qspi_handle_error(tqspi);
ret = -EIO;
goto complete_xfer;
}
if (tqspi->tx_status || tqspi->rx_status) {
tegra_qspi_handle_error(tqspi);
ret = -EIO;
goto complete_xfer;
}
msg->actual_length += xfer->len + dummy_bytes;
complete_xfer:
if (ret < 0) {
tegra_qspi_transfer_end(spi);
spi_transfer_delay_exec(xfer);
goto exit;
}
if (list_is_last(&xfer->transfer_list, &msg->transfers)) {
/* de-activate CS after last transfer only when cs_change is not set */
if (!xfer->cs_change) {
tegra_qspi_transfer_end(spi);
spi_transfer_delay_exec(xfer);
}
} else if (xfer->cs_change) {
/* de-activated CS between the transfers only when cs_change is set */
tegra_qspi_transfer_end(spi);
spi_transfer_delay_exec(xfer);
}
}
ret = 0;
exit:
msg->status = ret;
spi_finalize_current_message(master);
return ret;
}
static irqreturn_t handle_cpu_based_xfer(struct tegra_qspi *tqspi)
{
struct spi_transfer *t = tqspi->curr_xfer;
unsigned long flags;
spin_lock_irqsave(&tqspi->lock, flags);
if (tqspi->tx_status || tqspi->rx_status) {
tegra_qspi_handle_error(tqspi);
complete(&tqspi->xfer_completion);
goto exit;
}
if (tqspi->cur_direction & DATA_DIR_RX)
tegra_qspi_read_rx_fifo_to_client_rxbuf(tqspi, t);
if (tqspi->cur_direction & DATA_DIR_TX)
tqspi->cur_pos = tqspi->cur_tx_pos;
else
tqspi->cur_pos = tqspi->cur_rx_pos;
if (tqspi->cur_pos == t->len) {
complete(&tqspi->xfer_completion);
goto exit;
}
tegra_qspi_calculate_curr_xfer_param(tqspi, t);
tegra_qspi_start_cpu_based_transfer(tqspi, t);
exit:
spin_unlock_irqrestore(&tqspi->lock, flags);
return IRQ_HANDLED;
}
static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi)
{
struct spi_transfer *t = tqspi->curr_xfer;
unsigned int total_fifo_words;
unsigned long flags;
long wait_status;
int err = 0;
if (tqspi->cur_direction & DATA_DIR_TX) {
if (tqspi->tx_status) {
dmaengine_terminate_all(tqspi->tx_dma_chan);
err += 1;
} else {
wait_status = wait_for_completion_interruptible_timeout(
&tqspi->tx_dma_complete, QSPI_DMA_TIMEOUT);
if (wait_status <= 0) {
dmaengine_terminate_all(tqspi->tx_dma_chan);
dev_err(tqspi->dev, "failed TX DMA transfer\n");
err += 1;
}
}
}
if (tqspi->cur_direction & DATA_DIR_RX) {
if (tqspi->rx_status) {
dmaengine_terminate_all(tqspi->rx_dma_chan);
err += 2;
} else {
wait_status = wait_for_completion_interruptible_timeout(
&tqspi->rx_dma_complete, QSPI_DMA_TIMEOUT);
if (wait_status <= 0) {
dmaengine_terminate_all(tqspi->rx_dma_chan);
dev_err(tqspi->dev, "failed RX DMA transfer\n");
err += 2;
}
}
}
spin_lock_irqsave(&tqspi->lock, flags);
if (err) {
tegra_qspi_dma_unmap_xfer(tqspi, t);
tegra_qspi_handle_error(tqspi);
complete(&tqspi->xfer_completion);
goto exit;
}
if (tqspi->cur_direction & DATA_DIR_RX)
tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf(tqspi, t);
if (tqspi->cur_direction & DATA_DIR_TX)
tqspi->cur_pos = tqspi->cur_tx_pos;
else
tqspi->cur_pos = tqspi->cur_rx_pos;
if (tqspi->cur_pos == t->len) {
tegra_qspi_dma_unmap_xfer(tqspi, t);
complete(&tqspi->xfer_completion);
goto exit;
}
tegra_qspi_dma_unmap_xfer(tqspi, t);
/* continue transfer in current message */
total_fifo_words = tegra_qspi_calculate_curr_xfer_param(tqspi, t);
if (total_fifo_words > QSPI_FIFO_DEPTH)
err = tegra_qspi_start_dma_based_transfer(tqspi, t);
else
err = tegra_qspi_start_cpu_based_transfer(tqspi, t);
exit:
spin_unlock_irqrestore(&tqspi->lock, flags);
return IRQ_HANDLED;
}
static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data)
{
struct tegra_qspi *tqspi = context_data;
tqspi->status_reg = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
if (tqspi->cur_direction & DATA_DIR_TX)
tqspi->tx_status = tqspi->status_reg & (QSPI_TX_FIFO_UNF | QSPI_TX_FIFO_OVF);
if (tqspi->cur_direction & DATA_DIR_RX)
tqspi->rx_status = tqspi->status_reg & (QSPI_RX_FIFO_OVF | QSPI_RX_FIFO_UNF);
tegra_qspi_mask_clear_irq(tqspi);
if (!tqspi->is_curr_dma_xfer)
return handle_cpu_based_xfer(tqspi);
return handle_dma_based_xfer(tqspi);
}
static const struct of_device_id tegra_qspi_of_match[] = {
{ .compatible = "nvidia,tegra210-qspi", },
{ .compatible = "nvidia,tegra186-qspi", },
{ .compatible = "nvidia,tegra194-qspi", },
{}
};
MODULE_DEVICE_TABLE(of, tegra_qspi_of_match);
static int tegra_qspi_probe(struct platform_device *pdev)
{
struct spi_master *master;
struct tegra_qspi *tqspi;
struct resource *r;
int ret, qspi_irq;
int bus_num;
master = devm_spi_alloc_master(&pdev->dev, sizeof(*tqspi));
if (!master)
return -ENOMEM;
platform_set_drvdata(pdev, master);
tqspi = spi_master_get_devdata(master);
master->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_CS_HIGH |
SPI_TX_DUAL | SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD;
master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
master->setup = tegra_qspi_setup;
master->cleanup = tegra_qspi_cleanup;
master->transfer_one_message = tegra_qspi_transfer_one_message;
master->num_chipselect = 1;
master->auto_runtime_pm = true;
bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
if (bus_num >= 0)
master->bus_num = bus_num;
tqspi->master = master;
tqspi->dev = &pdev->dev;
spin_lock_init(&tqspi->lock);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
tqspi->base = devm_ioremap_resource(&pdev->dev, r);
if (IS_ERR(tqspi->base))
return PTR_ERR(tqspi->base);
tqspi->phys = r->start;
qspi_irq = platform_get_irq(pdev, 0);
tqspi->irq = qspi_irq;
tqspi->clk = devm_clk_get(&pdev->dev, "qspi");
if (IS_ERR(tqspi->clk)) {
ret = PTR_ERR(tqspi->clk);
dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
return ret;
}
tqspi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(tqspi->rst)) {
ret = PTR_ERR(tqspi->rst);
dev_err(&pdev->dev, "failed to get reset control: %d\n", ret);
return ret;
}
tqspi->max_buf_size = QSPI_FIFO_DEPTH << 2;
tqspi->dma_buf_size = DEFAULT_QSPI_DMA_BUF_LEN;
ret = tegra_qspi_init_dma(tqspi);
if (ret < 0)
return ret;
if (tqspi->use_dma)
tqspi->max_buf_size = tqspi->dma_buf_size;
init_completion(&tqspi->tx_dma_complete);
init_completion(&tqspi->rx_dma_complete);
init_completion(&tqspi->xfer_completion);
pm_runtime_enable(&pdev->dev);
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "failed to get runtime PM: %d\n", ret);
goto exit_pm_disable;
}
reset_control_assert(tqspi->rst);
udelay(2);
reset_control_deassert(tqspi->rst);
tqspi->def_command1_reg = QSPI_M_S | QSPI_CS_SW_HW | QSPI_CS_SW_VAL;
tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
tqspi->spi_cs_timing1 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING1);
tqspi->spi_cs_timing2 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING2);
tqspi->def_command2_reg = tegra_qspi_readl(tqspi, QSPI_COMMAND2);
pm_runtime_put(&pdev->dev);
ret = request_threaded_irq(tqspi->irq, NULL,
tegra_qspi_isr_thread, IRQF_ONESHOT,
dev_name(&pdev->dev), tqspi);
if (ret < 0) {
dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", tqspi->irq, ret);
goto exit_pm_disable;
}
master->dev.of_node = pdev->dev.of_node;
ret = spi_register_master(master);
if (ret < 0) {
dev_err(&pdev->dev, "failed to register master: %d\n", ret);
goto exit_free_irq;
}
return 0;
exit_free_irq:
free_irq(qspi_irq, tqspi);
exit_pm_disable:
pm_runtime_disable(&pdev->dev);
tegra_qspi_deinit_dma(tqspi);
return ret;
}
static int tegra_qspi_remove(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
struct tegra_qspi *tqspi = spi_master_get_devdata(master);
spi_unregister_master(master);
free_irq(tqspi->irq, tqspi);
pm_runtime_disable(&pdev->dev);
tegra_qspi_deinit_dma(tqspi);
return 0;
}
static int __maybe_unused tegra_qspi_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
return spi_master_suspend(master);
}
static int __maybe_unused tegra_qspi_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct tegra_qspi *tqspi = spi_master_get_devdata(master);
int ret;
ret = pm_runtime_resume_and_get(dev);
if (ret < 0) {
dev_err(dev, "failed to get runtime PM: %d\n", ret);
return ret;
}
tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1);
tegra_qspi_writel(tqspi, tqspi->def_command2_reg, QSPI_COMMAND2);
pm_runtime_put(dev);
return spi_master_resume(master);
}
static int __maybe_unused tegra_qspi_runtime_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct tegra_qspi *tqspi = spi_master_get_devdata(master);
/* flush all write which are in PPSB queue by reading back */
tegra_qspi_readl(tqspi, QSPI_COMMAND1);
clk_disable_unprepare(tqspi->clk);
return 0;
}
static int __maybe_unused tegra_qspi_runtime_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct tegra_qspi *tqspi = spi_master_get_devdata(master);
int ret;
ret = clk_prepare_enable(tqspi->clk);
if (ret < 0)
dev_err(tqspi->dev, "failed to enable clock: %d\n", ret);
return ret;
}
static const struct dev_pm_ops tegra_qspi_pm_ops = {
SET_RUNTIME_PM_OPS(tegra_qspi_runtime_suspend, tegra_qspi_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(tegra_qspi_suspend, tegra_qspi_resume)
};
static struct platform_driver tegra_qspi_driver = {
.driver = {
.name = "tegra-qspi",
.pm = &tegra_qspi_pm_ops,
.of_match_table = tegra_qspi_of_match,
},
.probe = tegra_qspi_probe,
.remove = tegra_qspi_remove,
};
module_platform_driver(tegra_qspi_driver);
MODULE_ALIAS("platform:qspi-tegra");
MODULE_DESCRIPTION("NVIDIA Tegra QSPI Controller Driver");
MODULE_AUTHOR("Sowjanya Komatineni <skomatineni@nvidia.com>");
MODULE_LICENSE("GPL v2");
drivers/spi/spi-txx9.c deleted 100644 → 0
View file @ 110bc220
/*
* TXx9 SPI controller driver.
*
* Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
* Copyright (C) 2000-2001 Toshiba Corporation
*
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
*
* Convert to generic SPI framework - Atsushi Nemoto (anemo@mba.ocn.ne.jp)
*/
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/spi/spi.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/gpio/machine.h>
#include <linux/gpio/consumer.h>
#define SPI_FIFO_SIZE 4
#define SPI_MAX_DIVIDER 0xff /* Max. value for SPCR1.SER */
#define SPI_MIN_DIVIDER 1 /* Min. value for SPCR1.SER */
#define TXx9_SPMCR 0x00
#define TXx9_SPCR0 0x04
#define TXx9_SPCR1 0x08
#define TXx9_SPFS 0x0c
#define TXx9_SPSR 0x14
#define TXx9_SPDR 0x18
/* SPMCR : SPI Master Control */
#define TXx9_SPMCR_OPMODE 0xc0
#define TXx9_SPMCR_CONFIG 0x40
#define TXx9_SPMCR_ACTIVE 0x80
#define TXx9_SPMCR_SPSTP 0x02
#define TXx9_SPMCR_BCLR 0x01
/* SPCR0 : SPI Control 0 */
#define TXx9_SPCR0_TXIFL_MASK 0xc000
#define TXx9_SPCR0_RXIFL_MASK 0x3000
#define TXx9_SPCR0_SIDIE 0x0800
#define TXx9_SPCR0_SOEIE 0x0400
#define TXx9_SPCR0_RBSIE 0x0200
#define TXx9_SPCR0_TBSIE 0x0100
#define TXx9_SPCR0_IFSPSE 0x0010
#define TXx9_SPCR0_SBOS 0x0004
#define TXx9_SPCR0_SPHA 0x0002
#define TXx9_SPCR0_SPOL 0x0001
/* SPSR : SPI Status */
#define TXx9_SPSR_TBSI 0x8000
#define TXx9_SPSR_RBSI 0x4000
#define TXx9_SPSR_TBS_MASK 0x3800
#define TXx9_SPSR_RBS_MASK 0x0700
#define TXx9_SPSR_SPOE 0x0080
#define TXx9_SPSR_IFSD 0x0008
#define TXx9_SPSR_SIDLE 0x0004
#define TXx9_SPSR_STRDY 0x0002
#define TXx9_SPSR_SRRDY 0x0001
struct txx9spi {
struct work_struct work;
spinlock_t lock; /* protect 'queue' */
struct list_head queue;
wait_queue_head_t waitq;
void __iomem *membase;
int baseclk;
struct clk *clk;
struct gpio_desc *last_chipselect;
int last_chipselect_val;
};
static u32 txx9spi_rd(struct txx9spi *c, int reg)
{
return __raw_readl(c->membase + reg);
}
static void txx9spi_wr(struct txx9spi *c, u32 val, int reg)
{
__raw_writel(val, c->membase + reg);
}
static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c,
int on, unsigned int cs_delay)
{
/*
* The GPIO descriptor will track polarity inversion inside
* gpiolib.
*/
if (on) {
/* deselect the chip with cs_change hint in last transfer */
if (c->last_chipselect)
gpiod_set_value(c->last_chipselect,
!c->last_chipselect_val);
c->last_chipselect = spi->cs_gpiod;
c->last_chipselect_val = on;
} else {
c->last_chipselect = NULL;
ndelay(cs_delay); /* CS Hold Time */
}
gpiod_set_value(spi->cs_gpiod, on);
ndelay(cs_delay); /* CS Setup Time / CS Recovery Time */
}
static int txx9spi_setup(struct spi_device *spi)
{
struct txx9spi *c = spi_master_get_devdata(spi->master);
if (!spi->max_speed_hz)
return -EINVAL;
/* deselect chip */
spin_lock(&c->lock);
txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz);
spin_unlock(&c->lock);
return 0;
}
static irqreturn_t txx9spi_interrupt(int irq, void *dev_id)
{
struct txx9spi *c = dev_id;
/* disable rx intr */
txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE,
TXx9_SPCR0);
wake_up(&c->waitq);
return IRQ_HANDLED;
}
static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m)
{
struct spi_device *spi = m->spi;
struct spi_transfer *t;
unsigned int cs_delay;
unsigned int cs_change = 1;
int status = 0;
u32 mcr;
u32 prev_speed_hz = 0;
u8 prev_bits_per_word = 0;
/* CS setup/hold/recovery time in nsec */
cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz;
mcr = txx9spi_rd(c, TXx9_SPMCR);
if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) {
dev_err(&spi->dev, "Bad mode.\n");
status = -EIO;
goto exit;
}
mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
/* enter config mode */
txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
txx9spi_wr(c, TXx9_SPCR0_SBOS
| ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0)
| ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0)
| 0x08,
TXx9_SPCR0);
list_for_each_entry(t, &m->transfers, transfer_list) {
const void *txbuf = t->tx_buf;
void *rxbuf = t->rx_buf;
u32 data;
unsigned int len = t->len;
unsigned int wsize;
u32 speed_hz = t->speed_hz;
u8 bits_per_word = t->bits_per_word;
wsize = bits_per_word >> 3; /* in bytes */
if (prev_speed_hz != speed_hz
|| prev_bits_per_word != bits_per_word) {
int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1;
n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER);
/* enter config mode */
txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR,
TXx9_SPMCR);
txx9spi_wr(c, (n << 8) | bits_per_word, TXx9_SPCR1);
/* enter active mode */
txx9spi_wr(c, mcr | TXx9_SPMCR_ACTIVE, TXx9_SPMCR);
prev_speed_hz = speed_hz;
prev_bits_per_word = bits_per_word;
}
if (cs_change)
txx9spi_cs_func(spi, c, 1, cs_delay);
cs_change = t->cs_change;
while (len) {
unsigned int count = SPI_FIFO_SIZE;
int i;
u32 cr0;
if (len < count * wsize)
count = len / wsize;
/* now tx must be idle... */
while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE))
cpu_relax();
cr0 = txx9spi_rd(c, TXx9_SPCR0);
cr0 &= ~TXx9_SPCR0_RXIFL_MASK;
cr0 |= (count - 1) << 12;
/* enable rx intr */
cr0 |= TXx9_SPCR0_RBSIE;
txx9spi_wr(c, cr0, TXx9_SPCR0);
/* send */
for (i = 0; i < count; i++) {
if (txbuf) {
data = (wsize == 1)
? *(const u8 *)txbuf
: *(const u16 *)txbuf;
txx9spi_wr(c, data, TXx9_SPDR);
txbuf += wsize;
} else
txx9spi_wr(c, 0, TXx9_SPDR);
}
/* wait all rx data */
wait_event(c->waitq,
txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI);
/* receive */
for (i = 0; i < count; i++) {
data = txx9spi_rd(c, TXx9_SPDR);
if (rxbuf) {
if (wsize == 1)
*(u8 *)rxbuf = data;
else
*(u16 *)rxbuf = data;
rxbuf += wsize;
}
}
len -= count * wsize;
}
m->actual_length += t->len;
spi_transfer_delay_exec(t);
if (!cs_change)
continue;
if (t->transfer_list.next == &m->transfers)
break;
/* sometimes a short mid-message deselect of the chip
* may be needed to terminate a mode or command
*/
txx9spi_cs_func(spi, c, 0, cs_delay);
}
exit:
m->status = status;
if (m->complete)
m->complete(m->context);
/* normally deactivate chipselect ... unless no error and
* cs_change has hinted that the next message will probably
* be for this chip too.
*/
if (!(status == 0 && cs_change))
txx9spi_cs_func(spi, c, 0, cs_delay);
/* enter config mode */
txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
}
static void txx9spi_work(struct work_struct *work)
{
struct txx9spi *c = container_of(work, struct txx9spi, work);
unsigned long flags;
spin_lock_irqsave(&c->lock, flags);
while (!list_empty(&c->queue)) {
struct spi_message *m;
m = container_of(c->queue.next, struct spi_message, queue);
list_del_init(&m->queue);
spin_unlock_irqrestore(&c->lock, flags);
txx9spi_work_one(c, m);
spin_lock_irqsave(&c->lock, flags);
}
spin_unlock_irqrestore(&c->lock, flags);
}
static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m)
{
struct spi_master *master = spi->master;
struct txx9spi *c = spi_master_get_devdata(master);
struct spi_transfer *t;
unsigned long flags;
m->actual_length = 0;
/* check each transfer's parameters */
list_for_each_entry(t, &m->transfers, transfer_list) {
if (!t->tx_buf && !t->rx_buf && t->len)
return -EINVAL;
}
spin_lock_irqsave(&c->lock, flags);
list_add_tail(&m->queue, &c->queue);
schedule_work(&c->work);
spin_unlock_irqrestore(&c->lock, flags);
return 0;
}
/*
* Chip select uses GPIO only, further the driver is using the chip select
* numer (from the device tree "reg" property, and this can only come from
* device tree since this i MIPS and there is no way to pass platform data) as
* the GPIO number. As the platform has only one GPIO controller (the txx9 GPIO
* chip) it is thus using the chip select number as an offset into that chip.
* This chip has a maximum of 16 GPIOs 0..15 and this is what all platforms
* register.
*
* We modernized this behaviour by explicitly converting that offset to an
* offset on the GPIO chip using a GPIO descriptor machine table of the same
* size as the txx9 GPIO chip with a 1-to-1 mapping of chip select to GPIO
* offset.
*
* This is admittedly a hack, but it is countering the hack of using "reg" to
* contain a GPIO offset when it should be using "cs-gpios" as the SPI bindings
* state.
*/
static struct gpiod_lookup_table txx9spi_cs_gpio_table = {
.dev_id = "spi0",
.table = {
GPIO_LOOKUP_IDX("TXx9", 0, "cs", 0, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 1, "cs", 1, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 2, "cs", 2, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 3, "cs", 3, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 4, "cs", 4, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 5, "cs", 5, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 6, "cs", 6, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 7, "cs", 7, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 8, "cs", 8, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 9, "cs", 9, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 10, "cs", 10, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 11, "cs", 11, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 12, "cs", 12, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 13, "cs", 13, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 14, "cs", 14, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("TXx9", 15, "cs", 15, GPIO_ACTIVE_LOW),
{ },
},
};
static int txx9spi_probe(struct platform_device *dev)
{
struct spi_master *master;
struct txx9spi *c;
struct resource *res;
int ret = -ENODEV;
u32 mcr;
int irq;
master = spi_alloc_master(&dev->dev, sizeof(*c));
if (!master)
return ret;
c = spi_master_get_devdata(master);
platform_set_drvdata(dev, master);
INIT_WORK(&c->work, txx9spi_work);
spin_lock_init(&c->lock);
INIT_LIST_HEAD(&c->queue);
init_waitqueue_head(&c->waitq);
c->clk = devm_clk_get(&dev->dev, "spi-baseclk");
if (IS_ERR(c->clk)) {
ret = PTR_ERR(c->clk);
c->clk = NULL;
goto exit;
}
ret = clk_prepare_enable(c->clk);
if (ret) {
c->clk = NULL;
goto exit;
}
c->baseclk = clk_get_rate(c->clk);
master->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1);
master->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1);
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
c->membase = devm_ioremap_resource(&dev->dev, res);
if (IS_ERR(c->membase))
goto exit_busy;
/* enter config mode */
mcr = txx9spi_rd(c, TXx9_SPMCR);
mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
irq = platform_get_irq(dev, 0);
if (irq < 0)
goto exit_busy;
ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0,
"spi_txx9", c);
if (ret)
goto exit;
c->last_chipselect = NULL;
dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n",
(unsigned long long)res->start, irq,
(c->baseclk + 500000) / 1000000);
gpiod_add_lookup_table(&txx9spi_cs_gpio_table);
/* the spi->mode bits understood by this driver: */
master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
master->bus_num = dev->id;
master->setup = txx9spi_setup;
master->transfer = txx9spi_transfer;
master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */
master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
master->use_gpio_descriptors = true;
ret = devm_spi_register_master(&dev->dev, master);
if (ret)
goto exit;
return 0;
exit_busy:
ret = -EBUSY;
exit:
clk_disable_unprepare(c->clk);
spi_master_put(master);
return ret;
}
static int txx9spi_remove(struct platform_device *dev)
{
struct spi_master *master = platform_get_drvdata(dev);
struct txx9spi *c = spi_master_get_devdata(master);
flush_work(&c->work);
clk_disable_unprepare(c->clk);
return 0;
}
/* work with hotplug and coldplug */
MODULE_ALIAS("platform:spi_txx9");
static struct platform_driver txx9spi_driver = {
.probe = txx9spi_probe,
.remove = txx9spi_remove,
.driver = {
.name = "spi_txx9",
},
};
static int __init txx9spi_init(void)
{
return platform_driver_register(&txx9spi_driver);
}
subsys_initcall(txx9spi_init);
static void __exit txx9spi_exit(void)
{
platform_driver_unregister(&txx9spi_driver);
}
module_exit(txx9spi_exit);
MODULE_DESCRIPTION("TXx9 SPI Driver");
MODULE_LICENSE("GPL");
drivers/spi/spi.c
View file @ eec262d1
......@@ -810,7 +810,8 @@ static void spi_set_cs(struct spi_device *spi, bool enable)
spi->controller->last_cs_enable = enable;
spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH;
if (!spi->controller->set_cs_timing) {
if (spi->cs_gpiod || gpio_is_valid(spi->cs_gpio) ||
!spi->controller->set_cs_timing) {
if (enable1)
spi_delay_exec(&spi->controller->cs_setup, NULL);
else
......@@ -841,7 +842,8 @@ static void spi_set_cs(struct spi_device *spi, bool enable)
spi->controller->set_cs(spi, !enable);
}
if (!spi->controller->set_cs_timing) {
if (spi->cs_gpiod || gpio_is_valid(spi->cs_gpio) ||
!spi->controller->set_cs_timing) {
if (!enable1)
spi_delay_exec(&spi->controller->cs_inactive, NULL);
}
......@@ -1945,6 +1947,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
/* Device DUAL/QUAD mode */
if (!of_property_read_u32(nc, "spi-tx-bus-width", &value)) {
switch (value) {
case 0:
spi->mode |= SPI_NO_TX;
break;
case 1:
break;
case 2:
......@@ -1966,6 +1971,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
if (!of_property_read_u32(nc, "spi-rx-bus-width", &value)) {
switch (value) {
case 0:
spi->mode |= SPI_NO_RX;
break;
case 1:
break;
case 2:
......@@ -3333,12 +3341,16 @@ int spi_setup(struct spi_device *spi)
unsigned bad_bits, ugly_bits;
int status;
/* check mode to prevent that DUAL and QUAD set at the same time
/*
* check mode to prevent that any two of DUAL, QUAD and NO_MOSI/MISO
* are set at the same time
*/
if (((spi->mode & SPI_TX_DUAL) && (spi->mode & SPI_TX_QUAD)) ||
((spi->mode & SPI_RX_DUAL) && (spi->mode & SPI_RX_QUAD))) {
if ((hweight_long(spi->mode &
(SPI_TX_DUAL | SPI_TX_QUAD | SPI_NO_TX)) > 1) ||
(hweight_long(spi->mode &
(SPI_RX_DUAL | SPI_RX_QUAD | SPI_NO_RX)) > 1)) {
dev_err(&spi->dev,
"setup: can not select dual and quad at the same time\n");
"setup: can not select any two of dual, quad and no-rx/tx at the same time\n");
return -EINVAL;
}
/* if it is SPI_3WIRE mode, DUAL and QUAD should be forbidden
......@@ -3352,7 +3364,8 @@ int spi_setup(struct spi_device *spi)
* SPI_CS_WORD has a fallback software implementation,
* so it is ignored here.
*/
bad_bits = spi->mode & ~(spi->controller->mode_bits | SPI_CS_WORD);
bad_bits = spi->mode & ~(spi->controller->mode_bits | SPI_CS_WORD |
SPI_NO_TX | SPI_NO_RX);
/* nothing prevents from working with active-high CS in case if it
* is driven by GPIO.
*/
......@@ -3449,11 +3462,31 @@ EXPORT_SYMBOL_GPL(spi_setup);
int spi_set_cs_timing(struct spi_device *spi, struct spi_delay *setup,
struct spi_delay *hold, struct spi_delay *inactive)
{
struct device *parent = spi->controller->dev.parent;
size_t len;
int status;
if (spi->controller->set_cs_timing &&
!(spi->cs_gpiod || gpio_is_valid(spi->cs_gpio))) {
if (spi->controller->auto_runtime_pm) {
status = pm_runtime_get_sync(parent);
if (status < 0) {
pm_runtime_put_noidle(parent);
dev_err(&spi->controller->dev, "Failed to power device: %d\n",
status);
return status;
}
if (spi->controller->set_cs_timing)
return spi->controller->set_cs_timing(spi, setup, hold,
inactive);
status = spi->controller->set_cs_timing(spi, setup,
hold, inactive);
pm_runtime_mark_last_busy(parent);
pm_runtime_put_autosuspend(parent);
return status;
} else {
return spi->controller->set_cs_timing(spi, setup, hold,
inactive);
}
}
if ((setup && setup->unit == SPI_DELAY_UNIT_SCK) ||
(hold && hold->unit == SPI_DELAY_UNIT_SCK) ||
......@@ -3615,6 +3648,8 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message)
* 2. check tx/rx_nbits match the mode in spi_device
*/
if (xfer->tx_buf) {
if (spi->mode & SPI_NO_TX)
return -EINVAL;
if (xfer->tx_nbits != SPI_NBITS_SINGLE &&
xfer->tx_nbits != SPI_NBITS_DUAL &&
xfer->tx_nbits != SPI_NBITS_QUAD)
......@@ -3628,6 +3663,8 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message)
}
/* check transfer rx_nbits */
if (xfer->rx_buf) {
if (spi->mode & SPI_NO_RX)
return -EINVAL;
if (xfer->rx_nbits != SPI_NBITS_SINGLE &&
xfer->rx_nbits != SPI_NBITS_DUAL &&
xfer->rx_nbits != SPI_NBITS_QUAD)
......
include/dt-bindings/clock/tegra210-car.h
View file @ eec262d1
......@@ -307,7 +307,7 @@
#define TEGRA210_CLK_AUDIO4 275
#define TEGRA210_CLK_SPDIF 276
/* 277 */
/* 278 */
#define TEGRA210_CLK_QSPI_PM 278
/* 279 */
/* 280 */
#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
......
include/linux/platform_data/efm32-spi.h deleted 100644 → 0
View file @ 110bc220
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LINUX_PLATFORM_DATA_EFM32_SPI_H__
#define __LINUX_PLATFORM_DATA_EFM32_SPI_H__
#include <linux/types.h>
/**
* struct efm32_spi_pdata
* @location: pinmux location for the I/O pins (to be written to the ROUTE
* register)
*/
struct efm32_spi_pdata {
u8 location;
};
#endif /* ifndef __LINUX_PLATFORM_DATA_EFM32_SPI_H__ */
include/linux/spi/spi-mem.h
View file @ eec262d1
......@@ -311,6 +311,9 @@ void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
bool spi_mem_default_supports_op(struct spi_mem *mem,
const struct spi_mem_op *op);
bool spi_mem_dtr_supports_op(struct spi_mem *mem,
const struct spi_mem_op *op);
#else
static inline int
spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
......@@ -334,6 +337,12 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
return false;
}
static inline
bool spi_mem_dtr_supports_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
return false;
}
#endif /* CONFIG_SPI_MEM */
int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op);
......
include/linux/spi/spi.h
View file @ eec262d1
......@@ -6,6 +6,7 @@
#ifndef __LINUX_SPI_H
#define __LINUX_SPI_H
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/mod_devicetable.h>
#include <linux/slab.h>
......@@ -15,6 +16,8 @@
#include <linux/gpio/consumer.h>
#include <linux/ptp_clock_kernel.h>
#include <uapi/linux/spi/spi.h>
struct dma_chan;
struct property_entry;
struct spi_controller;
......@@ -164,28 +167,19 @@ struct spi_device {
u8 chip_select;
u8 bits_per_word;
bool rt;
#define SPI_NO_TX BIT(31) /* no transmit wire */
#define SPI_NO_RX BIT(30) /* no receive wire */
/*
* All bits defined above should be covered by SPI_MODE_KERNEL_MASK.
* The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart,
* which is defined in 'include/uapi/linux/spi/spi.h'.
* The bits defined here are from bit 31 downwards, while in
* SPI_MODE_USER_MASK are from 0 upwards.
* These bits must not overlap. A static assert check should make sure of that.
* If adding extra bits, make sure to decrease the bit index below as well.
*/
#define SPI_MODE_KERNEL_MASK (~(BIT(30) - 1))
u32 mode;
#define SPI_CPHA 0x01 /* clock phase */
#define SPI_CPOL 0x02 /* clock polarity */
#define SPI_MODE_0 (0|0) /* (original MicroWire) */
#define SPI_MODE_1 (0|SPI_CPHA)
#define SPI_MODE_2 (SPI_CPOL|0)
#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
#define SPI_MODE_X_MASK (SPI_CPOL|SPI_CPHA)
#define SPI_CS_HIGH 0x04 /* chipselect active high? */
#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
#define SPI_3WIRE 0x10 /* SI/SO signals shared */
#define SPI_LOOP 0x20 /* loopback mode */
#define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */
#define SPI_READY 0x80 /* slave pulls low to pause */
#define SPI_TX_DUAL 0x100 /* transmit with 2 wires */
#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
#define SPI_RX_DUAL 0x400 /* receive with 2 wires */
#define SPI_RX_QUAD 0x800 /* receive with 4 wires */
#define SPI_CS_WORD 0x1000 /* toggle cs after each word */
#define SPI_TX_OCTAL 0x2000 /* transmit with 8 wires */
#define SPI_RX_OCTAL 0x4000 /* receive with 8 wires */
#define SPI_3WIRE_HIZ 0x8000 /* high impedance turnaround */
int irq;
void *controller_state;
void *controller_data;
......@@ -208,6 +202,10 @@ struct spi_device {
*/
};
/* Make sure that SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK don't overlap */
static_assert((SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK) == 0,
"SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK must not overlap");
static inline struct spi_device *to_spi_device(struct device *dev)
{
return dev ? container_of(dev, struct spi_device, dev) : NULL;
......@@ -624,7 +622,7 @@ struct spi_controller {
/*
* These hooks are for drivers that use a generic implementation
* of transfer_one_message() provied by the core.
* of transfer_one_message() provided by the core.
*/
void (*set_cs)(struct spi_device *spi, bool enable);
int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi,
......@@ -827,6 +825,7 @@ extern void spi_res_release(struct spi_controller *ctlr,
* transfer. If 0 the default (from @spi_device) is used.
* @bits_per_word: select a bits_per_word other than the device default
* for this transfer. If 0 the default (from @spi_device) is used.
* @dummy_data: indicates transfer is dummy bytes transfer.
* @cs_change: affects chipselect after this transfer completes
* @cs_change_delay: delay between cs deassert and assert when
* @cs_change is set and @spi_transfer is not the last in @spi_message
......@@ -939,6 +938,7 @@ struct spi_transfer {
struct sg_table tx_sg;
struct sg_table rx_sg;
unsigned dummy_data:1;
unsigned cs_change:1;
unsigned tx_nbits:3;
unsigned rx_nbits:3;
......
include/uapi/linux/spi/spi.h 0 → 100644
View file @ eec262d1
/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
#ifndef _UAPI_SPI_H
#define _UAPI_SPI_H
#include <linux/const.h>
#define SPI_CPHA _BITUL(0) /* clock phase */
#define SPI_CPOL _BITUL(1) /* clock polarity */
#define SPI_MODE_0 (0|0) /* (original MicroWire) */
#define SPI_MODE_1 (0|SPI_CPHA)
#define SPI_MODE_2 (SPI_CPOL|0)
#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
#define SPI_MODE_X_MASK (SPI_CPOL|SPI_CPHA)
#define SPI_CS_HIGH _BITUL(2) /* chipselect active high? */
#define SPI_LSB_FIRST _BITUL(3) /* per-word bits-on-wire */
#define SPI_3WIRE _BITUL(4) /* SI/SO signals shared */
#define SPI_LOOP _BITUL(5) /* loopback mode */
#define SPI_NO_CS _BITUL(6) /* 1 dev/bus, no chipselect */
#define SPI_READY _BITUL(7) /* slave pulls low to pause */
#define SPI_TX_DUAL _BITUL(8) /* transmit with 2 wires */
#define SPI_TX_QUAD _BITUL(9) /* transmit with 4 wires */
#define SPI_RX_DUAL _BITUL(10) /* receive with 2 wires */
#define SPI_RX_QUAD _BITUL(11) /* receive with 4 wires */
#define SPI_CS_WORD _BITUL(12) /* toggle cs after each word */
#define SPI_TX_OCTAL _BITUL(13) /* transmit with 8 wires */
#define SPI_RX_OCTAL _BITUL(14) /* receive with 8 wires */
#define SPI_3WIRE_HIZ _BITUL(15) /* high impedance turnaround */
/*
* All the bits defined above should be covered by SPI_MODE_USER_MASK.
* The SPI_MODE_USER_MASK has the SPI_MODE_KERNEL_MASK counterpart in
* 'include/linux/spi/spi.h'. The bits defined here are from bit 0 upwards
* while in SPI_MODE_KERNEL_MASK they are from the other end downwards.
* These bits must not overlap. A static assert check should make sure of that.
* If adding extra bits, make sure to increase the bit index below as well.
*/
#define SPI_MODE_USER_MASK (_BITUL(16) - 1)
#endif /* _UAPI_SPI_H */
include/uapi/linux/spi/spidev.h
View file @ eec262d1
......@@ -25,35 +25,7 @@
#include <linux/types.h>
#include <linux/ioctl.h>
/* User space versions of kernel symbols for SPI clocking modes,
* matching <linux/spi/spi.h>
*/
#define SPI_CPHA 0x01
#define SPI_CPOL 0x02
#define SPI_MODE_0 (0|0)
#define SPI_MODE_1 (0|SPI_CPHA)
#define SPI_MODE_2 (SPI_CPOL|0)
#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
#define SPI_CS_HIGH 0x04
#define SPI_LSB_FIRST 0x08
#define SPI_3WIRE 0x10
#define SPI_LOOP 0x20
#define SPI_NO_CS 0x40
#define SPI_READY 0x80
#define SPI_TX_DUAL 0x100
#define SPI_TX_QUAD 0x200
#define SPI_RX_DUAL 0x400
#define SPI_RX_QUAD 0x800
#define SPI_CS_WORD 0x1000
#define SPI_TX_OCTAL 0x2000
#define SPI_RX_OCTAL 0x4000
#define SPI_3WIRE_HIZ 0x8000
/*---------------------------------------------------------------------------*/
#include <linux/spi/spi.h>
/* IOCTL commands */
......
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