Commit f1be7b6c authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'drm-fixes-2023-04-13' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Daniel Vetter:

 - two fbcon regressions

 - amdgpu: dp mst, smu13

 - i915: dual link dsi for tgl+

 - armada, nouveau, drm/sched, fbmem

* tag 'drm-fixes-2023-04-13' of git://anongit.freedesktop.org/drm/drm:
  fbcon: set_con2fb_map needs to set con2fb_map!
  fbcon: Fix error paths in set_con2fb_map
  drm/amd/pm: correct the pcie link state check for SMU13
  drm/amd/pm: correct SMU13.0.7 max shader clock reporting
  drm/amd/pm: correct SMU13.0.7 pstate profiling clock settings
  drm/amd/display: Pass the right info to drm_dp_remove_payload
  drm/armada: Fix a potential double free in an error handling path
  fbmem: Reject FB_ACTIVATE_KD_TEXT from userspace
  drm/nouveau/fb: add missing sysmen flush callbacks
  drm/i915/dsi: fix DSS CTL register offsets for TGL+
  drm/scheduler: Fix UAF race in drm_sched_entity_push_job()
parents de466448 cab29322
...@@ -177,6 +177,40 @@ void dm_helpers_dp_update_branch_info( ...@@ -177,6 +177,40 @@ void dm_helpers_dp_update_branch_info(
const struct dc_link *link) const struct dc_link *link)
{} {}
static void dm_helpers_construct_old_payload(
struct dc_link *link,
int pbn_per_slot,
struct drm_dp_mst_atomic_payload *new_payload,
struct drm_dp_mst_atomic_payload *old_payload)
{
struct link_mst_stream_allocation_table current_link_table =
link->mst_stream_alloc_table;
struct link_mst_stream_allocation *dc_alloc;
int i;
*old_payload = *new_payload;
/* Set correct time_slots/PBN of old payload.
* other fields (delete & dsc_enabled) in
* struct drm_dp_mst_atomic_payload are don't care fields
* while calling drm_dp_remove_payload()
*/
for (i = 0; i < current_link_table.stream_count; i++) {
dc_alloc =
&current_link_table.stream_allocations[i];
if (dc_alloc->vcp_id == new_payload->vcpi) {
old_payload->time_slots = dc_alloc->slot_count;
old_payload->pbn = dc_alloc->slot_count * pbn_per_slot;
break;
}
}
/* make sure there is an old payload*/
ASSERT(i != current_link_table.stream_count);
}
/* /*
* Writes payload allocation table in immediate downstream device. * Writes payload allocation table in immediate downstream device.
*/ */
...@@ -188,7 +222,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( ...@@ -188,7 +222,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
{ {
struct amdgpu_dm_connector *aconnector; struct amdgpu_dm_connector *aconnector;
struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_topology_state *mst_state;
struct drm_dp_mst_atomic_payload *payload; struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload;
struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_topology_mgr *mst_mgr;
aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
...@@ -204,17 +238,26 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( ...@@ -204,17 +238,26 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
/* It's OK for this to fail */ /* It's OK for this to fail */
payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
if (enable)
drm_dp_add_payload_part1(mst_mgr, mst_state, payload); if (enable) {
else target_payload = new_payload;
drm_dp_remove_payload(mst_mgr, mst_state, payload, payload);
drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload);
} else {
/* construct old payload by VCPI*/
dm_helpers_construct_old_payload(stream->link, mst_state->pbn_div,
new_payload, &old_payload);
target_payload = &old_payload;
drm_dp_remove_payload(mst_mgr, mst_state, &old_payload, new_payload);
}
/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
* AUX message. The sequence is slot 1-63 allocated sequence for each * AUX message. The sequence is slot 1-63 allocated sequence for each
* stream. AMD ASIC stream slot allocation should follow the same * stream. AMD ASIC stream slot allocation should follow the same
* sequence. copy DRM MST allocation to dc */ * sequence. copy DRM MST allocation to dc */
fill_dc_mst_payload_table_from_drm(stream->link, enable, payload, proposed_table); fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table);
return true; return true;
} }
......
...@@ -61,6 +61,12 @@ ...@@ -61,6 +61,12 @@
#define CTF_OFFSET_HOTSPOT 5 #define CTF_OFFSET_HOTSPOT 5
#define CTF_OFFSET_MEM 5 #define CTF_OFFSET_MEM 5
static const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
static const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
#define DECODE_GEN_SPEED(gen_speed_idx) (pmfw_decoded_link_speed[gen_speed_idx])
#define DECODE_LANE_WIDTH(lane_width_idx) (pmfw_decoded_link_width[lane_width_idx])
struct smu_13_0_max_sustainable_clocks { struct smu_13_0_max_sustainable_clocks {
uint32_t display_clock; uint32_t display_clock;
uint32_t phy_clock; uint32_t phy_clock;
......
...@@ -1144,8 +1144,8 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu, ...@@ -1144,8 +1144,8 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
(pcie_table->pcie_lane[i] == 5) ? "x12" : (pcie_table->pcie_lane[i] == 5) ? "x12" :
(pcie_table->pcie_lane[i] == 6) ? "x16" : "", (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
pcie_table->clk_freq[i], pcie_table->clk_freq[i],
((gen_speed - 1) == pcie_table->pcie_gen[i]) && (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
(lane_width == link_width[pcie_table->pcie_lane[i]]) ? (lane_width == DECODE_LANE_WIDTH(link_width[pcie_table->pcie_lane[i]])) ?
"*" : ""); "*" : "");
break; break;
......
...@@ -575,6 +575,14 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) ...@@ -575,6 +575,14 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu)
dpm_table); dpm_table);
if (ret) if (ret)
return ret; return ret;
if (skutable->DriverReportedClocks.GameClockAc &&
(dpm_table->dpm_levels[dpm_table->count - 1].value >
skutable->DriverReportedClocks.GameClockAc)) {
dpm_table->dpm_levels[dpm_table->count - 1].value =
skutable->DriverReportedClocks.GameClockAc;
dpm_table->max = skutable->DriverReportedClocks.GameClockAc;
}
} else { } else {
dpm_table->count = 1; dpm_table->count = 1;
dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
...@@ -828,6 +836,57 @@ static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu, ...@@ -828,6 +836,57 @@ static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu,
return ret; return ret;
} }
static int smu_v13_0_7_get_dpm_ultimate_freq(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *min,
uint32_t *max)
{
struct smu_13_0_dpm_context *dpm_context =
smu->smu_dpm.dpm_context;
struct smu_13_0_dpm_table *dpm_table;
switch (clk_type) {
case SMU_MCLK:
case SMU_UCLK:
/* uclk dpm table */
dpm_table = &dpm_context->dpm_tables.uclk_table;
break;
case SMU_GFXCLK:
case SMU_SCLK:
/* gfxclk dpm table */
dpm_table = &dpm_context->dpm_tables.gfx_table;
break;
case SMU_SOCCLK:
/* socclk dpm table */
dpm_table = &dpm_context->dpm_tables.soc_table;
break;
case SMU_FCLK:
/* fclk dpm table */
dpm_table = &dpm_context->dpm_tables.fclk_table;
break;
case SMU_VCLK:
case SMU_VCLK1:
/* vclk dpm table */
dpm_table = &dpm_context->dpm_tables.vclk_table;
break;
case SMU_DCLK:
case SMU_DCLK1:
/* dclk dpm table */
dpm_table = &dpm_context->dpm_tables.dclk_table;
break;
default:
dev_err(smu->adev->dev, "Unsupported clock type!\n");
return -EINVAL;
}
if (min)
*min = dpm_table->min;
if (max)
*max = dpm_table->max;
return 0;
}
static int smu_v13_0_7_read_sensor(struct smu_context *smu, static int smu_v13_0_7_read_sensor(struct smu_context *smu,
enum amd_pp_sensors sensor, enum amd_pp_sensors sensor,
void *data, void *data,
...@@ -1074,8 +1133,8 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu, ...@@ -1074,8 +1133,8 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
(pcie_table->pcie_lane[i] == 5) ? "x12" : (pcie_table->pcie_lane[i] == 5) ? "x12" :
(pcie_table->pcie_lane[i] == 6) ? "x16" : "", (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
pcie_table->clk_freq[i], pcie_table->clk_freq[i],
(gen_speed == pcie_table->pcie_gen[i]) && (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
(lane_width == pcie_table->pcie_lane[i]) ? (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
"*" : ""); "*" : "");
break; break;
...@@ -1329,8 +1388,16 @@ static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu) ...@@ -1329,8 +1388,16 @@ static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
&dpm_context->dpm_tables.fclk_table; &dpm_context->dpm_tables.fclk_table;
struct smu_umd_pstate_table *pstate_table = struct smu_umd_pstate_table *pstate_table =
&smu->pstate_table; &smu->pstate_table;
struct smu_table_context *table_context = &smu->smu_table;
PPTable_t *pptable = table_context->driver_pptable;
DriverReportedClocks_t driver_clocks =
pptable->SkuTable.DriverReportedClocks;
pstate_table->gfxclk_pstate.min = gfx_table->min; pstate_table->gfxclk_pstate.min = gfx_table->min;
if (driver_clocks.GameClockAc &&
(driver_clocks.GameClockAc < gfx_table->max))
pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
else
pstate_table->gfxclk_pstate.peak = gfx_table->max; pstate_table->gfxclk_pstate.peak = gfx_table->max;
pstate_table->uclk_pstate.min = mem_table->min; pstate_table->uclk_pstate.min = mem_table->min;
...@@ -1348,12 +1415,12 @@ static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu) ...@@ -1348,12 +1415,12 @@ static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
pstate_table->fclk_pstate.min = fclk_table->min; pstate_table->fclk_pstate.min = fclk_table->min;
pstate_table->fclk_pstate.peak = fclk_table->max; pstate_table->fclk_pstate.peak = fclk_table->max;
/* if (driver_clocks.BaseClockAc &&
* For now, just use the mininum clock frequency. driver_clocks.BaseClockAc < gfx_table->max)
* TODO: update them when the real pstate settings available pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
*/ else
pstate_table->gfxclk_pstate.standard = gfx_table->min; pstate_table->gfxclk_pstate.standard = gfx_table->max;
pstate_table->uclk_pstate.standard = mem_table->min; pstate_table->uclk_pstate.standard = mem_table->max;
pstate_table->socclk_pstate.standard = soc_table->min; pstate_table->socclk_pstate.standard = soc_table->min;
pstate_table->vclk_pstate.standard = vclk_table->min; pstate_table->vclk_pstate.standard = vclk_table->min;
pstate_table->dclk_pstate.standard = dclk_table->min; pstate_table->dclk_pstate.standard = dclk_table->min;
...@@ -1676,7 +1743,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { ...@@ -1676,7 +1743,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
.dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable, .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
.init_pptable_microcode = smu_v13_0_init_pptable_microcode, .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
.populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk, .populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk,
.get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq, .get_dpm_ultimate_freq = smu_v13_0_7_get_dpm_ultimate_freq,
.get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
.read_sensor = smu_v13_0_7_read_sensor, .read_sensor = smu_v13_0_7_read_sensor,
.feature_is_enabled = smu_cmn_feature_is_enabled, .feature_is_enabled = smu_cmn_feature_is_enabled,
......
...@@ -99,7 +99,6 @@ static int armada_drm_bind(struct device *dev) ...@@ -99,7 +99,6 @@ static int armada_drm_bind(struct device *dev)
if (ret) { if (ret) {
dev_err(dev, "[" DRM_NAME ":%s] can't kick out simple-fb: %d\n", dev_err(dev, "[" DRM_NAME ":%s] can't kick out simple-fb: %d\n",
__func__, ret); __func__, ret);
kfree(priv);
return ret; return ret;
} }
......
...@@ -300,9 +300,21 @@ static void configure_dual_link_mode(struct intel_encoder *encoder, ...@@ -300,9 +300,21 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
{ {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
u32 dss_ctl1; u32 dss_ctl1;
dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); /* FIXME: Move all DSS handling to intel_vdsc.c */
if (DISPLAY_VER(dev_priv) >= 12) {
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
} else {
dss_ctl1_reg = DSS_CTL1;
dss_ctl2_reg = DSS_CTL2;
}
dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
dss_ctl1 |= SPLITTER_ENABLE; dss_ctl1 |= SPLITTER_ENABLE;
dss_ctl1 &= ~OVERLAP_PIXELS_MASK; dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
...@@ -323,16 +335,16 @@ static void configure_dual_link_mode(struct intel_encoder *encoder, ...@@ -323,16 +335,16 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg);
dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2);
} else { } else {
/* Interleave */ /* Interleave */
dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
} }
intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1);
} }
/* aka DSI 8X clock */ /* aka DSI 8X clock */
......
...@@ -31,6 +31,7 @@ gf108_fb = { ...@@ -31,6 +31,7 @@ gf108_fb = {
.init = gf100_fb_init, .init = gf100_fb_init,
.init_page = gf100_fb_init_page, .init_page = gf100_fb_init_page,
.intr = gf100_fb_intr, .intr = gf100_fb_intr,
.sysmem.flush_page_init = gf100_fb_sysmem_flush_page_init,
.ram_new = gf108_ram_new, .ram_new = gf108_ram_new,
.default_bigpage = 17, .default_bigpage = 17,
}; };
......
...@@ -77,6 +77,7 @@ gk104_fb = { ...@@ -77,6 +77,7 @@ gk104_fb = {
.init = gf100_fb_init, .init = gf100_fb_init,
.init_page = gf100_fb_init_page, .init_page = gf100_fb_init_page,
.intr = gf100_fb_intr, .intr = gf100_fb_intr,
.sysmem.flush_page_init = gf100_fb_sysmem_flush_page_init,
.ram_new = gk104_ram_new, .ram_new = gk104_ram_new,
.default_bigpage = 17, .default_bigpage = 17,
.clkgate_pack = gk104_fb_clkgate_pack, .clkgate_pack = gk104_fb_clkgate_pack,
......
...@@ -59,6 +59,7 @@ gk110_fb = { ...@@ -59,6 +59,7 @@ gk110_fb = {
.init = gf100_fb_init, .init = gf100_fb_init,
.init_page = gf100_fb_init_page, .init_page = gf100_fb_init_page,
.intr = gf100_fb_intr, .intr = gf100_fb_intr,
.sysmem.flush_page_init = gf100_fb_sysmem_flush_page_init,
.ram_new = gk104_ram_new, .ram_new = gk104_ram_new,
.default_bigpage = 17, .default_bigpage = 17,
.clkgate_pack = gk110_fb_clkgate_pack, .clkgate_pack = gk110_fb_clkgate_pack,
......
...@@ -31,6 +31,7 @@ gm107_fb = { ...@@ -31,6 +31,7 @@ gm107_fb = {
.init = gf100_fb_init, .init = gf100_fb_init,
.init_page = gf100_fb_init_page, .init_page = gf100_fb_init_page,
.intr = gf100_fb_intr, .intr = gf100_fb_intr,
.sysmem.flush_page_init = gf100_fb_sysmem_flush_page_init,
.ram_new = gm107_ram_new, .ram_new = gm107_ram_new,
.default_bigpage = 17, .default_bigpage = 17,
}; };
......
...@@ -507,12 +507,19 @@ void drm_sched_entity_push_job(struct drm_sched_job *sched_job) ...@@ -507,12 +507,19 @@ void drm_sched_entity_push_job(struct drm_sched_job *sched_job)
{ {
struct drm_sched_entity *entity = sched_job->entity; struct drm_sched_entity *entity = sched_job->entity;
bool first; bool first;
ktime_t submit_ts;
trace_drm_sched_job(sched_job, entity); trace_drm_sched_job(sched_job, entity);
atomic_inc(entity->rq->sched->score); atomic_inc(entity->rq->sched->score);
WRITE_ONCE(entity->last_user, current->group_leader); WRITE_ONCE(entity->last_user, current->group_leader);
/*
* After the sched_job is pushed into the entity queue, it may be
* completed and freed up at any time. We can no longer access it.
* Make sure to set the submit_ts first, to avoid a race.
*/
sched_job->submit_ts = submit_ts = ktime_get();
first = spsc_queue_push(&entity->job_queue, &sched_job->queue_node); first = spsc_queue_push(&entity->job_queue, &sched_job->queue_node);
sched_job->submit_ts = ktime_get();
/* first job wakes up scheduler */ /* first job wakes up scheduler */
if (first) { if (first) {
...@@ -529,7 +536,7 @@ void drm_sched_entity_push_job(struct drm_sched_job *sched_job) ...@@ -529,7 +536,7 @@ void drm_sched_entity_push_job(struct drm_sched_job *sched_job)
spin_unlock(&entity->rq_lock); spin_unlock(&entity->rq_lock);
if (drm_sched_policy == DRM_SCHED_POLICY_FIFO) if (drm_sched_policy == DRM_SCHED_POLICY_FIFO)
drm_sched_rq_update_fifo(entity, sched_job->submit_ts); drm_sched_rq_update_fifo(entity, submit_ts);
drm_sched_wakeup(entity->rq->sched); drm_sched_wakeup(entity->rq->sched);
} }
......
...@@ -823,7 +823,7 @@ static int set_con2fb_map(int unit, int newidx, int user) ...@@ -823,7 +823,7 @@ static int set_con2fb_map(int unit, int newidx, int user)
int oldidx = con2fb_map[unit]; int oldidx = con2fb_map[unit];
struct fb_info *info = fbcon_registered_fb[newidx]; struct fb_info *info = fbcon_registered_fb[newidx];
struct fb_info *oldinfo = NULL; struct fb_info *oldinfo = NULL;
int found, err = 0, show_logo; int err = 0, show_logo;
WARN_CONSOLE_UNLOCKED(); WARN_CONSOLE_UNLOCKED();
...@@ -841,26 +841,26 @@ static int set_con2fb_map(int unit, int newidx, int user) ...@@ -841,26 +841,26 @@ static int set_con2fb_map(int unit, int newidx, int user)
if (oldidx != -1) if (oldidx != -1)
oldinfo = fbcon_registered_fb[oldidx]; oldinfo = fbcon_registered_fb[oldidx];
found = search_fb_in_map(newidx); if (!search_fb_in_map(newidx)) {
if (!err && !found) {
err = con2fb_acquire_newinfo(vc, info, unit); err = con2fb_acquire_newinfo(vc, info, unit);
if (!err) if (err)
con2fb_map[unit] = newidx; return err;
fbcon_add_cursor_work(info);
} }
con2fb_map[unit] = newidx;
/* /*
* If old fb is not mapped to any of the consoles, * If old fb is not mapped to any of the consoles,
* fbcon should release it. * fbcon should release it.
*/ */
if (!err && oldinfo && !search_fb_in_map(oldidx)) if (oldinfo && !search_fb_in_map(oldidx))
con2fb_release_oldinfo(vc, oldinfo, info); con2fb_release_oldinfo(vc, oldinfo, info);
show_logo = (fg_console == 0 && !user && show_logo = (fg_console == 0 && !user &&
logo_shown != FBCON_LOGO_DONTSHOW); logo_shown != FBCON_LOGO_DONTSHOW);
if (!found)
fbcon_add_cursor_work(info);
con2fb_map_boot[unit] = newidx; con2fb_map_boot[unit] = newidx;
con2fb_init_display(vc, info, unit, show_logo); con2fb_init_display(vc, info, unit, show_logo);
......
...@@ -1116,6 +1116,8 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, ...@@ -1116,6 +1116,8 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
case FBIOPUT_VSCREENINFO: case FBIOPUT_VSCREENINFO:
if (copy_from_user(&var, argp, sizeof(var))) if (copy_from_user(&var, argp, sizeof(var)))
return -EFAULT; return -EFAULT;
/* only for kernel-internal use */
var.activate &= ~FB_ACTIVATE_KD_TEXT;
console_lock(); console_lock();
lock_fb_info(info); lock_fb_info(info);
ret = fbcon_modechange_possible(info, &var); ret = fbcon_modechange_possible(info, &var);
......
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