Commit f1d2736c authored by Seungwon Jeon's avatar Seungwon Jeon Committed by Chris Ball

mmc: dw_mmc: control card read threshold

Card Read Threshold should be ensured that the card clock does not stop
in the middle of a block of data being transferred from the card to the
Host. Specially, clock stop is allowed in fast transfer such as HS200
or SDR104 mode. And so, it should be enabled.
Signed-off-by: default avatarSeungwon Jeon <tgih.jun@samsung.com>
Tested-by: default avatarAlim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: default avatarChris Ball <cjb@laptop.org>
parent 52426899
...@@ -570,6 +570,37 @@ static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) ...@@ -570,6 +570,37 @@ static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
#endif #endif
} }
static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
{
unsigned int blksz = data->blksz;
u32 blksz_depth, fifo_depth;
u16 thld_size;
WARN_ON(!(data->flags & MMC_DATA_READ));
if (host->timing != MMC_TIMING_MMC_HS200 &&
host->timing != MMC_TIMING_UHS_SDR104)
goto disable;
blksz_depth = blksz / (1 << host->data_shift);
fifo_depth = host->fifo_depth;
if (blksz_depth > fifo_depth)
goto disable;
/*
* If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
* If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
* Currently just choose blksz.
*/
thld_size = blksz;
mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
return;
disable:
mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
}
static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
{ {
int sg_len; int sg_len;
...@@ -627,10 +658,12 @@ static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) ...@@ -627,10 +658,12 @@ static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
host->sg = NULL; host->sg = NULL;
host->data = data; host->data = data;
if (data->flags & MMC_DATA_READ) if (data->flags & MMC_DATA_READ) {
host->dir_status = DW_MCI_RECV_STATUS; host->dir_status = DW_MCI_RECV_STATUS;
else dw_mci_ctrl_rd_thld(host, data);
} else {
host->dir_status = DW_MCI_SEND_STATUS; host->dir_status = DW_MCI_SEND_STATUS;
}
if (dw_mci_submit_data_dma(host, data)) { if (dw_mci_submit_data_dma(host, data)) {
int flags = SG_MITER_ATOMIC; int flags = SG_MITER_ATOMIC;
...@@ -877,6 +910,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ...@@ -877,6 +910,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
regs &= ~((0x1 << slot->id) << 16); regs &= ~((0x1 << slot->id) << 16);
mci_writel(slot->host, UHS_REG, regs); mci_writel(slot->host, UHS_REG, regs);
slot->host->timing = ios->timing;
/* /*
* Use mirror of ios->clock to prevent race with mmc * Use mirror of ios->clock to prevent race with mmc
......
...@@ -53,6 +53,7 @@ ...@@ -53,6 +53,7 @@
#define SDMMC_IDINTEN 0x090 #define SDMMC_IDINTEN 0x090
#define SDMMC_DSCADDR 0x094 #define SDMMC_DSCADDR 0x094
#define SDMMC_BUFADDR 0x098 #define SDMMC_BUFADDR 0x098
#define SDMMC_CDTHRCTL 0x100
#define SDMMC_DATA(x) (x) #define SDMMC_DATA(x) (x)
/* /*
...@@ -146,6 +147,8 @@ ...@@ -146,6 +147,8 @@
#define SDMMC_IDMAC_SWRESET BIT(0) #define SDMMC_IDMAC_SWRESET BIT(0)
/* Version ID register define */ /* Version ID register define */
#define SDMMC_GET_VERID(x) ((x) & 0xFFFF) #define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
/* Card read threshold */
#define SDMMC_SET_RD_THLD(v, x) (((v) & 0x1FFF) << 16 | (x))
/* Register access macros */ /* Register access macros */
#define mci_readl(dev, reg) \ #define mci_readl(dev, reg) \
......
...@@ -130,6 +130,7 @@ struct dw_mci { ...@@ -130,6 +130,7 @@ struct dw_mci {
struct mmc_command *cmd; struct mmc_command *cmd;
struct mmc_data *data; struct mmc_data *data;
unsigned int prev_blksz; unsigned int prev_blksz;
unsigned char timing;
struct workqueue_struct *card_workqueue; struct workqueue_struct *card_workqueue;
/* DMA interface members*/ /* DMA interface members*/
......
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