Commit f449c7c1 authored by Stephen Hemminger's avatar Stephen Hemminger Committed by Jeff Garzik

sky2: rename BMU register

This register is more of a test and control register on Yukon2.
So rename it to Q_TEST and give some bit definitions.
Signed-off-by: default avatarStephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent fc99fe06
...@@ -1140,7 +1140,7 @@ static int sky2_rx_start(struct sky2_port *sky2) ...@@ -1140,7 +1140,7 @@ static int sky2_rx_start(struct sky2_port *sky2)
if (hw->chip_id == CHIP_ID_YUKON_EC_U && if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
(hw->chip_rev == CHIP_REV_YU_EC_U_A1 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
|| hw->chip_rev == CHIP_REV_YU_EC_U_B0)) || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
......
...@@ -592,23 +592,15 @@ enum { ...@@ -592,23 +592,15 @@ enum {
enum { enum {
B8_Q_REGS = 0x0400, /* base of Queue registers */ B8_Q_REGS = 0x0400, /* base of Queue registers */
Q_D = 0x00, /* 8*32 bit Current Descriptor */ Q_D = 0x00, /* 8*32 bit Current Descriptor */
Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */ Q_VLAN = 0x20, /* 16 bit Current VLAN Tag */
Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */ Q_DONE = 0x24, /* 16 bit Done Index */
Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */ Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */ Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
Q_BC = 0x30, /* 32 bit Current Byte Counter */ Q_BC = 0x30, /* 32 bit Current Byte Counter */
Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */ Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
Q_F = 0x38, /* 32 bit Flag Register */ Q_TEST = 0x38, /* 32 bit Test/Control Register */
Q_T1 = 0x3c, /* 32 bit Test Register 1 */
Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
Q_T2 = 0x40, /* 32 bit Test Register 2 */
Q_T3 = 0x44, /* 32 bit Test Register 3 */
/* Yukon-2 */ /* Yukon-2 */
Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
Q_WM = 0x40, /* 16 bit FIFO Watermark */ Q_WM = 0x40, /* 16 bit FIFO Watermark */
Q_AL = 0x42, /* 8 bit FIFO Alignment */ Q_AL = 0x42, /* 8 bit FIFO Alignment */
Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */ Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
...@@ -622,15 +614,16 @@ enum { ...@@ -622,15 +614,16 @@ enum {
}; };
#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
/* Q_F 32 bit Flag Register */ /* Q_TEST 32 bit Test Register */
enum { enum {
F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */ /* Transmit */
F_EMPTY = 1<<27, /* Tx FIFO: empty flag */ F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */
F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */ F_TX_CHK_AUTO_ON = 1<<30, /* Tx checksum auto calc off (Yukon EX) */
F_WM_REACHED = 1<<25, /* Watermark reached */
/* Receive */
F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */ F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */ /* Hardware testbits not used */
}; };
/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
......
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