drm/i915: Move context descriptor fields to intel_lrc.h

This is a more appropriate header for these definitions.

v2:
 - Cleanup whitespace. (Lucas)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220301231549.1817978-7-matthew.d.roper@intel.com

drivers/gpu/drm/i915/gt/intel_engine_cs.c

@@ -21,6 +21,7 @@
 #include "intel_gt.h"
 #include "intel_gt_requests.h"
 #include "intel_gt_pm.h"
+#include "intel_lrc.h"
 #include "intel_lrc_reg.h"
 #include "intel_reset.h"
 #include "intel_ring.h"

drivers/gpu/drm/i915/gt/intel_gt_regs.h

@@ -1499,38 +1499,4 @@
 
 #define GEN12_SFC_DONE(n)			_MMIO(0x1cc000 + (n) * 0x1000)
 
-enum {
-	INTEL_ADVANCED_CONTEXT = 0,
-	INTEL_LEGACY_32B_CONTEXT,
-	INTEL_ADVANCED_AD_CONTEXT,
-	INTEL_LEGACY_64B_CONTEXT
-};
-
-enum {
-	FAULT_AND_HANG = 0,
-	FAULT_AND_HALT, /* Debug only */
-	FAULT_AND_STREAM,
-	FAULT_AND_CONTINUE /* Unsupported */
-};
-
-#define   CTX_GTT_ADDRESS_MASK			GENMASK(31, 12)
-#define   GEN8_CTX_VALID			(1 << 0)
-#define   GEN8_CTX_FORCE_PD_RESTORE		(1 << 1)
-#define   GEN8_CTX_FORCE_RESTORE		(1 << 2)
-#define   GEN8_CTX_L3LLC_COHERENT		(1 << 5)
-#define   GEN8_CTX_PRIVILEGE			(1 << 8)
-#define   GEN8_CTX_ADDRESSING_MODE_SHIFT	3
-#define   GEN8_CTX_ID_SHIFT			32
-#define   GEN8_CTX_ID_WIDTH			21
-#define   GEN11_SW_CTX_ID_SHIFT			37
-#define   GEN11_SW_CTX_ID_WIDTH			11
-#define   GEN11_ENGINE_CLASS_SHIFT		61
-#define   GEN11_ENGINE_CLASS_WIDTH		3
-#define   GEN11_ENGINE_INSTANCE_SHIFT		48
-#define   GEN11_ENGINE_INSTANCE_WIDTH		6
-#define   XEHP_SW_CTX_ID_SHIFT			39
-#define   XEHP_SW_CTX_ID_WIDTH			16
-#define   XEHP_SW_COUNTER_SHIFT			58
-#define   XEHP_SW_COUNTER_WIDTH			6
-
 #endif /* __INTEL_GT_REGS__ */

drivers/gpu/drm/i915/gt/intel_lrc.h

@@ -69,4 +69,38 @@ void lrc_check_regs(const struct intel_context *ce,
 
 void lrc_update_runtime(struct intel_context *ce);
 
+enum {
+	INTEL_ADVANCED_CONTEXT = 0,
+	INTEL_LEGACY_32B_CONTEXT,
+	INTEL_ADVANCED_AD_CONTEXT,
+	INTEL_LEGACY_64B_CONTEXT
+};
+
+enum {
+	FAULT_AND_HANG = 0,
+	FAULT_AND_HALT, /* Debug only */
+	FAULT_AND_STREAM,
+	FAULT_AND_CONTINUE /* Unsupported */
+};
+
+#define CTX_GTT_ADDRESS_MASK			GENMASK(31, 12)
+#define GEN8_CTX_VALID				(1 << 0)
+#define GEN8_CTX_FORCE_PD_RESTORE		(1 << 1)
+#define GEN8_CTX_FORCE_RESTORE			(1 << 2)
+#define GEN8_CTX_L3LLC_COHERENT			(1 << 5)
+#define GEN8_CTX_PRIVILEGE			(1 << 8)
+#define GEN8_CTX_ADDRESSING_MODE_SHIFT		3
+#define GEN8_CTX_ID_SHIFT			32
+#define GEN8_CTX_ID_WIDTH			21
+#define GEN11_SW_CTX_ID_SHIFT			37
+#define GEN11_SW_CTX_ID_WIDTH			11
+#define GEN11_ENGINE_CLASS_SHIFT		61
+#define GEN11_ENGINE_CLASS_WIDTH		3
+#define GEN11_ENGINE_INSTANCE_SHIFT		48
+#define GEN11_ENGINE_INSTANCE_WIDTH		6
+#define XEHP_SW_CTX_ID_SHIFT			39
+#define XEHP_SW_CTX_ID_WIDTH			16
+#define XEHP_SW_COUNTER_SHIFT			58
+#define XEHP_SW_COUNTER_WIDTH			6
+
 #endif /* __INTEL_LRC_H__ */