Commit f524f829 authored by Dan Murphy's avatar Dan Murphy Committed by Marc Kleine-Budde

can: m_can: Create a m_can platform framework

Create a m_can platform framework that peripheral
devices can register to and use common code and register sets.
The peripheral devices may provide read/write and configuration
support of the IP.
Acked-by: default avatarWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: default avatarDan Murphy <dmurphy@ti.com>
Acked-by: default avatarFaiz Abbas <faiz_abbas@ti.com>
Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parent 69652195
# SPDX-License-Identifier: GPL-2.0-only # SPDX-License-Identifier: GPL-2.0-only
config CAN_M_CAN config CAN_M_CAN
tristate "Bosch M_CAN support"
---help---
Say Y here if you want support for Bosch M_CAN controller framework.
This is common support for devices that embed the Bosch M_CAN IP.
config CAN_M_CAN_PLATFORM
tristate "Bosch M_CAN support for io-mapped devices"
depends on HAS_IOMEM depends on HAS_IOMEM
tristate "Bosch M_CAN devices" depends on CAN_M_CAN
---help--- ---help---
Say Y here if you want to support for Bosch M_CAN controller. Say Y here if you want support for IO Mapped Bosch M_CAN controller.
This support is for devices that have the Bosch M_CAN controller
IP embedded into the device and the IP is IO Mapped to the processor.
...@@ -4,3 +4,4 @@ ...@@ -4,3 +4,4 @@
# #
obj-$(CONFIG_CAN_M_CAN) += m_can.o obj-$(CONFIG_CAN_M_CAN) += m_can.o
obj-$(CONFIG_CAN_M_CAN_PLATFORM) += m_can_platform.o
/* // SPDX-License-Identifier: GPL-2.0
* CAN bus driver for Bosch M_CAN controller // CAN bus driver for Bosch M_CAN controller
* // Copyright (C) 2014 Freescale Semiconductor, Inc.
* Copyright (C) 2014 Freescale Semiconductor, Inc. // Dong Aisheng <b29396@freescale.com>
* Dong Aisheng <b29396@freescale.com> // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
*
* Bosch M_CAN user manual can be obtained from: /* Bosch M_CAN user manual can be obtained from:
* http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/ * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
* mcan_users_manual_v302.pdf * mcan_users_manual_v302.pdf
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/ */
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/kernel.h> #include <linux/kernel.h>
...@@ -28,11 +22,7 @@ ...@@ -28,11 +22,7 @@
#include <linux/can/dev.h> #include <linux/can/dev.h>
#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/consumer.h>
/* napi related */ #include "m_can.h"
#define M_CAN_NAPI_WEIGHT 64
/* message ram configuration data length */
#define MRAM_CFG_LEN 8
/* registers definition */ /* registers definition */
enum m_can_reg { enum m_can_reg {
...@@ -86,28 +76,11 @@ enum m_can_reg { ...@@ -86,28 +76,11 @@ enum m_can_reg {
M_CAN_TXEFA = 0xf8, M_CAN_TXEFA = 0xf8,
}; };
/* m_can lec values */ /* napi related */
enum m_can_lec_type { #define M_CAN_NAPI_WEIGHT 64
LEC_NO_ERROR = 0,
LEC_STUFF_ERROR,
LEC_FORM_ERROR,
LEC_ACK_ERROR,
LEC_BIT1_ERROR,
LEC_BIT0_ERROR,
LEC_CRC_ERROR,
LEC_UNUSED,
};
enum m_can_mram_cfg { /* message ram configuration data length */
MRAM_SIDF = 0, #define MRAM_CFG_LEN 8
MRAM_XIDF,
MRAM_RXF0,
MRAM_RXF1,
MRAM_RXB,
MRAM_TXE,
MRAM_TXB,
MRAM_CFG_NUM,
};
/* Core Release Register (CREL) */ /* Core Release Register (CREL) */
#define CREL_REL_SHIFT 28 #define CREL_REL_SHIFT 28
...@@ -347,74 +320,69 @@ enum m_can_mram_cfg { ...@@ -347,74 +320,69 @@ enum m_can_mram_cfg {
#define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT #define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
#define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT) #define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
/* address offset and element number for each FIFO/Buffer in the Message RAM */ static inline u32 m_can_read(struct m_can_priv *priv, enum m_can_reg reg)
struct mram_cfg { {
u16 off; return priv->ops->read_reg(priv, reg);
u8 num; }
};
/* m_can private data structure */
struct m_can_priv {
struct can_priv can; /* must be the first member */
struct napi_struct napi;
struct net_device *dev;
struct device *device;
struct clk *hclk;
struct clk *cclk;
void __iomem *base;
u32 irqstatus;
int version;
/* message ram configuration */
void __iomem *mram_base;
struct mram_cfg mcfg[MRAM_CFG_NUM];
};
static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg) static inline void m_can_write(struct m_can_priv *priv, enum m_can_reg reg,
u32 val)
{ {
return readl(priv->base + reg); priv->ops->write_reg(priv, reg, val);
} }
static inline void m_can_write(const struct m_can_priv *priv, static u32 m_can_fifo_read(struct m_can_priv *priv,
enum m_can_reg reg, u32 val) u32 fgi, unsigned int offset)
{ {
writel(val, priv->base + reg); u32 addr_offset = priv->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +
offset;
return priv->ops->read_fifo(priv, addr_offset);
} }
static inline u32 m_can_fifo_read(const struct m_can_priv *priv, static void m_can_fifo_write(struct m_can_priv *priv,
u32 fgi, unsigned int offset) u32 fpi, unsigned int offset, u32 val)
{ {
return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off + u32 addr_offset = priv->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE +
fgi * RXF0_ELEMENT_SIZE + offset); offset;
priv->ops->write_fifo(priv, addr_offset, val);
} }
static inline void m_can_fifo_write(const struct m_can_priv *priv, static inline void m_can_fifo_write_no_off(struct m_can_priv *priv,
u32 fpi, unsigned int offset, u32 val) u32 fpi, u32 val)
{ {
writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off + priv->ops->write_fifo(priv, fpi, val);
fpi * TXB_ELEMENT_SIZE + offset);
} }
static inline u32 m_can_txe_fifo_read(const struct m_can_priv *priv, static u32 m_can_txe_fifo_read(struct m_can_priv *priv, u32 fgi, u32 offset)
u32 fgi, {
u32 offset) { u32 addr_offset = priv->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE +
return readl(priv->mram_base + priv->mcfg[MRAM_TXE].off + offset;
fgi * TXE_ELEMENT_SIZE + offset);
return priv->ops->read_fifo(priv, addr_offset);
} }
static inline bool m_can_tx_fifo_full(const struct m_can_priv *priv) static inline bool m_can_tx_fifo_full(struct m_can_priv *priv)
{ {
return !!(m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQF); return !!(m_can_read(priv, M_CAN_TXFQS) & TXFQS_TFQF);
} }
static inline void m_can_config_endisable(const struct m_can_priv *priv, void m_can_config_endisable(struct m_can_priv *priv, bool enable)
bool enable)
{ {
u32 cccr = m_can_read(priv, M_CAN_CCCR); u32 cccr = m_can_read(priv, M_CAN_CCCR);
u32 timeout = 10; u32 timeout = 10;
u32 val = 0; u32 val = 0;
/* Clear the Clock stop request if it was set */
if (cccr & CCCR_CSR)
cccr &= ~CCCR_CSR;
if (enable) { if (enable) {
/* Clear the Clock stop request if it was set */
if (cccr & CCCR_CSR)
cccr &= ~CCCR_CSR;
/* enable m_can configuration */ /* enable m_can configuration */
m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT); m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT);
udelay(5); udelay(5);
...@@ -430,7 +398,7 @@ static inline void m_can_config_endisable(const struct m_can_priv *priv, ...@@ -430,7 +398,7 @@ static inline void m_can_config_endisable(const struct m_can_priv *priv,
while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {
if (timeout == 0) { if (timeout == 0) {
netdev_warn(priv->dev, "Failed to init module\n"); netdev_warn(priv->net, "Failed to init module\n");
return; return;
} }
timeout--; timeout--;
...@@ -438,17 +406,34 @@ static inline void m_can_config_endisable(const struct m_can_priv *priv, ...@@ -438,17 +406,34 @@ static inline void m_can_config_endisable(const struct m_can_priv *priv,
} }
} }
static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv) static inline void m_can_enable_all_interrupts(struct m_can_priv *priv)
{ {
/* Only interrupt line 0 is used in this driver */ /* Only interrupt line 0 is used in this driver */
m_can_write(priv, M_CAN_ILE, ILE_EINT0); m_can_write(priv, M_CAN_ILE, ILE_EINT0);
} }
static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv) static inline void m_can_disable_all_interrupts(struct m_can_priv *priv)
{ {
m_can_write(priv, M_CAN_ILE, 0x0); m_can_write(priv, M_CAN_ILE, 0x0);
} }
static void m_can_clean(struct net_device *net)
{
struct m_can_priv *priv = netdev_priv(net);
if (priv->tx_skb) {
int putidx = 0;
net->stats.tx_errors++;
if (priv->version > 30)
putidx = ((m_can_read(priv, M_CAN_TXFQS) &
TXFQS_TFQPI_MASK) >> TXFQS_TFQPI_SHIFT);
can_free_echo_skb(priv->net, putidx);
priv->tx_skb = NULL;
}
}
static void m_can_read_fifo(struct net_device *dev, u32 rxfs) static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
{ {
struct net_device_stats *stats = &dev->stats; struct net_device_stats *stats = &dev->stats;
...@@ -633,9 +618,12 @@ static int m_can_clk_start(struct m_can_priv *priv) ...@@ -633,9 +618,12 @@ static int m_can_clk_start(struct m_can_priv *priv)
{ {
int err; int err;
err = pm_runtime_get_sync(priv->device); if (priv->pm_clock_support == 0)
return 0;
err = pm_runtime_get_sync(priv->dev);
if (err < 0) { if (err < 0) {
pm_runtime_put_noidle(priv->device); pm_runtime_put_noidle(priv->dev);
return err; return err;
} }
...@@ -644,7 +632,8 @@ static int m_can_clk_start(struct m_can_priv *priv) ...@@ -644,7 +632,8 @@ static int m_can_clk_start(struct m_can_priv *priv)
static void m_can_clk_stop(struct m_can_priv *priv) static void m_can_clk_stop(struct m_can_priv *priv)
{ {
pm_runtime_put_sync(priv->device); if (priv->pm_clock_support)
pm_runtime_put_sync(priv->dev);
} }
static int m_can_get_berr_counter(const struct net_device *dev, static int m_can_get_berr_counter(const struct net_device *dev,
...@@ -808,9 +797,8 @@ static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus, ...@@ -808,9 +797,8 @@ static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
return work_done; return work_done;
} }
static int m_can_poll(struct napi_struct *napi, int quota) static int m_can_rx_handler(struct net_device *dev, int quota)
{ {
struct net_device *dev = napi->dev;
struct m_can_priv *priv = netdev_priv(dev); struct m_can_priv *priv = netdev_priv(dev);
int work_done = 0; int work_done = 0;
u32 irqstatus, psr; u32 irqstatus, psr;
...@@ -849,13 +837,33 @@ static int m_can_poll(struct napi_struct *napi, int quota) ...@@ -849,13 +837,33 @@ static int m_can_poll(struct napi_struct *napi, int quota)
if (irqstatus & IR_RF0N) if (irqstatus & IR_RF0N)
work_done += m_can_do_rx_poll(dev, (quota - work_done)); work_done += m_can_do_rx_poll(dev, (quota - work_done));
end:
return work_done;
}
static int m_can_rx_peripheral(struct net_device *dev)
{
struct m_can_priv *priv = netdev_priv(dev);
m_can_rx_handler(dev, 1);
m_can_enable_all_interrupts(priv);
return 0;
}
static int m_can_poll(struct napi_struct *napi, int quota)
{
struct net_device *dev = napi->dev;
struct m_can_priv *priv = netdev_priv(dev);
int work_done;
work_done = m_can_rx_handler(dev, quota);
if (work_done < quota) { if (work_done < quota) {
napi_complete_done(napi, work_done); napi_complete_done(napi, work_done);
m_can_enable_all_interrupts(priv); m_can_enable_all_interrupts(priv);
} }
end:
return work_done; return work_done;
} }
...@@ -912,6 +920,9 @@ static irqreturn_t m_can_isr(int irq, void *dev_id) ...@@ -912,6 +920,9 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
if (ir & IR_ALL_INT) if (ir & IR_ALL_INT)
m_can_write(priv, M_CAN_IR, ir); m_can_write(priv, M_CAN_IR, ir);
if (priv->ops->clear_interrupts)
priv->ops->clear_interrupts(priv);
/* schedule NAPI in case of /* schedule NAPI in case of
* - rx IRQ * - rx IRQ
* - state change IRQ * - state change IRQ
...@@ -920,7 +931,10 @@ static irqreturn_t m_can_isr(int irq, void *dev_id) ...@@ -920,7 +931,10 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) { if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) {
priv->irqstatus = ir; priv->irqstatus = ir;
m_can_disable_all_interrupts(priv); m_can_disable_all_interrupts(priv);
napi_schedule(&priv->napi); if (!priv->is_peripheral)
napi_schedule(&priv->napi);
else
m_can_rx_peripheral(dev);
} }
if (priv->version == 30) { if (priv->version == 30) {
...@@ -1173,6 +1187,9 @@ static void m_can_chip_config(struct net_device *dev) ...@@ -1173,6 +1187,9 @@ static void m_can_chip_config(struct net_device *dev)
m_can_set_bittiming(dev); m_can_set_bittiming(dev);
m_can_config_endisable(priv, false); m_can_config_endisable(priv, false);
if (priv->ops->init)
priv->ops->init(priv);
} }
static void m_can_start(struct net_device *dev) static void m_can_start(struct net_device *dev)
...@@ -1191,6 +1208,7 @@ static int m_can_set_mode(struct net_device *dev, enum can_mode mode) ...@@ -1191,6 +1208,7 @@ static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
{ {
switch (mode) { switch (mode) {
case CAN_MODE_START: case CAN_MODE_START:
m_can_clean(dev);
m_can_start(dev); m_can_start(dev);
netif_wake_queue(dev); netif_wake_queue(dev);
break; break;
...@@ -1206,20 +1224,17 @@ static int m_can_set_mode(struct net_device *dev, enum can_mode mode) ...@@ -1206,20 +1224,17 @@ static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
* else it returns the release and step coded as: * else it returns the release and step coded as:
* return value = 10 * <release> + 1 * <step> * return value = 10 * <release> + 1 * <step>
*/ */
static int m_can_check_core_release(void __iomem *m_can_base) static int m_can_check_core_release(struct m_can_priv *priv)
{ {
u32 crel_reg; u32 crel_reg;
u8 rel; u8 rel;
u8 step; u8 step;
int res; int res;
struct m_can_priv temp_priv = {
.base = m_can_base
};
/* Read Core Release Version and split into version number /* Read Core Release Version and split into version number
* Example: Version 3.2.1 => rel = 3; step = 2; substep = 1; * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
*/ */
crel_reg = m_can_read(&temp_priv, M_CAN_CREL); crel_reg = m_can_read(priv, M_CAN_CREL);
rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT); rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT);
step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT); step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT);
...@@ -1237,18 +1252,26 @@ static int m_can_check_core_release(void __iomem *m_can_base) ...@@ -1237,18 +1252,26 @@ static int m_can_check_core_release(void __iomem *m_can_base)
/* Selectable Non ISO support only in version 3.2.x /* Selectable Non ISO support only in version 3.2.x
* This function checks if the bit is writable. * This function checks if the bit is writable.
*/ */
static bool m_can_niso_supported(const struct m_can_priv *priv) static bool m_can_niso_supported(struct m_can_priv *priv)
{ {
u32 cccr_reg, cccr_poll; u32 cccr_reg, cccr_poll = 0;
int niso_timeout; int niso_timeout = -ETIMEDOUT;
int i;
m_can_config_endisable(priv, true); m_can_config_endisable(priv, true);
cccr_reg = m_can_read(priv, M_CAN_CCCR); cccr_reg = m_can_read(priv, M_CAN_CCCR);
cccr_reg |= CCCR_NISO; cccr_reg |= CCCR_NISO;
m_can_write(priv, M_CAN_CCCR, cccr_reg); m_can_write(priv, M_CAN_CCCR, cccr_reg);
niso_timeout = readl_poll_timeout((priv->base + M_CAN_CCCR), cccr_poll, for (i = 0; i <= 10; i++) {
(cccr_poll == cccr_reg), 0, 10); cccr_poll = m_can_read(priv, M_CAN_CCCR);
if (cccr_poll == cccr_reg) {
niso_timeout = 0;
break;
}
usleep_range(1, 5);
}
/* Clear NISO */ /* Clear NISO */
cccr_reg &= ~(CCCR_NISO); cccr_reg &= ~(CCCR_NISO);
...@@ -1260,107 +1283,79 @@ static bool m_can_niso_supported(const struct m_can_priv *priv) ...@@ -1260,107 +1283,79 @@ static bool m_can_niso_supported(const struct m_can_priv *priv)
return !niso_timeout; return !niso_timeout;
} }
static int m_can_dev_setup(struct platform_device *pdev, struct net_device *dev, static int m_can_dev_setup(struct m_can_priv *m_can_dev)
void __iomem *addr)
{ {
struct m_can_priv *priv; struct net_device *dev = m_can_dev->net;
int m_can_version; int m_can_version;
m_can_version = m_can_check_core_release(addr); m_can_version = m_can_check_core_release(m_can_dev);
/* return if unsupported version */ /* return if unsupported version */
if (!m_can_version) { if (!m_can_version) {
dev_err(&pdev->dev, "Unsupported version number: %2d", dev_err(m_can_dev->dev, "Unsupported version number: %2d",
m_can_version); m_can_version);
return -EINVAL; return -EINVAL;
} }
priv = netdev_priv(dev); if (!m_can_dev->is_peripheral)
netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT); netif_napi_add(dev, &m_can_dev->napi,
m_can_poll, M_CAN_NAPI_WEIGHT);
/* Shared properties of all M_CAN versions */ /* Shared properties of all M_CAN versions */
priv->version = m_can_version; m_can_dev->version = m_can_version;
priv->dev = dev; m_can_dev->can.do_set_mode = m_can_set_mode;
priv->base = addr; m_can_dev->can.do_get_berr_counter = m_can_get_berr_counter;
priv->can.do_set_mode = m_can_set_mode;
priv->can.do_get_berr_counter = m_can_get_berr_counter;
/* Set M_CAN supported operations */ /* Set M_CAN supported operations */
priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | m_can_dev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_LISTENONLY |
CAN_CTRLMODE_BERR_REPORTING | CAN_CTRLMODE_BERR_REPORTING |
CAN_CTRLMODE_FD; CAN_CTRLMODE_FD;
/* Set properties depending on M_CAN version */ /* Set properties depending on M_CAN version */
switch (priv->version) { switch (m_can_dev->version) {
case 30: case 30:
/* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */ /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
priv->can.bittiming_const = &m_can_bittiming_const_30X; m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
priv->can.data_bittiming_const = m_can_dev->bit_timing : &m_can_bittiming_const_30X;
&m_can_data_bittiming_const_30X;
m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
m_can_dev->data_timing :
&m_can_data_bittiming_const_30X;
break; break;
case 31: case 31:
/* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */ /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
priv->can.bittiming_const = &m_can_bittiming_const_31X; m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
priv->can.data_bittiming_const = m_can_dev->bit_timing : &m_can_bittiming_const_31X;
&m_can_data_bittiming_const_31X;
m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
m_can_dev->data_timing :
&m_can_data_bittiming_const_31X;
break; break;
case 32: case 32:
priv->can.bittiming_const = &m_can_bittiming_const_31X; m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
priv->can.data_bittiming_const = m_can_dev->bit_timing : &m_can_bittiming_const_31X;
&m_can_data_bittiming_const_31X;
priv->can.ctrlmode_supported |= (m_can_niso_supported(priv) m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
m_can_dev->data_timing :
&m_can_data_bittiming_const_31X;
m_can_dev->can.ctrlmode_supported |=
(m_can_niso_supported(m_can_dev)
? CAN_CTRLMODE_FD_NON_ISO ? CAN_CTRLMODE_FD_NON_ISO
: 0); : 0);
break; break;
default: default:
dev_err(&pdev->dev, "Unsupported version number: %2d", dev_err(m_can_dev->dev, "Unsupported version number: %2d",
priv->version); m_can_dev->version);
return -EINVAL; return -EINVAL;
} }
return 0; if (m_can_dev->ops->init)
} m_can_dev->ops->init(m_can_dev);
static int m_can_open(struct net_device *dev)
{
struct m_can_priv *priv = netdev_priv(dev);
int err;
err = m_can_clk_start(priv);
if (err)
return err;
/* open the can device */
err = open_candev(dev);
if (err) {
netdev_err(dev, "failed to open can device\n");
goto exit_disable_clks;
}
/* register interrupt handler */
err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
dev);
if (err < 0) {
netdev_err(dev, "failed to request interrupt\n");
goto exit_irq_fail;
}
/* start the m_can controller */
m_can_start(dev);
can_led_event(dev, CAN_LED_EVENT_OPEN);
napi_enable(&priv->napi);
netif_start_queue(dev);
return 0; return 0;
exit_irq_fail:
close_candev(dev);
exit_disable_clks:
m_can_clk_stop(priv);
return err;
} }
static void m_can_stop(struct net_device *dev) static void m_can_stop(struct net_device *dev)
...@@ -1379,10 +1374,18 @@ static int m_can_close(struct net_device *dev) ...@@ -1379,10 +1374,18 @@ static int m_can_close(struct net_device *dev)
struct m_can_priv *priv = netdev_priv(dev); struct m_can_priv *priv = netdev_priv(dev);
netif_stop_queue(dev); netif_stop_queue(dev);
napi_disable(&priv->napi); if (!priv->is_peripheral)
napi_disable(&priv->napi);
m_can_stop(dev); m_can_stop(dev);
m_can_clk_stop(priv); m_can_clk_stop(priv);
free_irq(dev->irq, dev); free_irq(dev->irq, dev);
if (priv->is_peripheral) {
priv->tx_skb = NULL;
destroy_workqueue(priv->tx_wq);
priv->tx_wq = NULL;
}
close_candev(dev); close_candev(dev);
can_led_event(dev, CAN_LED_EVENT_STOP); can_led_event(dev, CAN_LED_EVENT_STOP);
...@@ -1403,18 +1406,15 @@ static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx) ...@@ -1403,18 +1406,15 @@ static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx)
return !!priv->can.echo_skb[next_idx]; return !!priv->can.echo_skb[next_idx];
} }
static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, static netdev_tx_t m_can_tx_handler(struct m_can_priv *priv)
struct net_device *dev)
{ {
struct m_can_priv *priv = netdev_priv(dev); struct canfd_frame *cf = (struct canfd_frame *)priv->tx_skb->data;
struct canfd_frame *cf = (struct canfd_frame *)skb->data; struct net_device *dev = priv->net;
struct sk_buff *skb = priv->tx_skb;
u32 id, cccr, fdflags; u32 id, cccr, fdflags;
int i; int i;
int putidx; int putidx;
if (can_dropped_invalid_skb(dev, skb))
return NETDEV_TX_OK;
/* Generate ID field for TX buffer Element */ /* Generate ID field for TX buffer Element */
/* Common to all supported M_CAN versions */ /* Common to all supported M_CAN versions */
if (cf->can_id & CAN_EFF_FLAG) { if (cf->can_id & CAN_EFF_FLAG) {
...@@ -1469,7 +1469,13 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, ...@@ -1469,7 +1469,13 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
netif_stop_queue(dev); netif_stop_queue(dev);
netdev_warn(dev, netdev_warn(dev,
"TX queue active although FIFO is full."); "TX queue active although FIFO is full.");
return NETDEV_TX_BUSY; if (priv->is_peripheral) {
kfree_skb(skb);
dev->stats.tx_dropped++;
return NETDEV_TX_OK;
} else {
return NETDEV_TX_BUSY;
}
} }
/* get put index for frame */ /* get put index for frame */
...@@ -1510,14 +1516,119 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, ...@@ -1510,14 +1516,119 @@ static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
m_can_write(priv, M_CAN_TXBAR, (1 << putidx)); m_can_write(priv, M_CAN_TXBAR, (1 << putidx));
/* stop network queue if fifo full */ /* stop network queue if fifo full */
if (m_can_tx_fifo_full(priv) || if (m_can_tx_fifo_full(priv) ||
m_can_next_echo_skb_occupied(dev, putidx)) m_can_next_echo_skb_occupied(dev, putidx))
netif_stop_queue(dev); netif_stop_queue(dev);
} }
return NETDEV_TX_OK; return NETDEV_TX_OK;
} }
static void m_can_tx_work_queue(struct work_struct *ws)
{
struct m_can_priv *priv = container_of(ws, struct m_can_priv,
tx_work);
m_can_tx_handler(priv);
priv->tx_skb = NULL;
}
static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
struct net_device *dev)
{
struct m_can_priv *priv = netdev_priv(dev);
if (can_dropped_invalid_skb(dev, skb))
return NETDEV_TX_OK;
if (priv->is_peripheral) {
if (priv->tx_skb) {
netdev_err(dev, "hard_xmit called while tx busy\n");
return NETDEV_TX_BUSY;
}
if (priv->can.state == CAN_STATE_BUS_OFF) {
m_can_clean(dev);
} else {
/* Need to stop the queue to avoid numerous requests
* from being sent. Suggested improvement is to create
* a queueing mechanism that will queue the skbs and
* process them in order.
*/
priv->tx_skb = skb;
netif_stop_queue(priv->net);
queue_work(priv->tx_wq, &priv->tx_work);
}
} else {
priv->tx_skb = skb;
return m_can_tx_handler(priv);
}
return NETDEV_TX_OK;
}
static int m_can_open(struct net_device *dev)
{
struct m_can_priv *priv = netdev_priv(dev);
int err;
err = m_can_clk_start(priv);
if (err)
return err;
/* open the can device */
err = open_candev(dev);
if (err) {
netdev_err(dev, "failed to open can device\n");
goto exit_disable_clks;
}
/* register interrupt handler */
if (priv->is_peripheral) {
priv->tx_skb = NULL;
priv->tx_wq = alloc_workqueue("mcan_wq",
WQ_FREEZABLE | WQ_MEM_RECLAIM, 0);
if (!priv->tx_wq) {
err = -ENOMEM;
goto out_wq_fail;
}
INIT_WORK(&priv->tx_work, m_can_tx_work_queue);
err = request_threaded_irq(dev->irq, NULL, m_can_isr,
IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
dev->name, dev);
} else {
err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
dev);
}
if (err < 0) {
netdev_err(dev, "failed to request interrupt\n");
goto exit_irq_fail;
}
/* start the m_can controller */
m_can_start(dev);
can_led_event(dev, CAN_LED_EVENT_OPEN);
if (!priv->is_peripheral)
napi_enable(&priv->napi);
netif_start_queue(dev);
return 0;
exit_irq_fail:
if (priv->is_peripheral)
destroy_workqueue(priv->tx_wq);
out_wq_fail:
close_candev(dev);
exit_disable_clks:
m_can_clk_stop(priv);
return err;
}
static const struct net_device_ops m_can_netdev_ops = { static const struct net_device_ops m_can_netdev_ops = {
.ndo_open = m_can_open, .ndo_open = m_can_open,
.ndo_stop = m_can_close, .ndo_stop = m_can_close,
...@@ -1533,20 +1644,6 @@ static int register_m_can_dev(struct net_device *dev) ...@@ -1533,20 +1644,6 @@ static int register_m_can_dev(struct net_device *dev)
return register_candev(dev); return register_candev(dev);
} }
static void m_can_init_ram(struct m_can_priv *priv)
{
int end, i, start;
/* initialize the entire Message RAM in use to avoid possible
* ECC/parity checksum errors when reading an uninitialized buffer
*/
start = priv->mcfg[MRAM_SIDF].off;
end = priv->mcfg[MRAM_TXB].off +
priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
for (i = start; i < end; i += 4)
writel(0x0, priv->mram_base + i);
}
static void m_can_of_parse_mram(struct m_can_priv *priv, static void m_can_of_parse_mram(struct m_can_priv *priv,
const u32 *mram_config_vals) const u32 *mram_config_vals)
{ {
...@@ -1574,9 +1671,8 @@ static void m_can_of_parse_mram(struct m_can_priv *priv, ...@@ -1574,9 +1671,8 @@ static void m_can_of_parse_mram(struct m_can_priv *priv,
priv->mcfg[MRAM_TXB].num = mram_config_vals[7] & priv->mcfg[MRAM_TXB].num = mram_config_vals[7] &
(TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT); (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
dev_dbg(priv->device, dev_dbg(priv->dev,
"mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n", "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
priv->mram_base,
priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num, priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num,
priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num, priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num,
priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num, priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num,
...@@ -1584,63 +1680,55 @@ static void m_can_of_parse_mram(struct m_can_priv *priv, ...@@ -1584,63 +1680,55 @@ static void m_can_of_parse_mram(struct m_can_priv *priv,
priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num, priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num,
priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num, priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num,
priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num); priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num);
m_can_init_ram(priv);
} }
static int m_can_plat_probe(struct platform_device *pdev) void m_can_init_ram(struct m_can_priv *priv)
{ {
struct net_device *dev; int end, i, start;
struct m_can_priv *priv;
struct resource *res;
void __iomem *addr;
void __iomem *mram_addr;
struct clk *hclk, *cclk;
int irq, ret;
struct device_node *np;
u32 mram_config_vals[MRAM_CFG_LEN];
u32 tx_fifo_size;
np = pdev->dev.of_node;
hclk = devm_clk_get(&pdev->dev, "hclk"); /* initialize the entire Message RAM in use to avoid possible
cclk = devm_clk_get(&pdev->dev, "cclk"); * ECC/parity checksum errors when reading an uninitialized buffer
*/
start = priv->mcfg[MRAM_SIDF].off;
end = priv->mcfg[MRAM_TXB].off +
priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
if (IS_ERR(hclk) || IS_ERR(cclk)) { for (i = start; i < end; i += 4)
dev_err(&pdev->dev, "no clock found\n"); m_can_fifo_write_no_off(priv, i, 0x0);
ret = -ENODEV; }
goto failed_ret; EXPORT_SYMBOL_GPL(m_can_init_ram);
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can"); int m_can_class_get_clocks(struct m_can_priv *m_can_dev)
addr = devm_ioremap_resource(&pdev->dev, res); {
irq = platform_get_irq_byname(pdev, "int0"); int ret = 0;
if (IS_ERR(addr) || irq < 0) { m_can_dev->hclk = devm_clk_get(m_can_dev->dev, "hclk");
ret = -EINVAL; m_can_dev->cclk = devm_clk_get(m_can_dev->dev, "cclk");
goto failed_ret;
}
/* message ram could be shared */ if (IS_ERR(m_can_dev->cclk)) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram"); dev_err(m_can_dev->dev, "no clock found\n");
if (!res) {
ret = -ENODEV; ret = -ENODEV;
goto failed_ret;
} }
mram_addr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); return ret;
if (!mram_addr) { }
ret = -ENOMEM; EXPORT_SYMBOL_GPL(m_can_class_get_clocks);
goto failed_ret;
}
/* get message ram configuration */ struct m_can_priv *m_can_class_allocate_dev(struct device *dev)
ret = of_property_read_u32_array(np, "bosch,mram-cfg", {
mram_config_vals, struct m_can_priv *class_dev = NULL;
sizeof(mram_config_vals) / 4); u32 mram_config_vals[MRAM_CFG_LEN];
struct net_device *net_dev;
u32 tx_fifo_size;
int ret;
ret = fwnode_property_read_u32_array(dev_fwnode(dev),
"bosch,mram-cfg",
mram_config_vals,
sizeof(mram_config_vals) / 4);
if (ret) { if (ret) {
dev_err(&pdev->dev, "Could not get Message RAM configuration."); dev_err(dev, "Could not get Message RAM configuration.");
goto failed_ret; goto out;
} }
/* Get TX FIFO size /* Get TX FIFO size
...@@ -1649,66 +1737,74 @@ static int m_can_plat_probe(struct platform_device *pdev) ...@@ -1649,66 +1737,74 @@ static int m_can_plat_probe(struct platform_device *pdev)
tx_fifo_size = mram_config_vals[7]; tx_fifo_size = mram_config_vals[7];
/* allocate the m_can device */ /* allocate the m_can device */
dev = alloc_candev(sizeof(*priv), tx_fifo_size); net_dev = alloc_candev(sizeof(*class_dev), tx_fifo_size);
if (!dev) { if (!net_dev) {
ret = -ENOMEM; dev_err(dev, "Failed to allocate CAN device");
goto failed_ret; goto out;
} }
priv = netdev_priv(dev); class_dev = netdev_priv(net_dev);
dev->irq = irq; if (!class_dev) {
priv->device = &pdev->dev; dev_err(dev, "Failed to init netdev private");
priv->hclk = hclk; goto out;
priv->cclk = cclk; }
priv->can.clock.freq = clk_get_rate(cclk);
priv->mram_base = mram_addr;
platform_set_drvdata(pdev, dev); class_dev->net = net_dev;
SET_NETDEV_DEV(dev, &pdev->dev); class_dev->dev = dev;
SET_NETDEV_DEV(net_dev, dev);
/* Enable clocks. Necessary to read Core Release in order to determine m_can_of_parse_mram(class_dev, mram_config_vals);
* M_CAN version out:
*/ return class_dev;
pm_runtime_enable(&pdev->dev); }
ret = m_can_clk_start(priv); EXPORT_SYMBOL_GPL(m_can_class_allocate_dev);
if (ret)
goto pm_runtime_fail; int m_can_class_register(struct m_can_priv *m_can_dev)
{
int ret;
ret = m_can_dev_setup(pdev, dev, addr); if (m_can_dev->pm_clock_support) {
pm_runtime_enable(m_can_dev->dev);
ret = m_can_clk_start(m_can_dev);
if (ret)
goto pm_runtime_fail;
}
ret = m_can_dev_setup(m_can_dev);
if (ret) if (ret)
goto clk_disable; goto clk_disable;
ret = register_m_can_dev(dev); ret = register_m_can_dev(m_can_dev->net);
if (ret) { if (ret) {
dev_err(&pdev->dev, "registering %s failed (err=%d)\n", dev_err(m_can_dev->dev, "registering %s failed (err=%d)\n",
KBUILD_MODNAME, ret); m_can_dev->net->name, ret);
goto clk_disable; goto clk_disable;
} }
m_can_of_parse_mram(priv, mram_config_vals); devm_can_led_init(m_can_dev->net);
devm_can_led_init(dev);
of_can_transceiver(dev); of_can_transceiver(m_can_dev->net);
dev_info(&pdev->dev, "%s device registered (irq=%d, version=%d)\n", dev_info(m_can_dev->dev, "%s device registered (irq=%d, version=%d)\n",
KBUILD_MODNAME, dev->irq, priv->version); KBUILD_MODNAME, m_can_dev->net->irq, m_can_dev->version);
/* Probe finished /* Probe finished
* Stop clocks. They will be reactivated once the M_CAN device is opened * Stop clocks. They will be reactivated once the M_CAN device is opened
*/ */
clk_disable: clk_disable:
m_can_clk_stop(priv); m_can_clk_stop(m_can_dev);
pm_runtime_fail: pm_runtime_fail:
if (ret) { if (ret) {
pm_runtime_disable(&pdev->dev); if (m_can_dev->pm_clock_support)
free_candev(dev); pm_runtime_disable(m_can_dev->dev);
free_candev(m_can_dev->net);
} }
failed_ret:
return ret; return ret;
} }
EXPORT_SYMBOL_GPL(m_can_class_register);
static __maybe_unused int m_can_suspend(struct device *dev) int m_can_class_suspend(struct device *dev)
{ {
struct net_device *ndev = dev_get_drvdata(dev); struct net_device *ndev = dev_get_drvdata(dev);
struct m_can_priv *priv = netdev_priv(ndev); struct m_can_priv *priv = netdev_priv(ndev);
...@@ -1726,8 +1822,9 @@ static __maybe_unused int m_can_suspend(struct device *dev) ...@@ -1726,8 +1822,9 @@ static __maybe_unused int m_can_suspend(struct device *dev)
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(m_can_class_suspend);
static __maybe_unused int m_can_resume(struct device *dev) int m_can_class_resume(struct device *dev)
{ {
struct net_device *ndev = dev_get_drvdata(dev); struct net_device *ndev = dev_get_drvdata(dev);
struct m_can_priv *priv = netdev_priv(ndev); struct m_can_priv *priv = netdev_priv(ndev);
...@@ -1751,79 +1848,19 @@ static __maybe_unused int m_can_resume(struct device *dev) ...@@ -1751,79 +1848,19 @@ static __maybe_unused int m_can_resume(struct device *dev)
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(m_can_class_resume);
static void unregister_m_can_dev(struct net_device *dev) void m_can_class_unregister(struct m_can_priv *m_can_dev)
{ {
unregister_candev(dev); unregister_candev(m_can_dev->net);
}
static int m_can_plat_remove(struct platform_device *pdev) m_can_clk_stop(m_can_dev);
{
struct net_device *dev = platform_get_drvdata(pdev);
unregister_m_can_dev(dev); free_candev(m_can_dev->net);
pm_runtime_disable(&pdev->dev);
platform_set_drvdata(pdev, NULL);
free_candev(dev);
return 0;
}
static int __maybe_unused m_can_runtime_suspend(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
struct m_can_priv *priv = netdev_priv(ndev);
clk_disable_unprepare(priv->cclk);
clk_disable_unprepare(priv->hclk);
return 0;
}
static int __maybe_unused m_can_runtime_resume(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
struct m_can_priv *priv = netdev_priv(ndev);
int err;
err = clk_prepare_enable(priv->hclk);
if (err)
return err;
err = clk_prepare_enable(priv->cclk);
if (err)
clk_disable_unprepare(priv->hclk);
return err;
} }
EXPORT_SYMBOL_GPL(m_can_class_unregister);
static const struct dev_pm_ops m_can_pmops = {
SET_RUNTIME_PM_OPS(m_can_runtime_suspend,
m_can_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume)
};
static const struct of_device_id m_can_of_table[] = {
{ .compatible = "bosch,m_can", .data = NULL },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, m_can_of_table);
static struct platform_driver m_can_plat_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = m_can_of_table,
.pm = &m_can_pmops,
},
.probe = m_can_plat_probe,
.remove = m_can_plat_remove,
};
module_platform_driver(m_can_plat_driver);
MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>"); MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller"); MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");
/* SPDX-License-Identifier: GPL-2.0 */
/* CAN bus driver for Bosch M_CAN controller
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*/
#ifndef _CAN_M_CAN_H_
#define _CAN_M_CAN_H_
#include <linux/can/core.h>
#include <linux/can/led.h>
#include <linux/completion.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/freezer.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/iopoll.h>
#include <linux/can/dev.h>
#include <linux/pinctrl/consumer.h>
/* m_can lec values */
enum m_can_lec_type {
LEC_NO_ERROR = 0,
LEC_STUFF_ERROR,
LEC_FORM_ERROR,
LEC_ACK_ERROR,
LEC_BIT1_ERROR,
LEC_BIT0_ERROR,
LEC_CRC_ERROR,
LEC_UNUSED,
};
enum m_can_mram_cfg {
MRAM_SIDF = 0,
MRAM_XIDF,
MRAM_RXF0,
MRAM_RXF1,
MRAM_RXB,
MRAM_TXE,
MRAM_TXB,
MRAM_CFG_NUM,
};
/* address offset and element number for each FIFO/Buffer in the Message RAM */
struct mram_cfg {
u16 off;
u8 num;
};
struct m_can_priv;
struct m_can_ops {
/* Device specific call backs */
int (*clear_interrupts)(struct m_can_priv *m_can_class);
u32 (*read_reg)(struct m_can_priv *m_can_class, int reg);
int (*write_reg)(struct m_can_priv *m_can_class, int reg, int val);
u32 (*read_fifo)(struct m_can_priv *m_can_class, int addr_offset);
int (*write_fifo)(struct m_can_priv *m_can_class, int addr_offset,
int val);
int (*init)(struct m_can_priv *m_can_class);
};
struct m_can_priv {
struct can_priv can;
struct napi_struct napi;
struct net_device *net;
struct device *dev;
struct clk *hclk;
struct clk *cclk;
struct workqueue_struct *tx_wq;
struct work_struct tx_work;
struct sk_buff *tx_skb;
struct can_bittiming_const *bit_timing;
struct can_bittiming_const *data_timing;
struct m_can_ops *ops;
void *device_data;
int version;
int freq;
u32 irqstatus;
int pm_clock_support;
int is_peripheral;
struct mram_cfg mcfg[MRAM_CFG_NUM];
};
struct m_can_priv *m_can_class_allocate_dev(struct device *dev);
int m_can_class_register(struct m_can_priv *m_can_dev);
void m_can_class_unregister(struct m_can_priv *m_can_dev);
int m_can_class_get_clocks(struct m_can_priv *m_can_dev);
void m_can_init_ram(struct m_can_priv *priv);
void m_can_config_endisable(struct m_can_priv *priv, bool enable);
int m_can_class_suspend(struct device *dev);
int m_can_class_resume(struct device *dev);
#endif /* _CAN_M_H_ */
// SPDX-License-Identifier: GPL-2.0
// IOMapped CAN bus driver for Bosch M_CAN controller
// Copyright (C) 2014 Freescale Semiconductor, Inc.
// Dong Aisheng <b29396@freescale.com>
//
// Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
#include <linux/platform_device.h>
#include "m_can.h"
struct m_can_plat_priv {
void __iomem *base;
void __iomem *mram_base;
};
static u32 iomap_read_reg(struct m_can_priv *cdev, int reg)
{
struct m_can_plat_priv *priv =
(struct m_can_plat_priv *)cdev->device_data;
return readl(priv->base + reg);
}
static u32 iomap_read_fifo(struct m_can_priv *cdev, int offset)
{
struct m_can_plat_priv *priv =
(struct m_can_plat_priv *)cdev->device_data;
return readl(priv->mram_base + offset);
}
static int iomap_write_reg(struct m_can_priv *cdev, int reg, int val)
{
struct m_can_plat_priv *priv =
(struct m_can_plat_priv *)cdev->device_data;
writel(val, priv->base + reg);
return 0;
}
static int iomap_write_fifo(struct m_can_priv *cdev, int offset, int val)
{
struct m_can_plat_priv *priv =
(struct m_can_plat_priv *)cdev->device_data;
writel(val, priv->mram_base + offset);
return 0;
}
static struct m_can_ops m_can_plat_ops = {
.read_reg = iomap_read_reg,
.write_reg = iomap_write_reg,
.write_fifo = iomap_write_fifo,
.read_fifo = iomap_read_fifo,
};
static int m_can_plat_probe(struct platform_device *pdev)
{
struct m_can_priv *mcan_class;
struct m_can_plat_priv *priv;
struct resource *res;
void __iomem *addr;
void __iomem *mram_addr;
int irq, ret = 0;
mcan_class = m_can_class_allocate_dev(&pdev->dev);
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
mcan_class->device_data = priv;
m_can_class_get_clocks(mcan_class);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can");
addr = devm_ioremap_resource(&pdev->dev, res);
irq = platform_get_irq_byname(pdev, "int0");
if (IS_ERR(addr) || irq < 0) {
ret = -EINVAL;
goto failed_ret;
}
/* message ram could be shared */
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
if (!res) {
ret = -ENODEV;
goto failed_ret;
}
mram_addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
if (!mram_addr) {
ret = -ENOMEM;
goto failed_ret;
}
priv->base = addr;
priv->mram_base = mram_addr;
mcan_class->net->irq = irq;
mcan_class->pm_clock_support = 1;
mcan_class->can.clock.freq = clk_get_rate(mcan_class->cclk);
mcan_class->dev = &pdev->dev;
mcan_class->ops = &m_can_plat_ops;
mcan_class->is_peripheral = false;
platform_set_drvdata(pdev, mcan_class->dev);
m_can_init_ram(mcan_class);
ret = m_can_class_register(mcan_class);
failed_ret:
return ret;
}
static __maybe_unused int m_can_suspend(struct device *dev)
{
return m_can_class_suspend(dev);
}
static __maybe_unused int m_can_resume(struct device *dev)
{
return m_can_class_resume(dev);
}
static int m_can_plat_remove(struct platform_device *pdev)
{
struct net_device *dev = platform_get_drvdata(pdev);
struct m_can_priv *mcan_class = netdev_priv(dev);
m_can_class_unregister(mcan_class);
platform_set_drvdata(pdev, NULL);
return 0;
}
static int __maybe_unused m_can_runtime_suspend(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
struct m_can_priv *mcan_class = netdev_priv(ndev);
m_can_class_suspend(dev);
clk_disable_unprepare(mcan_class->cclk);
clk_disable_unprepare(mcan_class->hclk);
return 0;
}
static int __maybe_unused m_can_runtime_resume(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
struct m_can_priv *mcan_class = netdev_priv(ndev);
int err;
err = clk_prepare_enable(mcan_class->hclk);
if (err)
return err;
err = clk_prepare_enable(mcan_class->cclk);
if (err)
clk_disable_unprepare(mcan_class->hclk);
m_can_class_resume(dev);
return err;
}
static const struct dev_pm_ops m_can_pmops = {
SET_RUNTIME_PM_OPS(m_can_runtime_suspend,
m_can_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume)
};
static const struct of_device_id m_can_of_table[] = {
{ .compatible = "bosch,m_can", .data = NULL },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, m_can_of_table);
static struct platform_driver m_can_plat_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = m_can_of_table,
.pm = &m_can_pmops,
},
.probe = m_can_plat_probe,
.remove = m_can_plat_remove,
};
module_platform_driver(m_can_plat_driver);
MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("M_CAN driver for IO Mapped Bosch controllers");
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