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Commit f58ec429 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'tegra-for-6.1-arm64-dt' of... 

Merge tag 'tegra-for-6.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v6.1-rc1

These changes enable PCI, Ethernet and HDA support on Jetson AGX Orin.
DMA support is enabled for I2C on a number of SoC generations and the
Google Pixel C (a.k.a. Smaug) device receives Bluetooth and Wi-Fi
support.

Other than that this also contains some minor cleanups and fixes.

* tag 'tegra-for-6.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Add GPCDMA support for Tegra I2C
  arm64: tegra: Add iommus for HDA on Tegra234
  arm64: tegra: Enable HDA node for Jetson AGX Orin
  arm64: tegra: Add context isolation domains on Tegra234
  arm64: tegra: Fixup iommu-map property formatting
  arm64: dts: tegra: smaug: Add Wi-Fi node
  arm64: dts: tegra: smaug: Add Bluetooth node
  arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit
  arm64: tegra: Add MGBE nodes on Tegra234
  arm64: tegra: Fix up compatible for Tegra234 GPCDMA
  arm64: tegra: Enable PCIe slots in P3737-0000 board
  arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT
  arm64: tegra: Add regulators required for PCIe

Link: https://lore.kernel.org/r/20220916101957.1635854-5-thierry.reding@gmail.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 195571f3 8e442805
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Showing with 1339 additions and 19 deletions
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View file @ f58ec429
......@@ -672,6 +672,10 @@ gen1_i2c: i2c@3160000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C1>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 21>, <&gpcdma 21>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -685,6 +689,10 @@ cam_i2c: i2c@3180000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C3>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 23>, <&gpcdma 23>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -702,6 +710,10 @@ dp_aux_ch1_i2c: i2c@3190000 {
pinctrl-names = "default", "idle";
pinctrl-0 = <&state_dpaux1_i2c>;
pinctrl-1 = <&state_dpaux1_off>;
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 26>, <&gpcdma 26>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -733,6 +745,10 @@ dp_aux_ch0_i2c: i2c@31b0000 {
pinctrl-names = "default", "idle";
pinctrl-0 = <&state_dpaux_i2c>;
pinctrl-1 = <&state_dpaux_off>;
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 30>, <&gpcdma 30>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -746,6 +762,10 @@ gen7_i2c: i2c@31c0000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C7>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 27>, <&gpcdma 27>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -759,6 +779,10 @@ gen9_i2c: i2c@31e0000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C9>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 31>, <&gpcdma 31>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -1176,6 +1200,10 @@ gen2_i2c: i2c@c240000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C2>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 22>, <&gpcdma 22>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -1189,6 +1217,10 @@ gen8_i2c: i2c@c250000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C8>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 0>, <&gpcdma 0>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -1485,15 +1517,14 @@ host1x@13e00000 {
iommus = <&smmu TEGRA186_SID_HOST1X>;
/* Context isolation domains */
iommu-map = <
0 &smmu TEGRA186_SID_HOST1X_CTX0 1
1 &smmu TEGRA186_SID_HOST1X_CTX1 1
2 &smmu TEGRA186_SID_HOST1X_CTX2 1
3 &smmu TEGRA186_SID_HOST1X_CTX3 1
4 &smmu TEGRA186_SID_HOST1X_CTX4 1
5 &smmu TEGRA186_SID_HOST1X_CTX5 1
6 &smmu TEGRA186_SID_HOST1X_CTX6 1
7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,
<1 &smmu TEGRA186_SID_HOST1X_CTX1 1>,
<2 &smmu TEGRA186_SID_HOST1X_CTX2 1>,
<3 &smmu TEGRA186_SID_HOST1X_CTX3 1>,
<4 &smmu TEGRA186_SID_HOST1X_CTX4 1>,
<5 &smmu TEGRA186_SID_HOST1X_CTX5 1>,
<6 &smmu TEGRA186_SID_HOST1X_CTX6 1>,
<7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
dpaux1: dpaux@15040000 {
compatible = "nvidia,tegra186-dpaux";
......
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View file @ f58ec429
......@@ -805,6 +805,10 @@ gen1_i2c: i2c@3160000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C1>;
reset-names = "i2c";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 21>, <&gpcdma 21>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -830,6 +834,10 @@ cam_i2c: i2c@3180000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C3>;
reset-names = "i2c";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 23>, <&gpcdma 23>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -847,6 +855,10 @@ dp_aux_ch1_i2c: i2c@3190000 {
pinctrl-0 = <&state_dpaux1_i2c>;
pinctrl-1 = <&state_dpaux1_off>;
pinctrl-names = "default", "idle";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 26>, <&gpcdma 26>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -864,6 +876,10 @@ dp_aux_ch0_i2c: i2c@31b0000 {
pinctrl-0 = <&state_dpaux0_i2c>;
pinctrl-1 = <&state_dpaux0_off>;
pinctrl-names = "default", "idle";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 30>, <&gpcdma 30>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -881,6 +897,10 @@ dp_aux_ch2_i2c: i2c@31c0000 {
pinctrl-0 = <&state_dpaux2_i2c>;
pinctrl-1 = <&state_dpaux2_off>;
pinctrl-names = "default", "idle";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 27>, <&gpcdma 27>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -898,6 +918,10 @@ dp_aux_ch3_i2c: i2c@31e0000 {
pinctrl-0 = <&state_dpaux3_i2c>;
pinctrl-1 = <&state_dpaux3_off>;
pinctrl-names = "default", "idle";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 31>, <&gpcdma 31>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -1565,6 +1589,10 @@ gen2_i2c: i2c@c240000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C2>;
reset-names = "i2c";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 22>, <&gpcdma 22>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -1578,6 +1606,10 @@ gen8_i2c: i2c@c250000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C8>;
reset-names = "i2c";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 0>, <&gpcdma 0>;
dma-names = "rx", "tx";
status = "disabled";
};
......@@ -1869,15 +1901,14 @@ host1x@13e00000 {
iommus = <&smmu TEGRA194_SID_HOST1X>;
/* Context isolation domains */
iommu-map = <
0 &smmu TEGRA194_SID_HOST1X_CTX0 1
1 &smmu TEGRA194_SID_HOST1X_CTX1 1
2 &smmu TEGRA194_SID_HOST1X_CTX2 1
3 &smmu TEGRA194_SID_HOST1X_CTX3 1
4 &smmu TEGRA194_SID_HOST1X_CTX4 1
5 &smmu TEGRA194_SID_HOST1X_CTX5 1
6 &smmu TEGRA194_SID_HOST1X_CTX6 1
7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;
iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>,
<1 &smmu TEGRA194_SID_HOST1X_CTX1 1>,
<2 &smmu TEGRA194_SID_HOST1X_CTX2 1>,
<3 &smmu TEGRA194_SID_HOST1X_CTX3 1>,
<4 &smmu TEGRA194_SID_HOST1X_CTX4 1>,
<5 &smmu TEGRA194_SID_HOST1X_CTX5 1>,
<6 &smmu TEGRA194_SID_HOST1X_CTX6 1>,
<7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;
nvdec@15140000 {
compatible = "nvidia,tegra194-nvdec";
......
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
View file @ f58ec429
......@@ -17,6 +17,7 @@ / {
aliases {
serial0 = &uarta;
serial3 = &uartd;
};
chosen {
......@@ -1309,6 +1310,22 @@ serial@70006000 {
status = "okay";
};
uartd: serial@70006300 {
compatible = "nvidia,tegra30-hsuart";
status = "okay";
bluetooth {
compatible = "brcm,bcm43540-bt";
max-speed = <4000000>;
brcm,bt-pcm-int-params = [01 02 00 01 01];
device-wakeup-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(H, 5) IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wakeup";
};
};
i2c@7000c400 {
status = "okay";
clock-frequency = <1000000>;
......@@ -1692,6 +1709,25 @@ usb3-0 {
};
};
mmc@700b0200 {
power-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
non-removable;
vqmmc-supply = <&pp1800>;
vmmc-supply = <&pp3300>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
wifi@1 {
compatible = "brcm,bcm4354-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(H, 2) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
};
};
mmc@700b0600 {
bus-width = <8>;
non-removable;
......
arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
View file @ f58ec429
......@@ -6,6 +6,42 @@ / {
model = "NVIDIA Jetson AGX Orin";
compatible = "nvidia,p3701-0000", "nvidia,tegra234";
vdd_1v8_ls: regulator-vdd-1v8-ls {
compatible = "regulator-fixed";
regulator-name = "VDD_1V8_LS";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vdd_1v8_ao: regulator-vdd-1v8-ao {
compatible = "regulator-fixed";
regulator-name = "VDD_1V8_AO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vdd_3v3_pcie: regulator-vdd-3v3-pcie {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3_PCIE";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio TEGRA234_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
regulator-boot-on;
enable-active-high;
};
vdd_12v_pcie: regulator-vdd-12v-pcie {
compatible = "regulator-fixed";
regulator-name = "VDD_12V_PCIE";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
regulator-boot-on;
enable-active-low;
};
bus@0 {
spi@3270000 {
status = "okay";
......
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
View file @ f58ec429
......@@ -2009,6 +2009,7 @@ serial@3100000 {
hda@3510000 {
nvidia,model = "NVIDIA Jetson AGX Orin HDA";
status = "okay";
};
};
......@@ -2017,6 +2018,27 @@ chosen {
stdout-path = "serial0:115200n8";
};
bus@0 {
ethernet@6800000 {
status = "okay";
phy-handle = <&mgbe0_phy>;
phy-mode = "usxgmii";
mdio {
#address-cells = <1>;
#size-cells = <0>;
mgbe0_phy: phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
#phy-cells = <0>;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
status = "okay";
......@@ -2111,4 +2133,55 @@ sound {
label = "NVIDIA Jetson AGX Orin APE";
};
pcie@14100000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_3>;
phy-names = "p2u-0";
};
pcie@14160000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
<&p2u_hsio_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
};
pcie@141a0000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
vpcie3v3-supply = <&vdd_3v3_pcie>;
vpcie12v-supply = <&vdd_12v_pcie>;
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
"p2u-5", "p2u-6", "p2u-7";
};
pcie-ep@141a0000 {
status = "disabled";
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
nvidia,refclk-select-gpios = <&gpio_aon
TEGRA234_AON_GPIO(AA, 4)
GPIO_ACTIVE_HIGH>;
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
"p2u-5", "p2u-6", "p2u-7";
};
};
arch/arm64/boot/dts/nvidia/tegra234.dtsi
View file @ f58ec429
......@@ -23,7 +23,6 @@ bus@0 {
gpcdma: dma-controller@2600000 {
compatible = "nvidia,tegra234-gpcdma",
"nvidia,tegra194-gpcdma",
"nvidia,tegra186-gpcdma";
reg = <0x2600000 0x210000>;
resets = <&bpmp TEGRA234_RESET_GPCDMA>;
......@@ -570,6 +569,24 @@ host1x@13e00000 {
interconnect-names = "dma-mem";
iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>;
/* Context isolation domains */
iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
<1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>,
<2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>,
<3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>,
<4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>,
<5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>,
<6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>,
<7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>,
<8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>,
<9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>,
<10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>,
<11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>,
<12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>,
<13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>,
<14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>,
<15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>;
vic@15340000 {
compatible = "nvidia,tegra234-vic";
reg = <0x15340000 0x00040000>;
......@@ -737,6 +754,10 @@ gen1_i2c: i2c@3160000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C1>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 21>, <&gpcdma 21>;
dma-names = "rx", "tx";
};
cam_i2c: i2c@3180000 {
......@@ -752,6 +773,10 @@ cam_i2c: i2c@3180000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C3>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 23>, <&gpcdma 23>;
dma-names = "rx", "tx";
};
dp_aux_ch1_i2c: i2c@3190000 {
......@@ -767,6 +792,10 @@ dp_aux_ch1_i2c: i2c@3190000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C4>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 26>, <&gpcdma 26>;
dma-names = "rx", "tx";
};
dp_aux_ch0_i2c: i2c@31b0000 {
......@@ -782,6 +811,10 @@ dp_aux_ch0_i2c: i2c@31b0000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C6>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 30>, <&gpcdma 30>;
dma-names = "rx", "tx";
};
dp_aux_ch2_i2c: i2c@31c0000 {
......@@ -797,6 +830,10 @@ dp_aux_ch2_i2c: i2c@31c0000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C7>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 27>, <&gpcdma 27>;
dma-names = "rx", "tx";
};
dp_aux_ch3_i2c: i2c@31e0000 {
......@@ -812,6 +849,10 @@ dp_aux_ch3_i2c: i2c@31e0000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C9>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 31>, <&gpcdma 31>;
dma-names = "rx", "tx";
};
spi@3270000 {
......@@ -897,6 +938,7 @@ hda@3510000 {
interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_HDA>;
status = "disabled";
};
......@@ -925,6 +967,142 @@ hsp_top0: hsp@3c00000 {
#mbox-cells = <2>;
};
ethernet@6800000 {
compatible = "nvidia,tegra234-mgbe";
reg = <0x06800000 0x10000>,
<0x06810000 0x10000>,
<0x068a0000 0x10000>;
reg-names = "hypervisor", "mac", "xpcs";
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
<&bpmp TEGRA234_CLK_MGBE0_MAC>,
<&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
<&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
<&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
<&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
<&bpmp TEGRA234_CLK_MGBE0_TX>,
<&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
<&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
"rx-pcs", "tx-pcs";
resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
<&bpmp TEGRA234_RESET_MGBE0_PCS>;
reset-names = "mac", "pcs";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
<&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
status = "disabled";
};
ethernet@6900000 {
compatible = "nvidia,tegra234-mgbe";
reg = <0x06900000 0x10000>,
<0x06910000 0x10000>,
<0x069a0000 0x10000>;
reg-names = "hypervisor", "mac", "xpcs";
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
<&bpmp TEGRA234_CLK_MGBE1_MAC>,
<&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
<&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
<&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
<&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
<&bpmp TEGRA234_CLK_MGBE1_TX>,
<&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
<&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
<&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
<&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
<&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
"rx-pcs", "tx-pcs";
resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
<&bpmp TEGRA234_RESET_MGBE1_PCS>;
reset-names = "mac", "pcs";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>,
<&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
status = "disabled";
};
ethernet@6a00000 {
compatible = "nvidia,tegra234-mgbe";
reg = <0x06a00000 0x10000>,
<0x06a10000 0x10000>,
<0x06aa0000 0x10000>;
reg-names = "hypervisor", "mac", "xpcs";
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
<&bpmp TEGRA234_CLK_MGBE2_MAC>,
<&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
<&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
<&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
<&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
<&bpmp TEGRA234_CLK_MGBE2_TX>,
<&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
<&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
<&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
<&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
<&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
"rx-pcs", "tx-pcs";
resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
<&bpmp TEGRA234_RESET_MGBE2_PCS>;
reset-names = "mac", "pcs";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>,
<&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
status = "disabled";
};
ethernet@6b00000 {
compatible = "nvidia,tegra234-mgbe";
reg = <0x06b00000 0x10000>,
<0x06b10000 0x10000>,
<0x06ba0000 0x10000>;
reg-names = "hypervisor", "mac", "xpcs";
interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
<&bpmp TEGRA234_CLK_MGBE3_MAC>,
<&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
<&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
<&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
<&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
<&bpmp TEGRA234_CLK_MGBE3_TX>,
<&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
<&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
<&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
<&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
<&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
"rx-pcs", "tx-pcs";
resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
<&bpmp TEGRA234_RESET_MGBE3_PCS>;
reset-names = "mac", "pcs";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>,
<&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>;
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
status = "disabled";
};
smmu_niso1: iommu@8000000 {
compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
reg = <0x8000000 0x1000000>,
......@@ -1081,6 +1259,198 @@ rce-fabric@be00000 {
status = "okay";
};
p2u_hsio_0: phy@3e00000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03e00000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_hsio_1: phy@3e10000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03e10000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_hsio_2: phy@3e20000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03e20000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_hsio_3: phy@3e30000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03e30000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_hsio_4: phy@3e40000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03e40000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_hsio_5: phy@3e50000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03e50000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_hsio_6: phy@3e60000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03e60000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_hsio_7: phy@3e70000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03e70000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_nvhs_0: phy@3e90000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03e90000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_nvhs_1: phy@3ea0000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03ea0000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_nvhs_2: phy@3eb0000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03eb0000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_nvhs_3: phy@3ec0000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03ec0000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_nvhs_4: phy@3ed0000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03ed0000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_nvhs_5: phy@3ee0000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03ee0000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_nvhs_6: phy@3ef0000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03ef0000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_nvhs_7: phy@3f00000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03f00000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_gbe_0: phy@3f20000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03f20000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_gbe_1: phy@3f30000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03f30000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_gbe_2: phy@3f40000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03f40000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_gbe_3: phy@3f50000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03f50000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_gbe_4: phy@3f60000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03f60000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_gbe_5: phy@3f70000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03f70000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_gbe_6: phy@3f80000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03f80000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
p2u_gbe_7: phy@3f90000 {
compatible = "nvidia,tegra234-p2u";
reg = <0x03f90000 0x10000>;
reg-names = "ctl";
#phy-cells = <0>;
};
hsp_aon: hsp@c150000 {
compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
reg = <0x0c150000 0x90000>;
......@@ -1109,6 +1479,10 @@ gen2_i2c: i2c@c240000 {
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
resets = <&bpmp TEGRA234_RESET_I2C2>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 22>, <&gpcdma 22>;
dma-names = "rx", "tx";
};
gen8_i2c: i2c@c250000 {
......@@ -1125,6 +1499,10 @@ gen8_i2c: i2c@c250000 {
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
resets = <&bpmp TEGRA234_RESET_I2C8>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 0>, <&gpcdma 0>;
dma-names = "rx", "tx";
};
rtc@c2a0000 {
......@@ -1495,6 +1873,741 @@ ccplex@e000000 {
status = "okay";
};
pcie@140a0000 {
compatible = "nvidia,tegra234-pcie";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
num-viewport = <8>;
linux,pci-domain = <8>;
clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>,
<&bpmp TEGRA234_RESET_PEX2_CORE_8>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
nvidia,bpmp = <&bpmp 8>;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
<0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
pcie@140c0000 {
compatible = "nvidia,tegra234-pcie";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
num-viewport = <8>;
linux,pci-domain = <9>;
clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>,
<&bpmp TEGRA234_RESET_PEX2_CORE_9>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
nvidia,bpmp = <&bpmp 9>;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
<0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
pcie@140e0000 {
compatible = "nvidia,tegra234-pcie";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
num-viewport = <8>;
linux,pci-domain = <10>;
clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
<&bpmp TEGRA234_RESET_PEX2_CORE_10>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
nvidia,bpmp = <&bpmp 10>;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
<0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
pcie@14100000 {
compatible = "nvidia,tegra234-pcie";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <1>;
num-viewport = <8>;
linux,pci-domain = <1>;
clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>,
<&bpmp TEGRA234_RESET_PEX0_CORE_1>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
nvidia,bpmp = <&bpmp 1>;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
<0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
pcie@14120000 {
compatible = "nvidia,tegra234-pcie";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <1>;
num-viewport = <8>;
linux,pci-domain = <2>;
clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>,
<&bpmp TEGRA234_RESET_PEX0_CORE_2>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
nvidia,bpmp = <&bpmp 2>;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
<0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
pcie@14140000 {
compatible = "nvidia,tegra234-pcie";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <1>;
num-viewport = <8>;
linux,pci-domain = <3>;
clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>,
<&bpmp TEGRA234_RESET_PEX0_CORE_3>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
nvidia,bpmp = <&bpmp 3>;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
<0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
pcie@14160000 {
compatible = "nvidia,tegra234-pcie";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
num-viewport = <8>;
linux,pci-domain = <4>;
clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
<&bpmp TEGRA234_RESET_PEX0_CORE_4>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
nvidia,bpmp = <&bpmp 4>;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
<0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
pcie@14180000 {
compatible = "nvidia,tegra234-pcie";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
num-viewport = <8>;
linux,pci-domain = <0>;
clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>,
<&bpmp TEGRA234_RESET_PEX0_CORE_0>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
nvidia,bpmp = <&bpmp 0>;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
<0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
pcie@141a0000 {
compatible = "nvidia,tegra234-pcie";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <8>;
num-viewport = <8>;
linux,pci-domain = <5>;
clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
<&bpmp TEGRA234_RESET_PEX1_CORE_5>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
nvidia,bpmp = <&bpmp 5>;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
ranges = <0x43000000 0x27 0x40000000 0x27 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */
<0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
pcie@141c0000 {
compatible = "nvidia,tegra234-pcie";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
num-viewport = <8>;
linux,pci-domain = <6>;
clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
<&bpmp TEGRA234_RESET_PEX1_CORE_6>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
nvidia,bpmp = <&bpmp 6>;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
<0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
pcie@141e0000 {
compatible = "nvidia,tegra234-pcie";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
<0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K) */
reg-names = "appl", "config", "atu_dma", "dbi";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <8>;
num-viewport = <8>;
linux,pci-domain = <7>;
clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
<&bpmp TEGRA234_RESET_PEX2_CORE_7>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
nvidia,bpmp = <&bpmp 7>;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
bus-range = <0x0 0xff>;
ranges = <0x43000000 0x2e 0x40000000 0x2e 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */
<0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
pcie-ep@141a0000 {
compatible = "nvidia,tegra234-pcie-ep";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
<0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
reg-names = "appl", "atu_dma", "dbi", "addr_space";
num-lanes = <8>;
clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
<&bpmp TEGRA234_RESET_PEX1_CORE_5>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "intr";
nvidia,bpmp = <&bpmp 5>;
nvidia,enable-ext-refclk;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
pcie-ep@141c0000{
compatible = "nvidia,tegra234-pcie-ep";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */
<0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
reg-names = "appl", "atu_dma", "dbi", "addr_space";
num-lanes = <4>;
clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
<&bpmp TEGRA234_RESET_PEX1_CORE_6>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "intr";
nvidia,bpmp = <&bpmp 6>;
nvidia,enable-ext-refclk;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
pcie-ep@141e0000{
compatible = "nvidia,tegra234-pcie-ep";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */
<0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
reg-names = "appl", "atu_dma", "dbi", "addr_space";
num-lanes = <8>;
clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
<&bpmp TEGRA234_RESET_PEX2_CORE_7>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "intr";
nvidia,bpmp = <&bpmp 7>;
nvidia,enable-ext-refclk;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
pcie-ep@140e0000{
compatible = "nvidia,tegra234-pcie-ep";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
<0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */
<0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
reg-names = "appl", "atu_dma", "dbi", "addr_space";
num-lanes = <4>;
clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
clock-names = "core";
resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
<&bpmp TEGRA234_RESET_PEX2_CORE_10>;
reset-names = "apb", "core";
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "intr";
nvidia,bpmp = <&bpmp 10>;
nvidia,enable-ext-refclk;
nvidia,aspm-cmrt-us = <60>;
nvidia,aspm-pwr-on-t-us = <20>;
nvidia,aspm-l0s-entrance-latency-us = <3>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
interconnect-names = "dma-mem", "write";
iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
iommu-map-mask = <0x0>;
dma-coherent;
status = "disabled";
};
sram@40000000 {
compatible = "nvidia,tegra234-sysram", "mmio-sram";
reg = <0x0 0x40000000 0x0 0x80000>;
......
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