Skip to content

L
linux
Commit f93bdefe authored by Alex Deucher's avatar Alex Deucher
Browse files
Options

drm/radeon: use callbacks for ring pointer handling (v3) 

Add callbacks to the radeon_asic struct to handle
rptr/wptr fetchs and wptr updates.
We currently use one version for all rings, but this
allows us to override with a ring specific versions.

Needed for compute rings on CIK.

v2: udpate as per Christian's comments
v3: fix some rebase cruft
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b556b12e
Hide whitespace changes
Inline Side-by-side
Showing with 182 additions and 14 deletions
drivers/gpu/drm/radeon/radeon.h
View file @ f93bdefe
...@@ -1285,6 +1285,10 @@ struct radeon_asic { ...@@ -1285,6 +1285,10 @@ struct radeon_asic {
int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
} ring[RADEON_NUM_RINGS]; } ring[RADEON_NUM_RINGS];
/* irqs */ /* irqs */
struct { struct {
...@@ -1962,6 +1966,9 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); ...@@ -1962,6 +1966,9 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
......
drivers/gpu/drm/radeon/radeon_asic.c
View file @ f93bdefe
...@@ -196,6 +196,9 @@ static struct radeon_asic r100_asic = { ...@@ -196,6 +196,9 @@ static struct radeon_asic r100_asic = {
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ib_test = &r100_ib_test, .ib_test = &r100_ib_test,
.is_lockup = &r100_gpu_is_lockup, .is_lockup = &r100_gpu_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -272,6 +275,9 @@ static struct radeon_asic r200_asic = { ...@@ -272,6 +275,9 @@ static struct radeon_asic r200_asic = {
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ib_test = &r100_ib_test, .ib_test = &r100_ib_test,
.is_lockup = &r100_gpu_is_lockup, .is_lockup = &r100_gpu_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -348,6 +354,9 @@ static struct radeon_asic r300_asic = { ...@@ -348,6 +354,9 @@ static struct radeon_asic r300_asic = {
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ib_test = &r100_ib_test, .ib_test = &r100_ib_test,
.is_lockup = &r100_gpu_is_lockup, .is_lockup = &r100_gpu_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -424,6 +433,9 @@ static struct radeon_asic r300_asic_pcie = { ...@@ -424,6 +433,9 @@ static struct radeon_asic r300_asic_pcie = {
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ib_test = &r100_ib_test, .ib_test = &r100_ib_test,
.is_lockup = &r100_gpu_is_lockup, .is_lockup = &r100_gpu_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -500,6 +512,9 @@ static struct radeon_asic r420_asic = { ...@@ -500,6 +512,9 @@ static struct radeon_asic r420_asic = {
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ib_test = &r100_ib_test, .ib_test = &r100_ib_test,
.is_lockup = &r100_gpu_is_lockup, .is_lockup = &r100_gpu_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -576,6 +591,9 @@ static struct radeon_asic rs400_asic = { ...@@ -576,6 +591,9 @@ static struct radeon_asic rs400_asic = {
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ib_test = &r100_ib_test, .ib_test = &r100_ib_test,
.is_lockup = &r100_gpu_is_lockup, .is_lockup = &r100_gpu_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -652,6 +670,9 @@ static struct radeon_asic rs600_asic = { ...@@ -652,6 +670,9 @@ static struct radeon_asic rs600_asic = {
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ib_test = &r100_ib_test, .ib_test = &r100_ib_test,
.is_lockup = &r100_gpu_is_lockup, .is_lockup = &r100_gpu_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -730,6 +751,9 @@ static struct radeon_asic rs690_asic = { ...@@ -730,6 +751,9 @@ static struct radeon_asic rs690_asic = {
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ib_test = &r100_ib_test, .ib_test = &r100_ib_test,
.is_lockup = &r100_gpu_is_lockup, .is_lockup = &r100_gpu_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -808,6 +832,9 @@ static struct radeon_asic rv515_asic = { ...@@ -808,6 +832,9 @@ static struct radeon_asic rv515_asic = {
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ib_test = &r100_ib_test, .ib_test = &r100_ib_test,
.is_lockup = &r100_gpu_is_lockup, .is_lockup = &r100_gpu_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -884,6 +911,9 @@ static struct radeon_asic r520_asic = { ...@@ -884,6 +911,9 @@ static struct radeon_asic r520_asic = {
.ring_test = &r100_ring_test, .ring_test = &r100_ring_test,
.ib_test = &r100_ib_test, .ib_test = &r100_ib_test,
.is_lockup = &r100_gpu_is_lockup, .is_lockup = &r100_gpu_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -961,6 +991,9 @@ static struct radeon_asic r600_asic = { ...@@ -961,6 +991,9 @@ static struct radeon_asic r600_asic = {
.ring_test = &r600_ring_test, .ring_test = &r600_ring_test,
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &r600_gfx_is_lockup, .is_lockup = &r600_gfx_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_DMA_INDEX] = { [R600_RING_TYPE_DMA_INDEX] = {
.ib_execute = &r600_dma_ring_ib_execute, .ib_execute = &r600_dma_ring_ib_execute,
...@@ -970,6 +1003,9 @@ static struct radeon_asic r600_asic = { ...@@ -970,6 +1003,9 @@ static struct radeon_asic r600_asic = {
.ring_test = &r600_dma_ring_test, .ring_test = &r600_dma_ring_test,
.ib_test = &r600_dma_ib_test, .ib_test = &r600_dma_ib_test,
.is_lockup = &r600_dma_is_lockup, .is_lockup = &r600_dma_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -1049,6 +1085,9 @@ static struct radeon_asic rs780_asic = { ...@@ -1049,6 +1085,9 @@ static struct radeon_asic rs780_asic = {
.ring_test = &r600_ring_test, .ring_test = &r600_ring_test,
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &r600_gfx_is_lockup, .is_lockup = &r600_gfx_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_DMA_INDEX] = { [R600_RING_TYPE_DMA_INDEX] = {
.ib_execute = &r600_dma_ring_ib_execute, .ib_execute = &r600_dma_ring_ib_execute,
...@@ -1058,6 +1097,9 @@ static struct radeon_asic rs780_asic = { ...@@ -1058,6 +1097,9 @@ static struct radeon_asic rs780_asic = {
.ring_test = &r600_dma_ring_test, .ring_test = &r600_dma_ring_test,
.ib_test = &r600_dma_ib_test, .ib_test = &r600_dma_ib_test,
.is_lockup = &r600_dma_is_lockup, .is_lockup = &r600_dma_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -1137,6 +1179,9 @@ static struct radeon_asic rv770_asic = { ...@@ -1137,6 +1179,9 @@ static struct radeon_asic rv770_asic = {
.ring_test = &r600_ring_test, .ring_test = &r600_ring_test,
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &r600_gfx_is_lockup, .is_lockup = &r600_gfx_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_DMA_INDEX] = { [R600_RING_TYPE_DMA_INDEX] = {
.ib_execute = &r600_dma_ring_ib_execute, .ib_execute = &r600_dma_ring_ib_execute,
...@@ -1146,6 +1191,9 @@ static struct radeon_asic rv770_asic = { ...@@ -1146,6 +1191,9 @@ static struct radeon_asic rv770_asic = {
.ring_test = &r600_dma_ring_test, .ring_test = &r600_dma_ring_test,
.ib_test = &r600_dma_ib_test, .ib_test = &r600_dma_ib_test,
.is_lockup = &r600_dma_is_lockup, .is_lockup = &r600_dma_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_UVD_INDEX] = { [R600_RING_TYPE_UVD_INDEX] = {
.ib_execute = &r600_uvd_ib_execute, .ib_execute = &r600_uvd_ib_execute,
...@@ -1155,6 +1203,9 @@ static struct radeon_asic rv770_asic = { ...@@ -1155,6 +1203,9 @@ static struct radeon_asic rv770_asic = {
.ring_test = &r600_uvd_ring_test, .ring_test = &r600_uvd_ring_test,
.ib_test = &r600_uvd_ib_test, .ib_test = &r600_uvd_ib_test,
.is_lockup = &radeon_ring_test_lockup, .is_lockup = &radeon_ring_test_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -1235,6 +1286,9 @@ static struct radeon_asic evergreen_asic = { ...@@ -1235,6 +1286,9 @@ static struct radeon_asic evergreen_asic = {
.ring_test = &r600_ring_test, .ring_test = &r600_ring_test,
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &evergreen_gfx_is_lockup, .is_lockup = &evergreen_gfx_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_DMA_INDEX] = { [R600_RING_TYPE_DMA_INDEX] = {
.ib_execute = &evergreen_dma_ring_ib_execute, .ib_execute = &evergreen_dma_ring_ib_execute,
...@@ -1244,6 +1298,9 @@ static struct radeon_asic evergreen_asic = { ...@@ -1244,6 +1298,9 @@ static struct radeon_asic evergreen_asic = {
.ring_test = &r600_dma_ring_test, .ring_test = &r600_dma_ring_test,
.ib_test = &r600_dma_ib_test, .ib_test = &r600_dma_ib_test,
.is_lockup = &evergreen_dma_is_lockup, .is_lockup = &evergreen_dma_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_UVD_INDEX] = { [R600_RING_TYPE_UVD_INDEX] = {
.ib_execute = &r600_uvd_ib_execute, .ib_execute = &r600_uvd_ib_execute,
...@@ -1253,6 +1310,9 @@ static struct radeon_asic evergreen_asic = { ...@@ -1253,6 +1310,9 @@ static struct radeon_asic evergreen_asic = {
.ring_test = &r600_uvd_ring_test, .ring_test = &r600_uvd_ring_test,
.ib_test = &r600_uvd_ib_test, .ib_test = &r600_uvd_ib_test,
.is_lockup = &radeon_ring_test_lockup, .is_lockup = &radeon_ring_test_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -1333,6 +1393,9 @@ static struct radeon_asic sumo_asic = { ...@@ -1333,6 +1393,9 @@ static struct radeon_asic sumo_asic = {
.ring_test = &r600_ring_test, .ring_test = &r600_ring_test,
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &evergreen_gfx_is_lockup, .is_lockup = &evergreen_gfx_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_DMA_INDEX] = { [R600_RING_TYPE_DMA_INDEX] = {
.ib_execute = &evergreen_dma_ring_ib_execute, .ib_execute = &evergreen_dma_ring_ib_execute,
...@@ -1342,6 +1405,9 @@ static struct radeon_asic sumo_asic = { ...@@ -1342,6 +1405,9 @@ static struct radeon_asic sumo_asic = {
.ring_test = &r600_dma_ring_test, .ring_test = &r600_dma_ring_test,
.ib_test = &r600_dma_ib_test, .ib_test = &r600_dma_ib_test,
.is_lockup = &evergreen_dma_is_lockup, .is_lockup = &evergreen_dma_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_UVD_INDEX] = { [R600_RING_TYPE_UVD_INDEX] = {
.ib_execute = &r600_uvd_ib_execute, .ib_execute = &r600_uvd_ib_execute,
...@@ -1351,6 +1417,9 @@ static struct radeon_asic sumo_asic = { ...@@ -1351,6 +1417,9 @@ static struct radeon_asic sumo_asic = {
.ring_test = &r600_uvd_ring_test, .ring_test = &r600_uvd_ring_test,
.ib_test = &r600_uvd_ib_test, .ib_test = &r600_uvd_ib_test,
.is_lockup = &radeon_ring_test_lockup, .is_lockup = &radeon_ring_test_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -1431,6 +1500,9 @@ static struct radeon_asic btc_asic = { ...@@ -1431,6 +1500,9 @@ static struct radeon_asic btc_asic = {
.ring_test = &r600_ring_test, .ring_test = &r600_ring_test,
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &evergreen_gfx_is_lockup, .is_lockup = &evergreen_gfx_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_DMA_INDEX] = { [R600_RING_TYPE_DMA_INDEX] = {
.ib_execute = &evergreen_dma_ring_ib_execute, .ib_execute = &evergreen_dma_ring_ib_execute,
...@@ -1440,6 +1512,9 @@ static struct radeon_asic btc_asic = { ...@@ -1440,6 +1512,9 @@ static struct radeon_asic btc_asic = {
.ring_test = &r600_dma_ring_test, .ring_test = &r600_dma_ring_test,
.ib_test = &r600_dma_ib_test, .ib_test = &r600_dma_ib_test,
.is_lockup = &evergreen_dma_is_lockup, .is_lockup = &evergreen_dma_is_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_UVD_INDEX] = { [R600_RING_TYPE_UVD_INDEX] = {
.ib_execute = &r600_uvd_ib_execute, .ib_execute = &r600_uvd_ib_execute,
...@@ -1449,6 +1524,9 @@ static struct radeon_asic btc_asic = { ...@@ -1449,6 +1524,9 @@ static struct radeon_asic btc_asic = {
.ring_test = &r600_uvd_ring_test, .ring_test = &r600_uvd_ring_test,
.ib_test = &r600_uvd_ib_test, .ib_test = &r600_uvd_ib_test,
.is_lockup = &radeon_ring_test_lockup, .is_lockup = &radeon_ring_test_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -1537,6 +1615,9 @@ static struct radeon_asic cayman_asic = { ...@@ -1537,6 +1615,9 @@ static struct radeon_asic cayman_asic = {
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &cayman_gfx_is_lockup, .is_lockup = &cayman_gfx_is_lockup,
.vm_flush = &cayman_vm_flush, .vm_flush = &cayman_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[CAYMAN_RING_TYPE_CP1_INDEX] = { [CAYMAN_RING_TYPE_CP1_INDEX] = {
.ib_execute = &cayman_ring_ib_execute, .ib_execute = &cayman_ring_ib_execute,
...@@ -1548,6 +1629,9 @@ static struct radeon_asic cayman_asic = { ...@@ -1548,6 +1629,9 @@ static struct radeon_asic cayman_asic = {
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &cayman_gfx_is_lockup, .is_lockup = &cayman_gfx_is_lockup,
.vm_flush = &cayman_vm_flush, .vm_flush = &cayman_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[CAYMAN_RING_TYPE_CP2_INDEX] = { [CAYMAN_RING_TYPE_CP2_INDEX] = {
.ib_execute = &cayman_ring_ib_execute, .ib_execute = &cayman_ring_ib_execute,
...@@ -1559,6 +1643,9 @@ static struct radeon_asic cayman_asic = { ...@@ -1559,6 +1643,9 @@ static struct radeon_asic cayman_asic = {
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &cayman_gfx_is_lockup, .is_lockup = &cayman_gfx_is_lockup,
.vm_flush = &cayman_vm_flush, .vm_flush = &cayman_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_DMA_INDEX] = { [R600_RING_TYPE_DMA_INDEX] = {
.ib_execute = &cayman_dma_ring_ib_execute, .ib_execute = &cayman_dma_ring_ib_execute,
...@@ -1570,6 +1657,9 @@ static struct radeon_asic cayman_asic = { ...@@ -1570,6 +1657,9 @@ static struct radeon_asic cayman_asic = {
.ib_test = &r600_dma_ib_test, .ib_test = &r600_dma_ib_test,
.is_lockup = &cayman_dma_is_lockup, .is_lockup = &cayman_dma_is_lockup,
.vm_flush = &cayman_dma_vm_flush, .vm_flush = &cayman_dma_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[CAYMAN_RING_TYPE_DMA1_INDEX] = { [CAYMAN_RING_TYPE_DMA1_INDEX] = {
.ib_execute = &cayman_dma_ring_ib_execute, .ib_execute = &cayman_dma_ring_ib_execute,
...@@ -1581,6 +1671,9 @@ static struct radeon_asic cayman_asic = { ...@@ -1581,6 +1671,9 @@ static struct radeon_asic cayman_asic = {
.ib_test = &r600_dma_ib_test, .ib_test = &r600_dma_ib_test,
.is_lockup = &cayman_dma_is_lockup, .is_lockup = &cayman_dma_is_lockup,
.vm_flush = &cayman_dma_vm_flush, .vm_flush = &cayman_dma_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_UVD_INDEX] = { [R600_RING_TYPE_UVD_INDEX] = {
.ib_execute = &r600_uvd_ib_execute, .ib_execute = &r600_uvd_ib_execute,
...@@ -1590,6 +1683,9 @@ static struct radeon_asic cayman_asic = { ...@@ -1590,6 +1683,9 @@ static struct radeon_asic cayman_asic = {
.ring_test = &r600_uvd_ring_test, .ring_test = &r600_uvd_ring_test,
.ib_test = &r600_uvd_ib_test, .ib_test = &r600_uvd_ib_test,
.is_lockup = &radeon_ring_test_lockup, .is_lockup = &radeon_ring_test_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -1678,6 +1774,9 @@ static struct radeon_asic trinity_asic = { ...@@ -1678,6 +1774,9 @@ static struct radeon_asic trinity_asic = {
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &cayman_gfx_is_lockup, .is_lockup = &cayman_gfx_is_lockup,
.vm_flush = &cayman_vm_flush, .vm_flush = &cayman_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[CAYMAN_RING_TYPE_CP1_INDEX] = { [CAYMAN_RING_TYPE_CP1_INDEX] = {
.ib_execute = &cayman_ring_ib_execute, .ib_execute = &cayman_ring_ib_execute,
...@@ -1689,6 +1788,9 @@ static struct radeon_asic trinity_asic = { ...@@ -1689,6 +1788,9 @@ static struct radeon_asic trinity_asic = {
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &cayman_gfx_is_lockup, .is_lockup = &cayman_gfx_is_lockup,
.vm_flush = &cayman_vm_flush, .vm_flush = &cayman_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[CAYMAN_RING_TYPE_CP2_INDEX] = { [CAYMAN_RING_TYPE_CP2_INDEX] = {
.ib_execute = &cayman_ring_ib_execute, .ib_execute = &cayman_ring_ib_execute,
...@@ -1700,6 +1802,9 @@ static struct radeon_asic trinity_asic = { ...@@ -1700,6 +1802,9 @@ static struct radeon_asic trinity_asic = {
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &cayman_gfx_is_lockup, .is_lockup = &cayman_gfx_is_lockup,
.vm_flush = &cayman_vm_flush, .vm_flush = &cayman_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_DMA_INDEX] = { [R600_RING_TYPE_DMA_INDEX] = {
.ib_execute = &cayman_dma_ring_ib_execute, .ib_execute = &cayman_dma_ring_ib_execute,
...@@ -1711,6 +1816,9 @@ static struct radeon_asic trinity_asic = { ...@@ -1711,6 +1816,9 @@ static struct radeon_asic trinity_asic = {
.ib_test = &r600_dma_ib_test, .ib_test = &r600_dma_ib_test,
.is_lockup = &cayman_dma_is_lockup, .is_lockup = &cayman_dma_is_lockup,
.vm_flush = &cayman_dma_vm_flush, .vm_flush = &cayman_dma_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[CAYMAN_RING_TYPE_DMA1_INDEX] = { [CAYMAN_RING_TYPE_DMA1_INDEX] = {
.ib_execute = &cayman_dma_ring_ib_execute, .ib_execute = &cayman_dma_ring_ib_execute,
...@@ -1722,6 +1830,9 @@ static struct radeon_asic trinity_asic = { ...@@ -1722,6 +1830,9 @@ static struct radeon_asic trinity_asic = {
.ib_test = &r600_dma_ib_test, .ib_test = &r600_dma_ib_test,
.is_lockup = &cayman_dma_is_lockup, .is_lockup = &cayman_dma_is_lockup,
.vm_flush = &cayman_dma_vm_flush, .vm_flush = &cayman_dma_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_UVD_INDEX] = { [R600_RING_TYPE_UVD_INDEX] = {
.ib_execute = &r600_uvd_ib_execute, .ib_execute = &r600_uvd_ib_execute,
...@@ -1731,6 +1842,9 @@ static struct radeon_asic trinity_asic = { ...@@ -1731,6 +1842,9 @@ static struct radeon_asic trinity_asic = {
.ring_test = &r600_uvd_ring_test, .ring_test = &r600_uvd_ring_test,
.ib_test = &r600_uvd_ib_test, .ib_test = &r600_uvd_ib_test,
.is_lockup = &radeon_ring_test_lockup, .is_lockup = &radeon_ring_test_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
...@@ -1817,6 +1931,9 @@ static struct radeon_asic si_asic = { ...@@ -1817,6 +1931,9 @@ static struct radeon_asic si_asic = {
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &si_gfx_is_lockup, .is_lockup = &si_gfx_is_lockup,
.vm_flush = &si_vm_flush, .vm_flush = &si_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[CAYMAN_RING_TYPE_CP1_INDEX] = { [CAYMAN_RING_TYPE_CP1_INDEX] = {
.ib_execute = &si_ring_ib_execute, .ib_execute = &si_ring_ib_execute,
...@@ -1828,6 +1945,9 @@ static struct radeon_asic si_asic = { ...@@ -1828,6 +1945,9 @@ static struct radeon_asic si_asic = {
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &si_gfx_is_lockup, .is_lockup = &si_gfx_is_lockup,
.vm_flush = &si_vm_flush, .vm_flush = &si_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[CAYMAN_RING_TYPE_CP2_INDEX] = { [CAYMAN_RING_TYPE_CP2_INDEX] = {
.ib_execute = &si_ring_ib_execute, .ib_execute = &si_ring_ib_execute,
...@@ -1839,6 +1959,9 @@ static struct radeon_asic si_asic = { ...@@ -1839,6 +1959,9 @@ static struct radeon_asic si_asic = {
.ib_test = &r600_ib_test, .ib_test = &r600_ib_test,
.is_lockup = &si_gfx_is_lockup, .is_lockup = &si_gfx_is_lockup,
.vm_flush = &si_vm_flush, .vm_flush = &si_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_DMA_INDEX] = { [R600_RING_TYPE_DMA_INDEX] = {
.ib_execute = &cayman_dma_ring_ib_execute, .ib_execute = &cayman_dma_ring_ib_execute,
...@@ -1850,6 +1973,9 @@ static struct radeon_asic si_asic = { ...@@ -1850,6 +1973,9 @@ static struct radeon_asic si_asic = {
.ib_test = &r600_dma_ib_test, .ib_test = &r600_dma_ib_test,
.is_lockup = &si_dma_is_lockup, .is_lockup = &si_dma_is_lockup,
.vm_flush = &si_dma_vm_flush, .vm_flush = &si_dma_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[CAYMAN_RING_TYPE_DMA1_INDEX] = { [CAYMAN_RING_TYPE_DMA1_INDEX] = {
.ib_execute = &cayman_dma_ring_ib_execute, .ib_execute = &cayman_dma_ring_ib_execute,
...@@ -1861,6 +1987,9 @@ static struct radeon_asic si_asic = { ...@@ -1861,6 +1987,9 @@ static struct radeon_asic si_asic = {
.ib_test = &r600_dma_ib_test, .ib_test = &r600_dma_ib_test,
.is_lockup = &si_dma_is_lockup, .is_lockup = &si_dma_is_lockup,
.vm_flush = &si_dma_vm_flush, .vm_flush = &si_dma_vm_flush,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
}, },
[R600_RING_TYPE_UVD_INDEX] = { [R600_RING_TYPE_UVD_INDEX] = {
.ib_execute = &r600_uvd_ib_execute, .ib_execute = &r600_uvd_ib_execute,
...@@ -1870,6 +1999,9 @@ static struct radeon_asic si_asic = { ...@@ -1870,6 +1999,9 @@ static struct radeon_asic si_asic = {
.ring_test = &r600_uvd_ring_test, .ring_test = &r600_uvd_ring_test,
.ib_test = &r600_uvd_ib_test, .ib_test = &r600_uvd_ib_test,
.is_lockup = &radeon_ring_test_lockup, .is_lockup = &radeon_ring_test_lockup,
.get_rptr = &radeon_ring_generic_get_rptr,
.get_wptr = &radeon_ring_generic_get_wptr,
.set_wptr = &radeon_ring_generic_set_wptr,
} }
}, },
.irq = { .irq = {
......
drivers/gpu/drm/radeon/radeon_asic.h
View file @ f93bdefe
...@@ -47,6 +47,12 @@ u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); ...@@ -47,6 +47,12 @@ u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
struct radeon_ring *ring);
u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
struct radeon_ring *ring);
void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
struct radeon_ring *ring);
/* /*
* r100,rv100,rs100,rv200,rs200 * r100,rv100,rs100,rv200,rs200
......
drivers/gpu/drm/radeon/radeon_ring.c
View file @ f93bdefe
...@@ -357,6 +357,38 @@ bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, ...@@ -357,6 +357,38 @@ bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
} }
} }
u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
struct radeon_ring *ring)
{
u32 rptr;
if (rdev->wb.enabled && ring != &rdev->ring[R600_RING_TYPE_UVD_INDEX])
rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
else
rptr = RREG32(ring->rptr_reg);
rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
return rptr;
}
u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
struct radeon_ring *ring)
{
u32 wptr;
wptr = RREG32(ring->wptr_reg);
wptr = (wptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
return wptr;
}
void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
struct radeon_ring *ring)
{
WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
(void)RREG32(ring->wptr_reg);
}
/** /**
* radeon_ring_free_size - update the free size * radeon_ring_free_size - update the free size
* *
...@@ -367,13 +399,7 @@ bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, ...@@ -367,13 +399,7 @@ bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
*/ */
void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
{ {
u32 rptr; ring->rptr = radeon_ring_get_rptr(rdev, ring);
if (rdev->wb.enabled && ring != &rdev->ring[R600_RING_TYPE_UVD_INDEX])
rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
else
rptr = RREG32(ring->rptr_reg);
ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
/* This works because ring_size is a power of 2 */ /* This works because ring_size is a power of 2 */
ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
ring->ring_free_dw -= ring->wptr; ring->ring_free_dw -= ring->wptr;
...@@ -458,8 +484,7 @@ void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) ...@@ -458,8 +484,7 @@ void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
radeon_ring_write(ring, ring->nop); radeon_ring_write(ring, ring->nop);
} }
DRM_MEMORYBARRIER(); DRM_MEMORYBARRIER();
WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); radeon_ring_set_wptr(rdev, ring);
(void)RREG32(ring->wptr_reg);
} }
/** /**
...@@ -561,7 +586,6 @@ void radeon_ring_lockup_update(struct radeon_ring *ring) ...@@ -561,7 +586,6 @@ void radeon_ring_lockup_update(struct radeon_ring *ring)
bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
{ {
unsigned long cjiffies, elapsed; unsigned long cjiffies, elapsed;
uint32_t rptr;
cjiffies = jiffies; cjiffies = jiffies;
if (!time_after(cjiffies, ring->last_activity)) { if (!time_after(cjiffies, ring->last_activity)) {
...@@ -569,8 +593,7 @@ bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *rin ...@@ -569,8 +593,7 @@ bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *rin
radeon_ring_lockup_update(ring); radeon_ring_lockup_update(ring);
return false; return false;
} }
rptr = RREG32(ring->rptr_reg); ring->rptr = radeon_ring_get_rptr(rdev, ring);
ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
if (ring->rptr != ring->last_rptr) { if (ring->rptr != ring->last_rptr) {
/* CP is still working no lockup */ /* CP is still working no lockup */
radeon_ring_lockup_update(ring); radeon_ring_lockup_update(ring);
...@@ -797,9 +820,9 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data) ...@@ -797,9 +820,9 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
radeon_ring_free_size(rdev, ring); radeon_ring_free_size(rdev, ring);
count = (ring->ring_size / 4) - ring->ring_free_dw; count = (ring->ring_size / 4) - ring->ring_free_dw;
tmp = RREG32(ring->wptr_reg) >> ring->ptr_reg_shift; tmp = radeon_ring_get_wptr(rdev, ring);
seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp); seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp);
tmp = RREG32(ring->rptr_reg) >> ring->ptr_reg_shift; tmp = radeon_ring_get_rptr(rdev, ring);
seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp); seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp);
if (ring->rptr_save_reg) { if (ring->rptr_save_reg) {
seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg, seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7