Commit fa416ddc authored by Lucas Stach's avatar Lucas Stach Committed by Dave Airlie

drm: tegra: remove redundant tegra2_tmds_config entry

The 720p and 1080p entries are completely redundant, as we are matching
the table entries against <=pclk.
Also generalize the comment, as we are using those table entries even
when driving other modes than the standard TV ones.
Signed-off-by: default avatarLucas Stach <dev@lynxeye.de>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 83c0bcb6
...@@ -149,7 +149,7 @@ struct tmds_config { ...@@ -149,7 +149,7 @@ struct tmds_config {
}; };
static const struct tmds_config tegra2_tmds_config[] = { static const struct tmds_config tegra2_tmds_config[] = {
{ /* 480p modes */ { /* slow pixel clock modes */
.pclk = 27000000, .pclk = 27000000,
.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
...@@ -163,21 +163,8 @@ static const struct tmds_config tegra2_tmds_config[] = { ...@@ -163,21 +163,8 @@ static const struct tmds_config tegra2_tmds_config[] = {
DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
}, { /* 720p modes */ },
.pclk = 74250000, { /* high pixel clock modes */
.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
SOR_PLL_TX_REG_LOAD(3),
.pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
.pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
PE_CURRENT1(PE_CURRENT_6_0_mA) |
PE_CURRENT2(PE_CURRENT_6_0_mA) |
PE_CURRENT3(PE_CURRENT_6_0_mA),
.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
}, { /* 1080p modes */
.pclk = UINT_MAX, .pclk = UINT_MAX,
.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
......
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