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Commit fa739f4b authored by James Zhu's avatar James Zhu Committed by Alex Deucher
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drm/amdgpu: add multiple instances support for Arcturus 

Arcturus has dual-VCN. Need add multiple instances support for Arcturus.
Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c01b6a1d
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Showing with 737 additions and 627 deletions
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
View file @ fa739f4b
...@@ -408,23 +408,29 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev, ...@@ -408,23 +408,29 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
break; break;
case AMDGPU_HW_IP_VCN_DEC: case AMDGPU_HW_IP_VCN_DEC:
type = AMD_IP_BLOCK_TYPE_VCN; type = AMD_IP_BLOCK_TYPE_VCN;
if (adev->vcn.inst[0].ring_dec.sched.ready) for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
++num_rings; if (adev->vcn.inst[i].ring_dec.sched.ready)
++num_rings;
}
ib_start_alignment = 16; ib_start_alignment = 16;
ib_size_alignment = 16; ib_size_alignment = 16;
break; break;
case AMDGPU_HW_IP_VCN_ENC: case AMDGPU_HW_IP_VCN_ENC:
type = AMD_IP_BLOCK_TYPE_VCN; type = AMD_IP_BLOCK_TYPE_VCN;
for (i = 0; i < adev->vcn.num_enc_rings; i++) for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
if (adev->vcn.inst[0].ring_enc[i].sched.ready) for (j = 0; j < adev->vcn.num_enc_rings; j++)
++num_rings; if (adev->vcn.inst[i].ring_enc[j].sched.ready)
++num_rings;
}
ib_start_alignment = 64; ib_start_alignment = 64;
ib_size_alignment = 1; ib_size_alignment = 1;
break; break;
case AMDGPU_HW_IP_VCN_JPEG: case AMDGPU_HW_IP_VCN_JPEG:
type = AMD_IP_BLOCK_TYPE_VCN; type = AMD_IP_BLOCK_TYPE_VCN;
if (adev->vcn.inst[0].ring_jpeg.sched.ready) for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
++num_rings; if (adev->vcn.inst[i].ring_jpeg.sched.ready)
++num_rings;
}
ib_start_alignment = 16; ib_start_alignment = 16;
ib_size_alignment = 16; ib_size_alignment = 16;
break; break;
......
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
View file @ fa739f4b
...@@ -65,7 +65,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) ...@@ -65,7 +65,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
const char *fw_name; const char *fw_name;
const struct common_firmware_header *hdr; const struct common_firmware_header *hdr;
unsigned char fw_check; unsigned char fw_check;
int r; int i, r;
INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
...@@ -146,12 +146,15 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) ...@@ -146,12 +146,15 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[0].vcpu_bo, for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
&adev->vcn.inst[0].gpu_addr, &adev->vcn.inst[0].cpu_addr); r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
if (r) { AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r); &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
return r; if (r) {
dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
return r;
}
} }
if (adev->vcn.indirect_sram) { if (adev->vcn.indirect_sram) {
...@@ -169,26 +172,28 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) ...@@ -169,26 +172,28 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
{ {
int i; int i, j;
kvfree(adev->vcn.inst[0].saved_bo);
if (adev->vcn.indirect_sram) { if (adev->vcn.indirect_sram) {
amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo, amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo,
&adev->vcn.dpg_sram_gpu_addr, &adev->vcn.dpg_sram_gpu_addr,
(void **)&adev->vcn.dpg_sram_cpu_addr); (void **)&adev->vcn.dpg_sram_cpu_addr);
} }
amdgpu_bo_free_kernel(&adev->vcn.inst[0].vcpu_bo, for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
&adev->vcn.inst[0].gpu_addr, kvfree(adev->vcn.inst[j].saved_bo);
(void **)&adev->vcn.inst[0].cpu_addr);
amdgpu_ring_fini(&adev->vcn.inst[0].ring_dec); amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
&adev->vcn.inst[j].gpu_addr,
(void **)&adev->vcn.inst[j].cpu_addr);
for (i = 0; i < adev->vcn.num_enc_rings; ++i) amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
amdgpu_ring_fini(&adev->vcn.inst[0].ring_enc[i]);
amdgpu_ring_fini(&adev->vcn.inst[0].ring_jpeg); for (i = 0; i < adev->vcn.num_enc_rings; ++i)
amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
amdgpu_ring_fini(&adev->vcn.inst[j].ring_jpeg);
}
release_firmware(adev->vcn.fw); release_firmware(adev->vcn.fw);
...@@ -199,21 +204,23 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev) ...@@ -199,21 +204,23 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
{ {
unsigned size; unsigned size;
void *ptr; void *ptr;
int i;
cancel_delayed_work_sync(&adev->vcn.idle_work); cancel_delayed_work_sync(&adev->vcn.idle_work);
if (adev->vcn.inst[0].vcpu_bo == NULL) for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
return 0; if (adev->vcn.inst[i].vcpu_bo == NULL)
return 0;
size = amdgpu_bo_size(adev->vcn.inst[0].vcpu_bo); size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
ptr = adev->vcn.inst[0].cpu_addr; ptr = adev->vcn.inst[i].cpu_addr;
adev->vcn.inst[0].saved_bo = kvmalloc(size, GFP_KERNEL); adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
if (!adev->vcn.inst[0].saved_bo) if (!adev->vcn.inst[i].saved_bo)
return -ENOMEM; return -ENOMEM;
memcpy_fromio(adev->vcn.inst[0].saved_bo, ptr, size);
memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
}
return 0; return 0;
} }
...@@ -221,32 +228,34 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev) ...@@ -221,32 +228,34 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
{ {
unsigned size; unsigned size;
void *ptr; void *ptr;
int i;
if (adev->vcn.inst[0].vcpu_bo == NULL) for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
return -EINVAL; if (adev->vcn.inst[i].vcpu_bo == NULL)
return -EINVAL;
size = amdgpu_bo_size(adev->vcn.inst[0].vcpu_bo);
ptr = adev->vcn.inst[0].cpu_addr; size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
ptr = adev->vcn.inst[i].cpu_addr;
if (adev->vcn.inst[0].saved_bo != NULL) {
memcpy_toio(ptr, adev->vcn.inst[0].saved_bo, size); if (adev->vcn.inst[i].saved_bo != NULL) {
kvfree(adev->vcn.inst[0].saved_bo); memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
adev->vcn.inst[0].saved_bo = NULL; kvfree(adev->vcn.inst[i].saved_bo);
} else { adev->vcn.inst[i].saved_bo = NULL;
const struct common_firmware_header *hdr; } else {
unsigned offset; const struct common_firmware_header *hdr;
unsigned offset;
hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
offset = le32_to_cpu(hdr->ucode_array_offset_bytes); if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
memcpy_toio(adev->vcn.inst[0].cpu_addr, adev->vcn.fw->data + offset, offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
le32_to_cpu(hdr->ucode_size_bytes)); memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
size -= le32_to_cpu(hdr->ucode_size_bytes); le32_to_cpu(hdr->ucode_size_bytes));
ptr += le32_to_cpu(hdr->ucode_size_bytes); size -= le32_to_cpu(hdr->ucode_size_bytes);
ptr += le32_to_cpu(hdr->ucode_size_bytes);
}
memset_io(ptr, 0, size);
} }
memset_io(ptr, 0, size);
} }
return 0; return 0;
} }
...@@ -254,31 +263,34 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work) ...@@ -254,31 +263,34 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
{ {
struct amdgpu_device *adev = struct amdgpu_device *adev =
container_of(work, struct amdgpu_device, vcn.idle_work.work); container_of(work, struct amdgpu_device, vcn.idle_work.work);
unsigned int fences = 0; unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
unsigned int i; unsigned int i, j;
for (i = 0; i < adev->vcn.num_enc_rings; ++i) { for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
fences += amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_enc[i]); for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
} fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
}
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
struct dpg_pause_state new_state; struct dpg_pause_state new_state;
if (fences) if (fence[j])
new_state.fw_based = VCN_DPG_STATE__PAUSE; new_state.fw_based = VCN_DPG_STATE__PAUSE;
else else
new_state.fw_based = VCN_DPG_STATE__UNPAUSE; new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
if (amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_jpeg)) if (amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg))
new_state.jpeg = VCN_DPG_STATE__PAUSE; new_state.jpeg = VCN_DPG_STATE__PAUSE;
else else
new_state.jpeg = VCN_DPG_STATE__UNPAUSE; new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
adev->vcn.pause_dpg_mode(adev, &new_state); adev->vcn.pause_dpg_mode(adev, &new_state);
} }
fences += amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_jpeg); fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg);
fences += amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_dec); fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
fences += fence[j];
}
if (fences == 0) { if (fences == 0) {
amdgpu_gfx_off_ctrl(adev, true); amdgpu_gfx_off_ctrl(adev, true);
...@@ -312,14 +324,14 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) ...@@ -312,14 +324,14 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
unsigned int i; unsigned int i;
for (i = 0; i < adev->vcn.num_enc_rings; ++i) { for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
fences += amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_enc[i]); fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
} }
if (fences) if (fences)
new_state.fw_based = VCN_DPG_STATE__PAUSE; new_state.fw_based = VCN_DPG_STATE__PAUSE;
else else
new_state.fw_based = VCN_DPG_STATE__UNPAUSE; new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
if (amdgpu_fence_count_emitted(&adev->vcn.inst[0].ring_jpeg)) if (amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_jpeg))
new_state.jpeg = VCN_DPG_STATE__PAUSE; new_state.jpeg = VCN_DPG_STATE__PAUSE;
else else
new_state.jpeg = VCN_DPG_STATE__UNPAUSE; new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
...@@ -345,7 +357,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) ...@@ -345,7 +357,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
unsigned i; unsigned i;
int r; int r;
WREG32(adev->vcn.inst[0].external.scratch9, 0xCAFEDEAD); WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 3); r = amdgpu_ring_alloc(ring, 3);
if (r) if (r)
return r; return r;
...@@ -353,7 +365,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) ...@@ -353,7 +365,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
amdgpu_ring_write(ring, 0xDEADBEEF); amdgpu_ring_write(ring, 0xDEADBEEF);
amdgpu_ring_commit(ring); amdgpu_ring_commit(ring);
for (i = 0; i < adev->usec_timeout; i++) { for (i = 0; i < adev->usec_timeout; i++) {
tmp = RREG32(adev->vcn.inst[0].external.scratch9); tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
if (tmp == 0xDEADBEEF) if (tmp == 0xDEADBEEF)
break; break;
udelay(1); udelay(1);
...@@ -664,7 +676,7 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring) ...@@ -664,7 +676,7 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
unsigned i; unsigned i;
int r; int r;
WREG32(adev->vcn.inst[0].external.jpeg_pitch, 0xCAFEDEAD); WREG32(adev->vcn.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 3); r = amdgpu_ring_alloc(ring, 3);
if (r) if (r)
return r; return r;
...@@ -674,7 +686,7 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring) ...@@ -674,7 +686,7 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
amdgpu_ring_commit(ring); amdgpu_ring_commit(ring);
for (i = 0; i < adev->usec_timeout; i++) { for (i = 0; i < adev->usec_timeout; i++) {
tmp = RREG32(adev->vcn.inst[0].external.jpeg_pitch); tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
if (tmp == 0xDEADBEEF) if (tmp == 0xDEADBEEF)
break; break;
udelay(1); udelay(1);
...@@ -748,7 +760,7 @@ int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout) ...@@ -748,7 +760,7 @@ int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
} }
for (i = 0; i < adev->usec_timeout; i++) { for (i = 0; i < adev->usec_timeout; i++) {
tmp = RREG32(adev->vcn.inst[0].external.jpeg_pitch); tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
if (tmp == 0xDEADBEEF) if (tmp == 0xDEADBEEF)
break; break;
udelay(1); udelay(1);
......
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
View file @ fa739f4b
...@@ -48,6 +48,8 @@ ...@@ -48,6 +48,8 @@
#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
#define VCN25_MAX_HW_INSTANCES_ARCTURUS 2
static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev); static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev); static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev);
...@@ -55,6 +57,11 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev); ...@@ -55,6 +57,11 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v2_5_set_powergating_state(void *handle, static int vcn_v2_5_set_powergating_state(void *handle,
enum amd_powergating_state state); enum amd_powergating_state state);
static int amdgpu_ih_clientid_vcns[] = {
SOC15_IH_CLIENTID_VCN,
SOC15_IH_CLIENTID_VCN1
};
/** /**
* vcn_v2_5_early_init - set function pointers * vcn_v2_5_early_init - set function pointers
* *
...@@ -65,8 +72,11 @@ static int vcn_v2_5_set_powergating_state(void *handle, ...@@ -65,8 +72,11 @@ static int vcn_v2_5_set_powergating_state(void *handle,
static int vcn_v2_5_early_init(void *handle) static int vcn_v2_5_early_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->asic_type == CHIP_ARCTURUS)
adev->vcn.num_vcn_inst = 1; adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS;
else
adev->vcn.num_vcn_inst = 1;
adev->vcn.num_enc_rings = 2; adev->vcn.num_enc_rings = 2;
vcn_v2_5_set_dec_ring_funcs(adev); vcn_v2_5_set_dec_ring_funcs(adev);
...@@ -87,29 +97,31 @@ static int vcn_v2_5_early_init(void *handle) ...@@ -87,29 +97,31 @@ static int vcn_v2_5_early_init(void *handle)
static int vcn_v2_5_sw_init(void *handle) static int vcn_v2_5_sw_init(void *handle)
{ {
struct amdgpu_ring *ring; struct amdgpu_ring *ring;
int i, r; int i, j, r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* VCN DEC TRAP */ for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, /* VCN DEC TRAP */
VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[0].irq); r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
if (r) VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq);
return r; if (r)
return r;
/* VCN ENC TRAP */
for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq);
if (r)
return r;
}
/* VCN ENC TRAP */ /* VCN JPEG TRAP */
for (i = 0; i < adev->vcn.num_enc_rings; ++i) { r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst[j].irq);
i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[0].irq);
if (r) if (r)
return r; return r;
} }
/* VCN JPEG TRAP */
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst[0].irq);
if (r)
return r;
r = amdgpu_vcn_sw_init(adev); r = amdgpu_vcn_sw_init(adev);
if (r) if (r)
return r; return r;
...@@ -121,6 +133,13 @@ static int vcn_v2_5_sw_init(void *handle) ...@@ -121,6 +133,13 @@ static int vcn_v2_5_sw_init(void *handle)
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
adev->firmware.fw_size += adev->firmware.fw_size +=
ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
if (adev->vcn.num_vcn_inst == VCN25_MAX_HW_INSTANCES_ARCTURUS) {
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
adev->firmware.fw_size +=
ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
}
DRM_INFO("PSP loading VCN firmware\n"); DRM_INFO("PSP loading VCN firmware\n");
} }
...@@ -128,52 +147,54 @@ static int vcn_v2_5_sw_init(void *handle) ...@@ -128,52 +147,54 @@ static int vcn_v2_5_sw_init(void *handle)
if (r) if (r)
return r; return r;
ring = &adev->vcn.inst[0].ring_dec; for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
ring->use_doorbell = true; adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
sprintf(ring->name, "vcn_dec"); adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[0].irq, 0); adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
if (r) adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
return r; adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(UVD, j, mmUVD_SCRATCH9);
adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA0);
adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA1);
adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_CMD);
adev->vcn.inst[0].external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(UVD, j, mmUVD_NO_OP);
adev->vcn.inst[0].external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
adev->vcn.inst[0].external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); adev->vcn.inst[j].external.jpeg_pitch = SOC15_REG_OFFSET(UVD, j, mmUVD_JPEG_PITCH);
adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
adev->vcn.inst[0].external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); ring = &adev->vcn.inst[j].ring_dec;
adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
adev->vcn.inst[0].external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
ring = &adev->vcn.inst[0].ring_enc[i];
ring->use_doorbell = true; ring->use_doorbell = true;
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i; ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8*j;
sprintf(ring->name, "vcn_enc%d", i); sprintf(ring->name, "vcn_dec_%d", j);
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[0].irq, 0); r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0);
if (r) if (r)
return r; return r;
}
ring = &adev->vcn.inst[0].ring_jpeg; for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
ring->use_doorbell = true; ring = &adev->vcn.inst[j].ring_enc[i];
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; ring->use_doorbell = true;
sprintf(ring->name, "vcn_jpeg"); ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i + 8*j;
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[0].irq, 0); sprintf(ring->name, "vcn_enc_%d.%d", j, i);
if (r) r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0);
return r; if (r)
return r;
}
adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; ring = &adev->vcn.inst[j].ring_jpeg;
adev->vcn.inst[0].external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH); ring->use_doorbell = true;
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8*j;
sprintf(ring->name, "vcn_jpeg_%d", j);
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0);
if (r)
return r;
}
return 0; return 0;
} }
...@@ -209,36 +230,39 @@ static int vcn_v2_5_sw_fini(void *handle) ...@@ -209,36 +230,39 @@ static int vcn_v2_5_sw_fini(void *handle)
static int vcn_v2_5_hw_init(void *handle) static int vcn_v2_5_hw_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring = &adev->vcn.inst[0].ring_dec; struct amdgpu_ring *ring;
int i, r; int i, j, r;
adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell, for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
ring->doorbell_index, 0); ring = &adev->vcn.inst[j].ring_dec;
r = amdgpu_ring_test_ring(ring); adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
if (r) { ring->doorbell_index, j);
ring->sched.ready = false;
goto done;
}
for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
ring = &adev->vcn.inst[0].ring_enc[i];
ring->sched.ready = false;
continue;
r = amdgpu_ring_test_ring(ring); r = amdgpu_ring_test_ring(ring);
if (r) { if (r) {
ring->sched.ready = false; ring->sched.ready = false;
goto done; goto done;
} }
}
ring = &adev->vcn.inst[0].ring_jpeg; for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
r = amdgpu_ring_test_ring(ring); ring = &adev->vcn.inst[j].ring_enc[i];
if (r) { ring->sched.ready = false;
ring->sched.ready = false; continue;
goto done; r = amdgpu_ring_test_ring(ring);
} if (r) {
ring->sched.ready = false;
goto done;
}
}
ring = &adev->vcn.inst[j].ring_jpeg;
r = amdgpu_ring_test_ring(ring);
if (r) {
ring->sched.ready = false;
goto done;
}
}
done: done:
if (!r) if (!r)
DRM_INFO("VCN decode and encode initialized successfully.\n"); DRM_INFO("VCN decode and encode initialized successfully.\n");
...@@ -256,21 +280,25 @@ static int vcn_v2_5_hw_init(void *handle) ...@@ -256,21 +280,25 @@ static int vcn_v2_5_hw_init(void *handle)
static int vcn_v2_5_hw_fini(void *handle) static int vcn_v2_5_hw_fini(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring = &adev->vcn.inst[0].ring_dec; struct amdgpu_ring *ring;
int i; int i;
if (RREG32_SOC15(VCN, 0, mmUVD_STATUS)) for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE); ring = &adev->vcn.inst[i].ring_dec;
ring->sched.ready = false; if (RREG32_SOC15(VCN, i, mmUVD_STATUS))
vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
ring = &adev->vcn.inst[0].ring_enc[i];
ring->sched.ready = false; ring->sched.ready = false;
}
ring = &adev->vcn.inst[0].ring_jpeg; for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
ring->sched.ready = false; ring = &adev->vcn.inst[i].ring_enc[i];
ring->sched.ready = false;
}
ring = &adev->vcn.inst[i].ring_jpeg;
ring->sched.ready = false;
}
return 0; return 0;
} }
...@@ -328,44 +356,47 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev) ...@@ -328,44 +356,47 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
{ {
uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
uint32_t offset; uint32_t offset;
int i;
/* cache window 0: fw */ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { /* cache window 0: fw */
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
offset = 0; WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
} else { offset = 0;
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, } else {
lower_32_bits(adev->vcn.inst[0].gpu_addr)); WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, lower_32_bits(adev->vcn.inst[i].gpu_addr));
upper_32_bits(adev->vcn.inst[0].gpu_addr)); WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
offset = size; upper_32_bits(adev->vcn.inst[i].gpu_addr));
/* No signed header for now from firmware offset = size;
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, /* No signed header for now from firmware
AMDGPU_UVD_FIRMWARE_OFFSET >> 3); WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
*/ AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); */
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
}
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
/* cache window 1: stack */
WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, 0);
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
/* cache window 2: context */
WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, 0);
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
} }
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
/* cache window 1: stack */
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
lower_32_bits(adev->vcn.inst[0].gpu_addr + offset));
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
upper_32_bits(adev->vcn.inst[0].gpu_addr + offset));
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
/* cache window 2: context */
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
lower_32_bits(adev->vcn.inst[0].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
upper_32_bits(adev->vcn.inst[0].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
} }
/** /**
...@@ -380,106 +411,109 @@ static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev) ...@@ -380,106 +411,109 @@ static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
{ {
uint32_t data; uint32_t data;
int ret = 0; int ret = 0;
int i;
/* UVD disable CGC */ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); /* UVD disable CGC */
if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
else data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; else
data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
data &= ~(UVD_CGC_GATE__SYS_MASK data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);
| UVD_CGC_GATE__UDEC_MASK data &= ~(UVD_CGC_GATE__SYS_MASK
| UVD_CGC_GATE__MPEG2_MASK | UVD_CGC_GATE__UDEC_MASK
| UVD_CGC_GATE__REGS_MASK | UVD_CGC_GATE__MPEG2_MASK
| UVD_CGC_GATE__RBC_MASK | UVD_CGC_GATE__REGS_MASK
| UVD_CGC_GATE__LMI_MC_MASK | UVD_CGC_GATE__RBC_MASK
| UVD_CGC_GATE__LMI_UMC_MASK | UVD_CGC_GATE__LMI_MC_MASK
| UVD_CGC_GATE__IDCT_MASK | UVD_CGC_GATE__LMI_UMC_MASK
| UVD_CGC_GATE__MPRD_MASK | UVD_CGC_GATE__IDCT_MASK
| UVD_CGC_GATE__MPC_MASK | UVD_CGC_GATE__MPRD_MASK
| UVD_CGC_GATE__LBSI_MASK | UVD_CGC_GATE__MPC_MASK
| UVD_CGC_GATE__LRBBM_MASK | UVD_CGC_GATE__LBSI_MASK
| UVD_CGC_GATE__UDEC_RE_MASK | UVD_CGC_GATE__LRBBM_MASK
| UVD_CGC_GATE__UDEC_CM_MASK | UVD_CGC_GATE__UDEC_RE_MASK
| UVD_CGC_GATE__UDEC_IT_MASK | UVD_CGC_GATE__UDEC_CM_MASK
| UVD_CGC_GATE__UDEC_DB_MASK | UVD_CGC_GATE__UDEC_IT_MASK
| UVD_CGC_GATE__UDEC_MP_MASK | UVD_CGC_GATE__UDEC_DB_MASK
| UVD_CGC_GATE__WCB_MASK | UVD_CGC_GATE__UDEC_MP_MASK
| UVD_CGC_GATE__VCPU_MASK | UVD_CGC_GATE__WCB_MASK
| UVD_CGC_GATE__MMSCH_MASK); | UVD_CGC_GATE__VCPU_MASK
| UVD_CGC_GATE__MMSCH_MASK);
WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, ret);
SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, ret);
data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
| UVD_CGC_CTRL__UDEC_CM_MODE_MASK data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
| UVD_CGC_CTRL__UDEC_IT_MODE_MASK | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
| UVD_CGC_CTRL__UDEC_DB_MODE_MASK | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
| UVD_CGC_CTRL__UDEC_MP_MODE_MASK | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
| UVD_CGC_CTRL__SYS_MODE_MASK | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
| UVD_CGC_CTRL__UDEC_MODE_MASK | UVD_CGC_CTRL__SYS_MODE_MASK
| UVD_CGC_CTRL__MPEG2_MODE_MASK | UVD_CGC_CTRL__UDEC_MODE_MASK
| UVD_CGC_CTRL__REGS_MODE_MASK | UVD_CGC_CTRL__MPEG2_MODE_MASK
| UVD_CGC_CTRL__RBC_MODE_MASK | UVD_CGC_CTRL__REGS_MODE_MASK
| UVD_CGC_CTRL__LMI_MC_MODE_MASK | UVD_CGC_CTRL__RBC_MODE_MASK
| UVD_CGC_CTRL__LMI_UMC_MODE_MASK | UVD_CGC_CTRL__LMI_MC_MODE_MASK
| UVD_CGC_CTRL__IDCT_MODE_MASK | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
| UVD_CGC_CTRL__MPRD_MODE_MASK | UVD_CGC_CTRL__IDCT_MODE_MASK
| UVD_CGC_CTRL__MPC_MODE_MASK | UVD_CGC_CTRL__MPRD_MODE_MASK
| UVD_CGC_CTRL__LBSI_MODE_MASK | UVD_CGC_CTRL__MPC_MODE_MASK
| UVD_CGC_CTRL__LRBBM_MODE_MASK | UVD_CGC_CTRL__LBSI_MODE_MASK
| UVD_CGC_CTRL__WCB_MODE_MASK | UVD_CGC_CTRL__LRBBM_MODE_MASK
| UVD_CGC_CTRL__VCPU_MODE_MASK | UVD_CGC_CTRL__WCB_MODE_MASK
| UVD_CGC_CTRL__MMSCH_MODE_MASK); | UVD_CGC_CTRL__VCPU_MODE_MASK
WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); | UVD_CGC_CTRL__MMSCH_MODE_MASK);
WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
/* turn on */
data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); /* turn on */
data |= (UVD_SUVD_CGC_GATE__SRE_MASK data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);
| UVD_SUVD_CGC_GATE__SIT_MASK data |= (UVD_SUVD_CGC_GATE__SRE_MASK
| UVD_SUVD_CGC_GATE__SMP_MASK | UVD_SUVD_CGC_GATE__SIT_MASK
| UVD_SUVD_CGC_GATE__SCM_MASK | UVD_SUVD_CGC_GATE__SMP_MASK
| UVD_SUVD_CGC_GATE__SDB_MASK | UVD_SUVD_CGC_GATE__SCM_MASK
| UVD_SUVD_CGC_GATE__SRE_H264_MASK | UVD_SUVD_CGC_GATE__SDB_MASK
| UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | UVD_SUVD_CGC_GATE__SRE_H264_MASK
| UVD_SUVD_CGC_GATE__SIT_H264_MASK | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
| UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | UVD_SUVD_CGC_GATE__SIT_H264_MASK
| UVD_SUVD_CGC_GATE__SCM_H264_MASK | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
| UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | UVD_SUVD_CGC_GATE__SCM_H264_MASK
| UVD_SUVD_CGC_GATE__SDB_H264_MASK | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
| UVD_SUVD_CGC_GATE__SDB_HEVC_MASK | UVD_SUVD_CGC_GATE__SDB_H264_MASK
| UVD_SUVD_CGC_GATE__SCLR_MASK | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
| UVD_SUVD_CGC_GATE__UVD_SC_MASK | UVD_SUVD_CGC_GATE__SCLR_MASK
| UVD_SUVD_CGC_GATE__ENT_MASK | UVD_SUVD_CGC_GATE__UVD_SC_MASK
| UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK | UVD_SUVD_CGC_GATE__ENT_MASK
| UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
| UVD_SUVD_CGC_GATE__SITE_MASK | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
| UVD_SUVD_CGC_GATE__SRE_VP9_MASK | UVD_SUVD_CGC_GATE__SITE_MASK
| UVD_SUVD_CGC_GATE__SCM_VP9_MASK | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
| UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
| UVD_SUVD_CGC_GATE__SDB_VP9_MASK | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
| UVD_SUVD_CGC_GATE__IME_HEVC_MASK); | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data);
data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
| UVD_SUVD_CGC_CTRL__IME_MODE_MASK | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
}
} }
/** /**
...@@ -493,51 +527,54 @@ static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev) ...@@ -493,51 +527,54 @@ static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev) static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
{ {
uint32_t data = 0; uint32_t data = 0;
int i;
/* enable UVD CGC */ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); /* enable UVD CGC */
if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
else data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; else
data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
| UVD_CGC_CTRL__UDEC_CM_MODE_MASK data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
| UVD_CGC_CTRL__UDEC_IT_MODE_MASK | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
| UVD_CGC_CTRL__UDEC_DB_MODE_MASK | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
| UVD_CGC_CTRL__UDEC_MP_MODE_MASK | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
| UVD_CGC_CTRL__SYS_MODE_MASK | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
| UVD_CGC_CTRL__UDEC_MODE_MASK | UVD_CGC_CTRL__SYS_MODE_MASK
| UVD_CGC_CTRL__MPEG2_MODE_MASK | UVD_CGC_CTRL__UDEC_MODE_MASK
| UVD_CGC_CTRL__REGS_MODE_MASK | UVD_CGC_CTRL__MPEG2_MODE_MASK
| UVD_CGC_CTRL__RBC_MODE_MASK | UVD_CGC_CTRL__REGS_MODE_MASK
| UVD_CGC_CTRL__LMI_MC_MODE_MASK | UVD_CGC_CTRL__RBC_MODE_MASK
| UVD_CGC_CTRL__LMI_UMC_MODE_MASK | UVD_CGC_CTRL__LMI_MC_MODE_MASK
| UVD_CGC_CTRL__IDCT_MODE_MASK | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
| UVD_CGC_CTRL__MPRD_MODE_MASK | UVD_CGC_CTRL__IDCT_MODE_MASK
| UVD_CGC_CTRL__MPC_MODE_MASK | UVD_CGC_CTRL__MPRD_MODE_MASK
| UVD_CGC_CTRL__LBSI_MODE_MASK | UVD_CGC_CTRL__MPC_MODE_MASK
| UVD_CGC_CTRL__LRBBM_MODE_MASK | UVD_CGC_CTRL__LBSI_MODE_MASK
| UVD_CGC_CTRL__WCB_MODE_MASK | UVD_CGC_CTRL__LRBBM_MODE_MASK
| UVD_CGC_CTRL__VCPU_MODE_MASK); | UVD_CGC_CTRL__WCB_MODE_MASK
WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); | UVD_CGC_CTRL__VCPU_MODE_MASK);
WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
| UVD_SUVD_CGC_CTRL__IME_MODE_MASK | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
}
} }
/** /**
...@@ -549,60 +586,64 @@ static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev) ...@@ -549,60 +586,64 @@ static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
*/ */
static int jpeg_v2_5_start(struct amdgpu_device *adev) static int jpeg_v2_5_start(struct amdgpu_device *adev)
{ {
struct amdgpu_ring *ring = &adev->vcn.inst[0].ring_jpeg; struct amdgpu_ring *ring;
uint32_t tmp; uint32_t tmp;
int i;
/* disable anti hang mechanism */ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), 0, ring = &adev->vcn.inst[i].ring_jpeg;
~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); /* disable anti hang mechanism */
WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS), 0,
/* JPEG disable CGC */ ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; /* JPEG disable CGC */
tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL);
tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp); tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); WREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL, tmp);
tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
| JPEG_CGC_GATE__JPEG2_DEC_MASK tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_GATE);
| JPEG_CGC_GATE__JMCIF_MASK tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
| JPEG_CGC_GATE__JRBBM_MASK); | JPEG_CGC_GATE__JPEG2_DEC_MASK
WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp); | JPEG_CGC_GATE__JMCIF_MASK
| JPEG_CGC_GATE__JRBBM_MASK);
tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); WREG32_SOC15(VCN, i, mmJPEG_CGC_GATE, tmp);
tmp &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
| JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL);
| JPEG_CGC_CTRL__JMCIF_MODE_MASK tmp &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
| JPEG_CGC_CTRL__JRBBM_MODE_MASK); | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp); | JPEG_CGC_CTRL__JMCIF_MODE_MASK
| JPEG_CGC_CTRL__JRBBM_MODE_MASK);
/* MJPEG global tiling registers */ WREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL, tmp);
WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX8_ADDR_CONFIG,
adev->gfx.config.gb_addr_config); /* MJPEG global tiling registers */
WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, WREG32_SOC15(UVD, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
adev->gfx.config.gb_addr_config); adev->gfx.config.gb_addr_config);
WREG32_SOC15(UVD, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
/* enable JMI channel */ adev->gfx.config.gb_addr_config);
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), 0,
~UVD_JMI_CNTL__SOFT_RESET_MASK); /* enable JMI channel */
WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL), 0,
/* enable System Interrupt for JRBC */ ~UVD_JMI_CNTL__SOFT_RESET_MASK);
WREG32_P(SOC15_REG_OFFSET(VCN, 0, mmJPEG_SYS_INT_EN),
JPEG_SYS_INT_EN__DJRBC_MASK, /* enable System Interrupt for JRBC */
~JPEG_SYS_INT_EN__DJRBC_MASK); WREG32_P(SOC15_REG_OFFSET(VCN, i, mmJPEG_SYS_INT_EN),
JPEG_SYS_INT_EN__DJRBC_MASK,
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); ~JPEG_SYS_INT_EN__DJRBC_MASK);
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_VMID, 0);
lower_32_bits(ring->gpu_addr)); WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
upper_32_bits(ring->gpu_addr)); lower_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0); WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0); upper_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_RPTR, 0);
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR, 0);
ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
ring->wptr = RREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR);
}
return 0; return 0;
} }
...@@ -617,185 +658,194 @@ static int jpeg_v2_5_start(struct amdgpu_device *adev) ...@@ -617,185 +658,194 @@ static int jpeg_v2_5_start(struct amdgpu_device *adev)
static int jpeg_v2_5_stop(struct amdgpu_device *adev) static int jpeg_v2_5_stop(struct amdgpu_device *adev)
{ {
uint32_t tmp; uint32_t tmp;
int i;
/* reset JMI */ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JMI_CNTL), /* reset JMI */
UVD_JMI_CNTL__SOFT_RESET_MASK, WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL),
~UVD_JMI_CNTL__SOFT_RESET_MASK); UVD_JMI_CNTL__SOFT_RESET_MASK,
~UVD_JMI_CNTL__SOFT_RESET_MASK);
tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_GATE);
|JPEG_CGC_GATE__JPEG2_DEC_MASK tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK
|JPEG_CGC_GATE__JMCIF_MASK |JPEG_CGC_GATE__JPEG2_DEC_MASK
|JPEG_CGC_GATE__JRBBM_MASK); |JPEG_CGC_GATE__JMCIF_MASK
WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp); |JPEG_CGC_GATE__JRBBM_MASK);
WREG32_SOC15(VCN, i, mmJPEG_CGC_GATE, tmp);
/* enable anti hang mechanism */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_POWER_STATUS), /* enable anti hang mechanism */
UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS),
~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
}
return 0; return 0;
} }
static int vcn_v2_5_start(struct amdgpu_device *adev) static int vcn_v2_5_start(struct amdgpu_device *adev)
{ {
struct amdgpu_ring *ring = &adev->vcn.inst[0].ring_dec; struct amdgpu_ring *ring;
uint32_t rb_bufsz, tmp; uint32_t rb_bufsz, tmp;
int i, j, r; int i, j, k, r;
/* disable register anti-hang mechanism */ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, /* disable register anti-hang mechanism */
~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
/* set uvd status busy */ /* set uvd status busy */
tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; tmp = RREG32_SOC15(UVD, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); WREG32_SOC15(UVD, i, mmUVD_STATUS, tmp);
}
/*SW clock gating */ /*SW clock gating */
vcn_v2_5_disable_clock_gating(adev); vcn_v2_5_disable_clock_gating(adev);
/* enable VCPU clock */ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), /* enable VCPU clock */
UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
/* disable master interrupt */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, /* disable master interrupt */
~UVD_MASTINT_EN__VCPU_EN_MASK); WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0,
~UVD_MASTINT_EN__VCPU_EN_MASK);
/* setup mmUVD_LMI_CTRL */
tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); /* setup mmUVD_LMI_CTRL */
tmp &= ~0xff; tmp = RREG32_SOC15(UVD, i, mmUVD_LMI_CTRL);
WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 0x8| tmp &= ~0xff;
UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | WREG32_SOC15(UVD, i, mmUVD_LMI_CTRL, tmp | 0x8|
UVD_LMI_CTRL__MASK_MC_URGENT_MASK | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
/* setup mmUVD_MPC_CNTL */
tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); /* setup mmUVD_MPC_CNTL */
tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; tmp = RREG32_SOC15(UVD, i, mmUVD_MPC_CNTL);
tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
/* setup UVD_MPC_SET_MUXA0 */
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, /* setup UVD_MPC_SET_MUXA0 */
((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXA0,
(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
/* setup UVD_MPC_SET_MUXB0 */
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, /* setup UVD_MPC_SET_MUXB0 */
((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXB0,
(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
/* setup mmUVD_MPC_SET_MUX */
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, /* setup mmUVD_MPC_SET_MUX */
((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUX,
(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
}
vcn_v2_5_mc_resume(adev); vcn_v2_5_mc_resume(adev);
/* VCN global tiling registers */ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
WREG32_SOC15(UVD, 0, mmUVD_GFX8_ADDR_CONFIG, /* VCN global tiling registers */
adev->gfx.config.gb_addr_config); WREG32_SOC15(UVD, i, mmUVD_GFX8_ADDR_CONFIG,
WREG32_SOC15(UVD, 0, mmUVD_GFX8_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
adev->gfx.config.gb_addr_config); WREG32_SOC15(UVD, i, mmUVD_GFX8_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
/* enable LMI MC and UMC channels */ /* enable LMI MC and UMC channels */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
/* unblock VCPU register access */ /* unblock VCPU register access */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_ARB_CTRL), 0, WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL), 0,
~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
~UVD_VCPU_CNTL__BLK_RST_MASK); ~UVD_VCPU_CNTL__BLK_RST_MASK);
for (i = 0; i < 10; ++i) {
uint32_t status;
for (j = 0; j < 100; ++j) { for (k = 0; k < 10; ++k) {
status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); uint32_t status;
for (j = 0; j < 100; ++j) {
status = RREG32_SOC15(UVD, i, mmUVD_STATUS);
if (status & 2)
break;
if (amdgpu_emu_mode == 1)
msleep(500);
else
mdelay(10);
}
r = 0;
if (status & 2) if (status & 2)
break; break;
if (amdgpu_emu_mode == 1)
msleep(500);
else
mdelay(10);
}
r = 0;
if (status & 2)
break;
DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
UVD_VCPU_CNTL__BLK_RST_MASK,
~UVD_VCPU_CNTL__BLK_RST_MASK);
mdelay(10);
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
~UVD_VCPU_CNTL__BLK_RST_MASK);
mdelay(10); DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
r = -1; WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
} UVD_VCPU_CNTL__BLK_RST_MASK,
~UVD_VCPU_CNTL__BLK_RST_MASK);
mdelay(10);
WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
~UVD_VCPU_CNTL__BLK_RST_MASK);
if (r) { mdelay(10);
DRM_ERROR("VCN decode not responding, giving up!!!\n"); r = -1;
return r; }
}
/* enable master interrupt */ if (r) {
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), DRM_ERROR("VCN decode not responding, giving up!!!\n");
UVD_MASTINT_EN__VCPU_EN_MASK, return r;
~UVD_MASTINT_EN__VCPU_EN_MASK); }
/* clear the busy bit of VCN_STATUS */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
/* force RBC into idle state */
rb_bufsz = order_base_2(ring->ring_size);
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
/* programm the RB_BASE for ring buffer */
WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
lower_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
upper_32_bits(ring->gpu_addr));
/* Initialize the ring buffer's read and write pointers */
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
lower_32_bits(ring->wptr));
ring = &adev->vcn.inst[0].ring_enc[0];
WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
ring = &adev->vcn.inst[0].ring_enc[1];
WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
/* enable master interrupt */
WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
UVD_MASTINT_EN__VCPU_EN_MASK,
~UVD_MASTINT_EN__VCPU_EN_MASK);
/* clear the busy bit of VCN_STATUS */
WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0,
~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_VMID, 0);
ring = &adev->vcn.inst[i].ring_dec;
/* force RBC into idle state */
rb_bufsz = order_base_2(ring->ring_size);
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, tmp);
/* programm the RB_BASE for ring buffer */
WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
lower_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
upper_32_bits(ring->gpu_addr));
/* Initialize the ring buffer's read and write pointers */
WREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR, 0);
ring->wptr = RREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR);
WREG32_SOC15(UVD, i, mmUVD_RBC_RB_WPTR,
lower_32_bits(ring->wptr));
ring = &adev->vcn.inst[i].ring_enc[0];
WREG32_SOC15(UVD, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
WREG32_SOC15(UVD, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, i, mmUVD_RB_SIZE, ring->ring_size / 4);
ring = &adev->vcn.inst[i].ring_enc[1];
WREG32_SOC15(UVD, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
WREG32_SOC15(UVD, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
}
r = jpeg_v2_5_start(adev); r = jpeg_v2_5_start(adev);
return r; return r;
...@@ -804,59 +854,61 @@ static int vcn_v2_5_start(struct amdgpu_device *adev) ...@@ -804,59 +854,61 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
static int vcn_v2_5_stop(struct amdgpu_device *adev) static int vcn_v2_5_stop(struct amdgpu_device *adev)
{ {
uint32_t tmp; uint32_t tmp;
int r; int i, r;
r = jpeg_v2_5_stop(adev); r = jpeg_v2_5_stop(adev);
if (r) if (r)
return r; return r;
/* wait for vcn idle */ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r); /* wait for vcn idle */
if (r) SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
return r; if (r)
return r;
tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
UVD_LMI_STATUS__READ_CLEAN_MASK | UVD_LMI_STATUS__READ_CLEAN_MASK |
UVD_LMI_STATUS__WRITE_CLEAN_MASK | UVD_LMI_STATUS__WRITE_CLEAN_MASK |
UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r); SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);
if (r) if (r)
return r; return r;
/* block LMI UMC channel */ /* block LMI UMC channel */
tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r); SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);
if (r) if (r)
return r; return r;
/* block VCPU register access */ /* block VCPU register access */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_ARB_CTRL), WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL),
UVD_RB_ARB_CTRL__VCPU_DIS_MASK, UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
/* reset VCPU */ /* reset VCPU */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
UVD_VCPU_CNTL__BLK_RST_MASK, UVD_VCPU_CNTL__BLK_RST_MASK,
~UVD_VCPU_CNTL__BLK_RST_MASK); ~UVD_VCPU_CNTL__BLK_RST_MASK);
/* disable VCPU clock */ /* disable VCPU clock */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
~(UVD_VCPU_CNTL__CLK_EN_MASK)); ~(UVD_VCPU_CNTL__CLK_EN_MASK));
/* clear status */ /* clear status */
WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
vcn_v2_5_enable_clock_gating(adev); vcn_v2_5_enable_clock_gating(adev);
/* enable register anti-hang mechanism */ /* enable register anti-hang mechanism */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS),
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
}
return 0; return 0;
} }
...@@ -872,7 +924,7 @@ static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring) ...@@ -872,7 +924,7 @@ static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
{ {
struct amdgpu_device *adev = ring->adev; struct amdgpu_device *adev = ring->adev;
return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
} }
/** /**
...@@ -889,7 +941,7 @@ static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring) ...@@ -889,7 +941,7 @@ static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
if (ring->use_doorbell) if (ring->use_doorbell)
return adev->wb.wb[ring->wptr_offs]; return adev->wb.wb[ring->wptr_offs];
else else
return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
} }
/** /**
...@@ -907,7 +959,7 @@ static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) ...@@ -907,7 +959,7 @@ static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
} else { } else {
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
} }
} }
...@@ -952,10 +1004,10 @@ static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring) ...@@ -952,10 +1004,10 @@ static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
{ {
struct amdgpu_device *adev = ring->adev; struct amdgpu_device *adev = ring->adev;
if (ring == &adev->vcn.inst[0].ring_enc[0]) if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
else else
return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
} }
/** /**
...@@ -969,16 +1021,16 @@ static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring) ...@@ -969,16 +1021,16 @@ static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
{ {
struct amdgpu_device *adev = ring->adev; struct amdgpu_device *adev = ring->adev;
if (ring == &adev->vcn.inst[0].ring_enc[0]) { if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
if (ring->use_doorbell) if (ring->use_doorbell)
return adev->wb.wb[ring->wptr_offs]; return adev->wb.wb[ring->wptr_offs];
else else
return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
} else { } else {
if (ring->use_doorbell) if (ring->use_doorbell)
return adev->wb.wb[ring->wptr_offs]; return adev->wb.wb[ring->wptr_offs];
else else
return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
} }
} }
...@@ -993,19 +1045,19 @@ static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring) ...@@ -993,19 +1045,19 @@ static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
{ {
struct amdgpu_device *adev = ring->adev; struct amdgpu_device *adev = ring->adev;
if (ring == &adev->vcn.inst[0].ring_enc[0]) { if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
if (ring->use_doorbell) { if (ring->use_doorbell) {
adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
} else { } else {
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
} }
} else { } else {
if (ring->use_doorbell) { if (ring->use_doorbell) {
adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
} else { } else {
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
} }
} }
} }
...@@ -1051,7 +1103,7 @@ static uint64_t vcn_v2_5_jpeg_ring_get_rptr(struct amdgpu_ring *ring) ...@@ -1051,7 +1103,7 @@ static uint64_t vcn_v2_5_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
{ {
struct amdgpu_device *adev = ring->adev; struct amdgpu_device *adev = ring->adev;
return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR); return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_RPTR);
} }
/** /**
...@@ -1068,7 +1120,7 @@ static uint64_t vcn_v2_5_jpeg_ring_get_wptr(struct amdgpu_ring *ring) ...@@ -1068,7 +1120,7 @@ static uint64_t vcn_v2_5_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
if (ring->use_doorbell) if (ring->use_doorbell)
return adev->wb.wb[ring->wptr_offs]; return adev->wb.wb[ring->wptr_offs];
else else
return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR);
} }
/** /**
...@@ -1086,7 +1138,7 @@ static void vcn_v2_5_jpeg_ring_set_wptr(struct amdgpu_ring *ring) ...@@ -1086,7 +1138,7 @@ static void vcn_v2_5_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
} else { } else {
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); WREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
} }
} }
...@@ -1122,40 +1174,62 @@ static const struct amdgpu_ring_funcs vcn_v2_5_jpeg_ring_vm_funcs = { ...@@ -1122,40 +1174,62 @@ static const struct amdgpu_ring_funcs vcn_v2_5_jpeg_ring_vm_funcs = {
static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
{ {
adev->vcn.inst[0].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs; int i;
DRM_INFO("VCN decode is enabled in VM mode\n");
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
adev->vcn.inst[i].ring_dec.me = i;
DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i);
}
} }
static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev) static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
{ {
int i; int i, j;
for (i = 0; i < adev->vcn.num_enc_rings; ++i)
adev->vcn.inst[0].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
DRM_INFO("VCN encode is enabled in VM mode\n"); for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
adev->vcn.inst[j].ring_enc[i].me = j;
}
DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j);
}
} }
static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev) static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev)
{ {
adev->vcn.inst[0].ring_jpeg.funcs = &vcn_v2_5_jpeg_ring_vm_funcs; int i;
DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
adev->vcn.inst[i].ring_jpeg.funcs = &vcn_v2_5_jpeg_ring_vm_funcs;
adev->vcn.inst[i].ring_jpeg.me = i;
DRM_INFO("VCN(%d) jpeg decode is enabled in VM mode\n", i);
}
} }
static bool vcn_v2_5_is_idle(void *handle) static bool vcn_v2_5_is_idle(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int i, ret = 1;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
}
return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); return ret;
} }
static int vcn_v2_5_wait_for_idle(void *handle) static int vcn_v2_5_wait_for_idle(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret = 0; int i, ret = 0;
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
UVD_STATUS__IDLE, ret); SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
UVD_STATUS__IDLE, ret);
if (ret)
return ret;
}
return ret; return ret;
} }
...@@ -1209,20 +1283,34 @@ static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev, ...@@ -1209,20 +1283,34 @@ static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
struct amdgpu_irq_src *source, struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry) struct amdgpu_iv_entry *entry)
{ {
uint32_t ip_instance;
switch (entry->client_id) {
case SOC15_IH_CLIENTID_VCN:
ip_instance = 0;
break;
case SOC15_IH_CLIENTID_VCN1:
ip_instance = 1;
break;
default:
DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
return 0;
}
DRM_DEBUG("IH: VCN TRAP\n"); DRM_DEBUG("IH: VCN TRAP\n");
switch (entry->src_id) { switch (entry->src_id) {
case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
amdgpu_fence_process(&adev->vcn.inst[0].ring_dec); amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
break; break;
case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
amdgpu_fence_process(&adev->vcn.inst[0].ring_enc[0]); amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
break; break;
case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
amdgpu_fence_process(&adev->vcn.inst[0].ring_enc[1]); amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
break; break;
case VCN_2_0__SRCID__JPEG_DECODE: case VCN_2_0__SRCID__JPEG_DECODE:
amdgpu_fence_process(&adev->vcn.inst[0].ring_jpeg); amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_jpeg);
break; break;
default: default:
DRM_ERROR("Unhandled interrupt: %d %d\n", DRM_ERROR("Unhandled interrupt: %d %d\n",
...@@ -1240,8 +1328,12 @@ static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = { ...@@ -1240,8 +1328,12 @@ static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = {
static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev) static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
{ {
adev->vcn.inst[0].irq.num_types = adev->vcn.num_enc_rings + 2; int i;
adev->vcn.inst[0].irq.funcs = &vcn_v2_5_irq_funcs;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 2;
adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
}
} }
static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
......
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