Commit faa865f1 authored by Stephen Boyd's avatar Stephen Boyd

Merge tag 'clk-v4.15-samsung' of...

Merge tag 'clk-v4.15-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next

Pull Samsung clk driver updates from Sylwester Nawrocki:

Overall clk/samsung clean up and fixes. Removed remaining unused code
after removal of exynos4212 SoC support; dropped internal data structure
fields and related code for registering clkdev lookup entry for each
possible clock object, clkdev aliases could still be defined if needed
in a separate table; other minor fixes of the clock tree definitions.

* tag 'clk-v4.15-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: Remove obsolete clkdev alias support
  clk: samsung: Add explicit MPLL, EPLL clkdev aliases in S3C2443 driver
  clk: samsung: Rework clkdev alias handling in S3C2443 driver
  clk: samsung: Rework clkdev alias handling in Exynos5440 driver
  clk: samsung: Drop useless alias in Exynos5420 clk driver
  clk: samsung: Remove clkdev alias support in Exynos5250 clk driver
  clk: samsung: Remove double assignment of CLK_ARM_CLK in Exynos4 driver
  clk: samsung: Remove clkdev alias support in Exynos4 clk driver
  clk: samsung: Remove support for obsolete Exynos4212 CPU clock
  clk: samsung: Remove support for Exynos4212 SoCs in Exynos CLKOUT driver
  clk: samsung: Properly propagate flags in __PLL macro
  clk: samsung: Fix m2m scaler clock on Exynos542x
  clk: samsung: Delete a memory allocation error message in clk-cpu.c
parents f09a6b86 a4f21e9c
...@@ -457,8 +457,6 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, ...@@ -457,8 +457,6 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL); cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL);
if (!cpuclk->cfg) { if (!cpuclk->cfg) {
pr_err("%s: could not allocate memory for cpuclk data\n",
__func__);
ret = -ENOMEM; ret = -ENOMEM;
goto unregister_clk_nb; goto unregister_clk_nb;
} }
......
...@@ -144,8 +144,6 @@ static void __init exynos4_clkout_init(struct device_node *node) ...@@ -144,8 +144,6 @@ static void __init exynos4_clkout_init(struct device_node *node)
} }
CLK_OF_DECLARE_DRIVER(exynos4210_clkout, "samsung,exynos4210-pmu", CLK_OF_DECLARE_DRIVER(exynos4210_clkout, "samsung,exynos4210-pmu",
exynos4_clkout_init); exynos4_clkout_init);
CLK_OF_DECLARE_DRIVER(exynos4212_clkout, "samsung,exynos4212-pmu",
exynos4_clkout_init);
CLK_OF_DECLARE_DRIVER(exynos4412_clkout, "samsung,exynos4412-pmu", CLK_OF_DECLARE_DRIVER(exynos4412_clkout, "samsung,exynos4412-pmu",
exynos4_clkout_init); exynos4_clkout_init);
CLK_OF_DECLARE_DRIVER(exynos3250_clkout, "samsung,exynos3250-pmu", CLK_OF_DECLARE_DRIVER(exynos3250_clkout, "samsung,exynos3250-pmu",
......
...@@ -550,9 +550,8 @@ static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __ ...@@ -550,9 +550,8 @@ static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __
/* list of mux clocks supported in all exynos4 soc's */ /* list of mux clocks supported in all exynos4 soc's */
static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = { static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0, CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
"mout_apll"),
MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
...@@ -737,7 +736,7 @@ static const struct samsung_div_clock exynos4_div_clks[] __initconst = { ...@@ -737,7 +736,7 @@ static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3), DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3), DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3), DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3), DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3), DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6), DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
...@@ -853,11 +852,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { ...@@ -853,11 +852,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
/* list of gate clocks supported in all exynos4 soc's */ /* list of gate clocks supported in all exynos4 soc's */
static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = { static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
/*
* After all Exynos4 based platforms are migrated to use device tree,
* the device name and clock alias names specified below for some
* of the clocks can be removed.
*/
GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0), GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0), GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
...@@ -1205,20 +1199,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { ...@@ -1205,20 +1199,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
0), 0),
}; };
static const struct samsung_clock_alias exynos4_aliases[] __initconst = {
ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
ALIAS(CLK_ARM_CLK, NULL, "armclk"),
ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
};
static const struct samsung_clock_alias exynos4210_aliases[] __initconst = {
ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
};
static const struct samsung_clock_alias exynos4x12_aliases[] __initconst = {
ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
};
/* /*
* The parent of the fin_pll clock is selected by the XOM[0] bit. This bit * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
* resides in chipid register space, outside of the clock controller memory * resides in chipid register space, outside of the clock controller memory
...@@ -1355,14 +1335,14 @@ static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = ...@@ -1355,14 +1335,14 @@ static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst =
}; };
static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = { static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
[apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll", [apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
APLL_LOCK, APLL_CON0, "fout_apll", NULL), APLL_LOCK, APLL_CON0, NULL),
[mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL), E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL),
[epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll", [epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
EPLL_LOCK, EPLL_CON0, "fout_epll", NULL), EPLL_LOCK, EPLL_CON0, NULL),
[vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc", [vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL), VPLL_LOCK, VPLL_CON0, NULL),
}; };
static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
...@@ -1416,24 +1396,6 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = { ...@@ -1416,24 +1396,6 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
{ 0 }, { 0 },
}; };
static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
{ 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
{ 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
{ 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
{ 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
{ 0 },
};
#define E4412_CPU_DIV1(cores, hpm, copy) \ #define E4412_CPU_DIV1(cores, hpm, copy) \
(((cores) << 8) | ((hpm) << 4) | ((copy) << 0)) (((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
...@@ -1527,8 +1489,6 @@ static void __init exynos4_clk_init(struct device_node *np, ...@@ -1527,8 +1489,6 @@ static void __init exynos4_clk_init(struct device_node *np,
ARRAY_SIZE(exynos4210_div_clks)); ARRAY_SIZE(exynos4210_div_clks));
samsung_clk_register_gate(ctx, exynos4210_gate_clks, samsung_clk_register_gate(ctx, exynos4210_gate_clks,
ARRAY_SIZE(exynos4210_gate_clks)); ARRAY_SIZE(exynos4210_gate_clks));
samsung_clk_register_alias(ctx, exynos4210_aliases,
ARRAY_SIZE(exynos4210_aliases));
samsung_clk_register_fixed_factor(ctx, samsung_clk_register_fixed_factor(ctx,
exynos4210_fixed_factor_clks, exynos4210_fixed_factor_clks,
ARRAY_SIZE(exynos4210_fixed_factor_clks)); ARRAY_SIZE(exynos4210_fixed_factor_clks));
...@@ -1543,26 +1503,14 @@ static void __init exynos4_clk_init(struct device_node *np, ...@@ -1543,26 +1503,14 @@ static void __init exynos4_clk_init(struct device_node *np,
ARRAY_SIZE(exynos4x12_div_clks)); ARRAY_SIZE(exynos4x12_div_clks));
samsung_clk_register_gate(ctx, exynos4x12_gate_clks, samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
ARRAY_SIZE(exynos4x12_gate_clks)); ARRAY_SIZE(exynos4x12_gate_clks));
samsung_clk_register_alias(ctx, exynos4x12_aliases,
ARRAY_SIZE(exynos4x12_aliases));
samsung_clk_register_fixed_factor(ctx, samsung_clk_register_fixed_factor(ctx,
exynos4x12_fixed_factor_clks, exynos4x12_fixed_factor_clks,
ARRAY_SIZE(exynos4x12_fixed_factor_clks)); ARRAY_SIZE(exynos4x12_fixed_factor_clks));
if (of_machine_is_compatible("samsung,exynos4412")) {
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d), e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
} else {
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
} }
}
samsung_clk_register_alias(ctx, exynos4_aliases,
ARRAY_SIZE(exynos4_aliases));
if (soc == EXYNOS4X12) if (soc == EXYNOS4X12)
exynos4x12_core_down_clock(); exynos4x12_core_down_clock();
......
...@@ -293,14 +293,14 @@ static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = { ...@@ -293,14 +293,14 @@ static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
/* /*
* CMU_CPU * CMU_CPU
*/ */
MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
CLK_SET_RATE_PARENT, 0, "mout_apll"), CLK_SET_RATE_PARENT, 0),
MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
/* /*
* CMU_CORE * CMU_CORE
*/ */
MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
/* /*
* CMU_TOP * CMU_TOP
...@@ -391,7 +391,7 @@ static const struct samsung_div_clock exynos5250_div_clks[] __initconst = { ...@@ -391,7 +391,7 @@ static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
*/ */
DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3), DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"), DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
/* /*
* CMU_TOP * CMU_TOP
...@@ -743,10 +743,10 @@ static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = { ...@@ -743,10 +743,10 @@ static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
}; };
static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
[apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
APLL_LOCK, APLL_CON0, "fout_apll", NULL), APLL_CON0, NULL),
[mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL), MPLL_CON0, NULL),
[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
BPLL_CON0, NULL), BPLL_CON0, NULL),
[gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK, [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
......
...@@ -600,8 +600,7 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { ...@@ -600,8 +600,7 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
TOP_SPARE2, 4, 1), TOP_SPARE2, 4, 1),
MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
MUX_A(0, "mout_aclk400_mscl", mout_group1_p, MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
SRC_TOP0, 4, 2, "aclk400_mscl"),
MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
...@@ -998,7 +997,7 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { ...@@ -998,7 +997,7 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
GATE(0, "aclk400_isp", "mout_user_aclk400_isp", GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
GATE_BUS_TOP, 16, 0, 0), GATE_BUS_TOP, 16, 0, 0),
GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
GATE_BUS_TOP, 17, 0, 0), GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
......
...@@ -53,8 +53,7 @@ static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __ ...@@ -53,8 +53,7 @@ static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __
/* mux clocks */ /* mux clocks */
static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = { static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = {
MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p, MUX(CLK_ARM_CLK, "arm_clk", mout_armclk_p, CPU_CLK_STATUS, 0, 1),
CPU_CLK_STATUS, 0, 1, "armclk"),
}; };
/* divider clocks */ /* divider clocks */
...@@ -117,6 +116,13 @@ static const struct samsung_pll_clock exynos5440_plls[] __initconst = { ...@@ -117,6 +116,13 @@ static const struct samsung_pll_clock exynos5440_plls[] __initconst = {
PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL), PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL),
}; };
/*
* Clock aliases for legacy clkdev look-up.
*/
static const struct samsung_clock_alias exynos5440_aliases[] __initconst = {
ALIAS(CLK_ARM_CLK, NULL, "armclk"),
};
/* register exynos5440 clocks */ /* register exynos5440 clocks */
static void __init exynos5440_clk_init(struct device_node *np) static void __init exynos5440_clk_init(struct device_node *np)
{ {
...@@ -147,6 +153,8 @@ static void __init exynos5440_clk_init(struct device_node *np) ...@@ -147,6 +153,8 @@ static void __init exynos5440_clk_init(struct device_node *np)
ARRAY_SIZE(exynos5440_div_clks)); ARRAY_SIZE(exynos5440_div_clks));
samsung_clk_register_gate(ctx, exynos5440_gate_clks, samsung_clk_register_gate(ctx, exynos5440_gate_clks,
ARRAY_SIZE(exynos5440_gate_clks)); ARRAY_SIZE(exynos5440_gate_clks));
samsung_clk_register_alias(ctx, exynos5440_aliases,
ARRAY_SIZE(exynos5440_aliases));
samsung_clk_of_add_provider(np, ctx); samsung_clk_of_add_provider(np, ctx);
......
...@@ -1397,15 +1397,6 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, ...@@ -1397,15 +1397,6 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
} }
samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id);
if (!pll_clk->alias)
return;
ret = clk_hw_register_clkdev(&pll->hw, pll_clk->alias,
pll_clk->dev_name);
if (ret)
pr_err("%s: failed to register lookup for %s : %d",
__func__, pll_clk->name, ret);
} }
void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
......
...@@ -117,8 +117,8 @@ struct samsung_mux_clock s3c2443_common_muxes[] __initdata = { ...@@ -117,8 +117,8 @@ struct samsung_mux_clock s3c2443_common_muxes[] __initdata = {
MUX(0, "epllref", epllref_p, CLKSRC, 7, 2), MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1), MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1), MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
MUX_A(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1, "msysclk"), MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
MUX_A(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1, "armclk"), MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1),
MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2), MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
}; };
...@@ -189,6 +189,10 @@ struct samsung_gate_clock s3c2443_common_gates[] __initdata = { ...@@ -189,6 +189,10 @@ struct samsung_gate_clock s3c2443_common_gates[] __initdata = {
}; };
struct samsung_clock_alias s3c2443_common_aliases[] __initdata = { struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
ALIAS(MSYSCLK, NULL, "msysclk"),
ALIAS(ARMCLK, NULL, "armclk"),
ALIAS(MPLL, NULL, "mpll"),
ALIAS(EPLL, NULL, "epll"),
ALIAS(HCLK, NULL, "hclk"), ALIAS(HCLK, NULL, "hclk"),
ALIAS(HCLK_SSMC, NULL, "nand"), ALIAS(HCLK_SSMC, NULL, "nand"),
ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"), ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
...@@ -221,9 +225,9 @@ struct samsung_clock_alias s3c2443_common_aliases[] __initdata = { ...@@ -221,9 +225,9 @@ struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
/* S3C2416 specific clocks */ /* S3C2416 specific clocks */
static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = { static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = {
[mpll] = PLL(pll_6552_s3c2416, 0, "mpll", "mpllref", [mpll] = PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref",
LOCKCON0, MPLLCON, NULL), LOCKCON0, MPLLCON, NULL),
[epll] = PLL(pll_6553, 0, "epll", "epllref", [epll] = PLL(pll_6553, EPLL, "epll", "epllref",
LOCKCON1, EPLLCON, NULL), LOCKCON1, EPLLCON, NULL),
}; };
...@@ -275,9 +279,9 @@ struct samsung_clock_alias s3c2416_aliases[] __initdata = { ...@@ -275,9 +279,9 @@ struct samsung_clock_alias s3c2416_aliases[] __initdata = {
/* S3C2443 specific clocks */ /* S3C2443 specific clocks */
static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = { static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = {
[mpll] = PLL(pll_3000, 0, "mpll", "mpllref", [mpll] = PLL(pll_3000, MPLL, "mpll", "mpllref",
LOCKCON0, MPLLCON, NULL), LOCKCON0, MPLLCON, NULL),
[epll] = PLL(pll_2126, 0, "epll", "epllref", [epll] = PLL(pll_2126, EPLL, "epll", "epllref",
LOCKCON1, EPLLCON, NULL), LOCKCON1, EPLLCON, NULL),
}; };
......
...@@ -181,7 +181,7 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, ...@@ -181,7 +181,7 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
unsigned int nr_clk) unsigned int nr_clk)
{ {
struct clk_hw *clk_hw; struct clk_hw *clk_hw;
unsigned int idx, ret; unsigned int idx;
for (idx = 0; idx < nr_clk; idx++, list++) { for (idx = 0; idx < nr_clk; idx++, list++) {
clk_hw = clk_hw_register_mux(ctx->dev, list->name, clk_hw = clk_hw_register_mux(ctx->dev, list->name,
...@@ -195,15 +195,6 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, ...@@ -195,15 +195,6 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
} }
samsung_clk_add_lookup(ctx, clk_hw, list->id); samsung_clk_add_lookup(ctx, clk_hw, list->id);
/* register a clock lookup only if a clock alias is specified */
if (list->alias) {
ret = clk_hw_register_clkdev(clk_hw, list->alias,
list->dev_name);
if (ret)
pr_err("%s: failed to register lookup %s\n",
__func__, list->alias);
}
} }
} }
...@@ -213,7 +204,7 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, ...@@ -213,7 +204,7 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
unsigned int nr_clk) unsigned int nr_clk)
{ {
struct clk_hw *clk_hw; struct clk_hw *clk_hw;
unsigned int idx, ret; unsigned int idx;
for (idx = 0; idx < nr_clk; idx++, list++) { for (idx = 0; idx < nr_clk; idx++, list++) {
if (list->table) if (list->table)
...@@ -234,15 +225,6 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, ...@@ -234,15 +225,6 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
} }
samsung_clk_add_lookup(ctx, clk_hw, list->id); samsung_clk_add_lookup(ctx, clk_hw, list->id);
/* register a clock lookup only if a clock alias is specified */
if (list->alias) {
ret = clk_hw_register_clkdev(clk_hw, list->alias,
list->dev_name);
if (ret)
pr_err("%s: failed to register lookup %s\n",
__func__, list->alias);
}
} }
} }
...@@ -252,7 +234,7 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, ...@@ -252,7 +234,7 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
unsigned int nr_clk) unsigned int nr_clk)
{ {
struct clk_hw *clk_hw; struct clk_hw *clk_hw;
unsigned int idx, ret; unsigned int idx;
for (idx = 0; idx < nr_clk; idx++, list++) { for (idx = 0; idx < nr_clk; idx++, list++) {
clk_hw = clk_hw_register_gate(ctx->dev, list->name, list->parent_name, clk_hw = clk_hw_register_gate(ctx->dev, list->name, list->parent_name,
...@@ -264,15 +246,6 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, ...@@ -264,15 +246,6 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
continue; continue;
} }
/* register a clock lookup only if a clock alias is specified */
if (list->alias) {
ret = clk_hw_register_clkdev(clk_hw, list->alias,
list->dev_name);
if (ret)
pr_err("%s: failed to register lookup %s\n",
__func__, list->alias);
}
samsung_clk_add_lookup(ctx, clk_hw, list->id); samsung_clk_add_lookup(ctx, clk_hw, list->id);
} }
} }
......
...@@ -107,7 +107,6 @@ struct samsung_fixed_factor_clock { ...@@ -107,7 +107,6 @@ struct samsung_fixed_factor_clock {
/** /**
* struct samsung_mux_clock: information about mux clock * struct samsung_mux_clock: information about mux clock
* @id: platform specific id of the clock. * @id: platform specific id of the clock.
* @dev_name: name of the device to which this clock belongs.
* @name: name of this mux clock. * @name: name of this mux clock.
* @parent_names: array of pointer to parent clock names. * @parent_names: array of pointer to parent clock names.
* @num_parents: number of parents listed in @parent_names. * @num_parents: number of parents listed in @parent_names.
...@@ -116,11 +115,9 @@ struct samsung_fixed_factor_clock { ...@@ -116,11 +115,9 @@ struct samsung_fixed_factor_clock {
* @shift: starting bit location of the mux control bit-field in @reg. * @shift: starting bit location of the mux control bit-field in @reg.
* @width: width of the mux control bit-field in @reg. * @width: width of the mux control bit-field in @reg.
* @mux_flags: flags for mux-type clock. * @mux_flags: flags for mux-type clock.
* @alias: optional clock alias name to be assigned to this clock.
*/ */
struct samsung_mux_clock { struct samsung_mux_clock {
unsigned int id; unsigned int id;
const char *dev_name;
const char *name; const char *name;
const char *const *parent_names; const char *const *parent_names;
u8 num_parents; u8 num_parents;
...@@ -129,13 +126,11 @@ struct samsung_mux_clock { ...@@ -129,13 +126,11 @@ struct samsung_mux_clock {
u8 shift; u8 shift;
u8 width; u8 width;
u8 mux_flags; u8 mux_flags;
const char *alias;
}; };
#define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a) \ #define __MUX(_id, cname, pnames, o, s, w, f, mf) \
{ \ { \
.id = _id, \ .id = _id, \
.dev_name = dname, \
.name = cname, \ .name = cname, \
.parent_names = pnames, \ .parent_names = pnames, \
.num_parents = ARRAY_SIZE(pnames), \ .num_parents = ARRAY_SIZE(pnames), \
...@@ -144,36 +139,26 @@ struct samsung_mux_clock { ...@@ -144,36 +139,26 @@ struct samsung_mux_clock {
.shift = s, \ .shift = s, \
.width = w, \ .width = w, \
.mux_flags = mf, \ .mux_flags = mf, \
.alias = a, \
} }
#define MUX(_id, cname, pnames, o, s, w) \ #define MUX(_id, cname, pnames, o, s, w) \
__MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL) __MUX(_id, cname, pnames, o, s, w, 0, 0)
#define MUX_A(_id, cname, pnames, o, s, w, a) \
__MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \ #define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
__MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL) __MUX(_id, cname, pnames, o, s, w, f, mf)
#define MUX_FA(_id, cname, pnames, o, s, w, f, mf, a) \
__MUX(_id, NULL, cname, pnames, o, s, w, f, mf, a)
/** /**
* @id: platform specific id of the clock. * @id: platform specific id of the clock.
* struct samsung_div_clock: information about div clock * struct samsung_div_clock: information about div clock
* @dev_name: name of the device to which this clock belongs.
* @name: name of this div clock. * @name: name of this div clock.
* @parent_name: name of the parent clock. * @parent_name: name of the parent clock.
* @flags: optional flags for basic clock. * @flags: optional flags for basic clock.
* @offset: offset of the register for configuring the div. * @offset: offset of the register for configuring the div.
* @shift: starting bit location of the div control bit-field in @reg. * @shift: starting bit location of the div control bit-field in @reg.
* @div_flags: flags for div-type clock. * @div_flags: flags for div-type clock.
* @alias: optional clock alias name to be assigned to this clock.
*/ */
struct samsung_div_clock { struct samsung_div_clock {
unsigned int id; unsigned int id;
const char *dev_name;
const char *name; const char *name;
const char *parent_name; const char *parent_name;
unsigned long flags; unsigned long flags;
...@@ -181,14 +166,12 @@ struct samsung_div_clock { ...@@ -181,14 +166,12 @@ struct samsung_div_clock {
u8 shift; u8 shift;
u8 width; u8 width;
u8 div_flags; u8 div_flags;
const char *alias;
struct clk_div_table *table; struct clk_div_table *table;
}; };
#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t) \ #define __DIV(_id, cname, pname, o, s, w, f, df, t) \
{ \ { \
.id = _id, \ .id = _id, \
.dev_name = dname, \
.name = cname, \ .name = cname, \
.parent_name = pname, \ .parent_name = pname, \
.flags = f, \ .flags = f, \
...@@ -196,70 +179,51 @@ struct samsung_div_clock { ...@@ -196,70 +179,51 @@ struct samsung_div_clock {
.shift = s, \ .shift = s, \
.width = w, \ .width = w, \
.div_flags = df, \ .div_flags = df, \
.alias = a, \
.table = t, \ .table = t, \
} }
#define DIV(_id, cname, pname, o, s, w) \ #define DIV(_id, cname, pname, o, s, w) \
__DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL) __DIV(_id, cname, pname, o, s, w, 0, 0, NULL)
#define DIV_A(_id, cname, pname, o, s, w, a) \
__DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
#define DIV_F(_id, cname, pname, o, s, w, f, df) \ #define DIV_F(_id, cname, pname, o, s, w, f, df) \
__DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL) __DIV(_id, cname, pname, o, s, w, f, df, NULL)
#define DIV_T(_id, cname, pname, o, s, w, t) \ #define DIV_T(_id, cname, pname, o, s, w, t) \
__DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t) __DIV(_id, cname, pname, o, s, w, 0, 0, t)
/** /**
* struct samsung_gate_clock: information about gate clock * struct samsung_gate_clock: information about gate clock
* @id: platform specific id of the clock. * @id: platform specific id of the clock.
* @dev_name: name of the device to which this clock belongs.
* @name: name of this gate clock. * @name: name of this gate clock.
* @parent_name: name of the parent clock. * @parent_name: name of the parent clock.
* @flags: optional flags for basic clock. * @flags: optional flags for basic clock.
* @offset: offset of the register for configuring the gate. * @offset: offset of the register for configuring the gate.
* @bit_idx: bit index of the gate control bit-field in @reg. * @bit_idx: bit index of the gate control bit-field in @reg.
* @gate_flags: flags for gate-type clock. * @gate_flags: flags for gate-type clock.
* @alias: optional clock alias name to be assigned to this clock.
*/ */
struct samsung_gate_clock { struct samsung_gate_clock {
unsigned int id; unsigned int id;
const char *dev_name;
const char *name; const char *name;
const char *parent_name; const char *parent_name;
unsigned long flags; unsigned long flags;
unsigned long offset; unsigned long offset;
u8 bit_idx; u8 bit_idx;
u8 gate_flags; u8 gate_flags;
const char *alias;
}; };
#define __GATE(_id, dname, cname, pname, o, b, f, gf, a) \ #define __GATE(_id, cname, pname, o, b, f, gf) \
{ \ { \
.id = _id, \ .id = _id, \
.dev_name = dname, \
.name = cname, \ .name = cname, \
.parent_name = pname, \ .parent_name = pname, \
.flags = f, \ .flags = f, \
.offset = o, \ .offset = o, \
.bit_idx = b, \ .bit_idx = b, \
.gate_flags = gf, \ .gate_flags = gf, \
.alias = a, \
} }
#define GATE(_id, cname, pname, o, b, f, gf) \ #define GATE(_id, cname, pname, o, b, f, gf) \
__GATE(_id, NULL, cname, pname, o, b, f, gf, NULL) __GATE(_id, cname, pname, o, b, f, gf)
#define GATE_A(_id, cname, pname, o, b, f, gf, a) \
__GATE(_id, NULL, cname, pname, o, b, f, gf, a)
#define GATE_D(_id, dname, cname, pname, o, b, f, gf) \
__GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a) \
__GATE(_id, dname, cname, pname, o, b, f, gf, a)
#define PNAME(x) static const char * const x[] __initconst #define PNAME(x) static const char * const x[] __initconst
...@@ -276,18 +240,15 @@ struct samsung_clk_reg_dump { ...@@ -276,18 +240,15 @@ struct samsung_clk_reg_dump {
/** /**
* struct samsung_pll_clock: information about pll clock * struct samsung_pll_clock: information about pll clock
* @id: platform specific id of the clock. * @id: platform specific id of the clock.
* @dev_name: name of the device to which this clock belongs.
* @name: name of this pll clock. * @name: name of this pll clock.
* @parent_name: name of the parent clock. * @parent_name: name of the parent clock.
* @flags: optional flags for basic clock. * @flags: optional flags for basic clock.
* @con_offset: offset of the register for configuring the PLL. * @con_offset: offset of the register for configuring the PLL.
* @lock_offset: offset of the register for locking the PLL. * @lock_offset: offset of the register for locking the PLL.
* @type: Type of PLL to be registered. * @type: Type of PLL to be registered.
* @alias: optional clock alias name to be assigned to this clock.
*/ */
struct samsung_pll_clock { struct samsung_pll_clock {
unsigned int id; unsigned int id;
const char *dev_name;
const char *name; const char *name;
const char *parent_name; const char *parent_name;
unsigned long flags; unsigned long flags;
...@@ -295,31 +256,23 @@ struct samsung_pll_clock { ...@@ -295,31 +256,23 @@ struct samsung_pll_clock {
int lock_offset; int lock_offset;
enum samsung_pll_type type; enum samsung_pll_type type;
const struct samsung_pll_rate_table *rate_table; const struct samsung_pll_rate_table *rate_table;
const char *alias;
}; };
#define __PLL(_typ, _id, _dname, _name, _pname, _flags, _lock, _con, \ #define __PLL(_typ, _id, _name, _pname, _flags, _lock, _con, _rtable) \
_rtable, _alias) \
{ \ { \
.id = _id, \ .id = _id, \
.type = _typ, \ .type = _typ, \
.dev_name = _dname, \
.name = _name, \ .name = _name, \
.parent_name = _pname, \ .parent_name = _pname, \
.flags = CLK_GET_RATE_NOCACHE, \ .flags = _flags, \
.con_offset = _con, \ .con_offset = _con, \
.lock_offset = _lock, \ .lock_offset = _lock, \
.rate_table = _rtable, \ .rate_table = _rtable, \
.alias = _alias, \
} }
#define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \ #define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \
__PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \ __PLL(_typ, _id, _name, _pname, CLK_GET_RATE_NOCACHE, _lock, \
_lock, _con, _rtable, _name) _con, _rtable)
#define PLL_A(_typ, _id, _name, _pname, _lock, _con, _alias, _rtable) \
__PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
_lock, _con, _rtable, _alias)
struct samsung_clock_reg_cache { struct samsung_clock_reg_cache {
struct list_head node; struct list_head node;
......
...@@ -26,6 +26,8 @@ ...@@ -26,6 +26,8 @@
#define ARMCLK 4 #define ARMCLK 4
#define HCLK 5 #define HCLK 5
#define PCLK 6 #define PCLK 6
#define MPLL 7
#define EPLL 8
/* Special clocks */ /* Special clocks */
#define SCLK_HSSPI0 16 #define SCLK_HSSPI0 16
......
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