Commit fb25ca37 authored by Jacopo Mondi's avatar Jacopo Mondi Committed by Mauro Carvalho Chehab

media: rcar-vin: Mask VNCSI_IFMD register

The VNCSI_IFMD register controls the data expansion mode and the
channel routing between the CSI-2 receivers and VIN instances.

According to the chip manual revision 2.20 not all fields are available
for all the SoCs:
- V3M, V3H and E3 do not support the DES1 field has they do not feature
  a CSI20 receiver.
- D3 only supports parallel input, and the whole register shall always
  be written as 0.

Inspect the per-SoC channel routing table where the available CSI-2
instances are reported and configure VNCSI_IFMD accordingly.

This patch supports this BSP change commit:

https://github.com/renesas-rcar/linux-bsp/commit/f54697394457
("media: rcar-vin: Fix VnCSI_IFMD register access for r8a77990")

[hverkuil: replace BSP commit ID with BSP URL]
Reviewed-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Suggested-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: default avatarJacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent aa821b2b
...@@ -1448,7 +1448,9 @@ int rvin_dma_register(struct rvin_dev *vin, int irq) ...@@ -1448,7 +1448,9 @@ int rvin_dma_register(struct rvin_dev *vin, int irq)
*/ */
int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel) int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel)
{ {
u32 ifmd, vnmc; const struct rvin_group_route *route;
u32 ifmd = 0;
u32 vnmc;
int ret; int ret;
ret = pm_runtime_get_sync(vin->dev); ret = pm_runtime_get_sync(vin->dev);
...@@ -1461,9 +1463,26 @@ int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel) ...@@ -1461,9 +1463,26 @@ int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel)
vnmc = rvin_read(vin, VNMC_REG); vnmc = rvin_read(vin, VNMC_REG);
rvin_write(vin, vnmc & ~VNMC_VUP, VNMC_REG); rvin_write(vin, vnmc & ~VNMC_VUP, VNMC_REG);
ifmd = VNCSI_IFMD_DES1 | VNCSI_IFMD_DES0 | VNCSI_IFMD_CSI_CHSEL(chsel); /*
* Set data expansion mode to "pad with 0s" by inspecting the routes
* table to find out which bit fields are available in the IFMD
* register. IFMD_DES1 controls data expansion mode for CSI20/21,
* IFMD_DES0 controls data expansion mode for CSI40/41.
*/
for (route = vin->info->routes; route->mask; route++) {
if (route->csi == RVIN_CSI20 || route->csi == RVIN_CSI21)
ifmd |= VNCSI_IFMD_DES1;
else
ifmd |= VNCSI_IFMD_DES0;
if (ifmd == (VNCSI_IFMD_DES0 | VNCSI_IFMD_DES1))
break;
}
if (ifmd) {
ifmd |= VNCSI_IFMD_CSI_CHSEL(chsel);
rvin_write(vin, ifmd, VNCSI_IFMD_REG); rvin_write(vin, ifmd, VNCSI_IFMD_REG);
}
vin_dbg(vin, "Set IFMD 0x%x\n", ifmd); vin_dbg(vin, "Set IFMD 0x%x\n", ifmd);
......
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