Commit fb575510 authored by Rajvi Jingar's avatar Rajvi Jingar Committed by Hans de Goede

platform/x86/intel/pmc: Alder Lake PCH slp_s0_residency fix

For platforms with Alder Lake PCH (Alder Lake S and Raptor Lake S) the
slp_s0_residency attribute has been reporting the wrong value. Unlike other
platforms, ADL PCH does not have a counter for the time that the SLP_S0
signal was asserted. Instead, firmware uses the aggregate of the Low Power
Mode (LPM) substate counters as the S0ix value.  Since the LPM counters run
at a different frequency, this lead to misreporting of the S0ix time.

Add a check for Alder Lake PCH and adjust the frequency accordingly when
display slp_s0_residency.

Fixes: bbab3110 ("platform/x86/intel: pmc/core: Add Alderlake support to pmc core driver")
Signed-off-by: default avatarRajvi Jingar <rajvi.jingar@linux.intel.com>
Signed-off-by: default avatarDavid E. Box <david.e.box@linux.intel.com>
Reviewed-by: default avatarRajneesh Bhardwaj <irenic.rajneesh@gmail.com>
Reviewed-by: default avatarAndy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20230320212029.3154407-1-david.e.box@linux.intel.comReviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent acd0acb8
......@@ -66,6 +66,17 @@ static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset,
static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 value)
{
/*
* ADL PCH does not have the SLP_S0 counter and LPM Residency counters are
* used as a workaround which uses 30.5 usec tick. All other client
* programs have the legacy SLP_S0 residency counter that is using the 122
* usec tick.
*/
const int lpm_adj_x2 = pmcdev->map->lpm_res_counter_step_x2;
if (pmcdev->map == &adl_reg_map)
return (u64)value * GET_X2_COUNTER((u64)lpm_adj_x2);
else
return (u64)value * pmcdev->map->slp_s0_res_counter_step;
}
......
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