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Commit fc599211 authored by Robert Bragg's avatar Robert Bragg Committed by Ben Widawsky
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drm/i915/perf: Add more OA configs for BDW, CHV, SKL + BXT 

These are auto generated from an XML description of metric sets,
currently maintained in gputop, ref:

 https://github.com/rib/gputop
 > gputop-data/oa-*.xml
 > scripts/i915-perf-kernelgen.py

 $ make -C gputop-data -f Makefile.xml
Signed-off-by: default avatarRobert Bragg <robert@sixbynine.org>
Signed-off-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
parent 19f81df2
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Inline Side-by-side
Showing with 19161 additions and 188 deletions
drivers/gpu/drm/i915/i915_drv.h
View file @ fc599211
...@@ -2418,8 +2418,8 @@ struct drm_i915_private { ...@@ -2418,8 +2418,8 @@ struct drm_i915_private {
int metrics_set; int metrics_set;
const struct i915_oa_reg *mux_regs[2]; const struct i915_oa_reg *mux_regs[6];
int mux_regs_lens[2]; int mux_regs_lens[6];
int n_mux_configs; int n_mux_configs;
const struct i915_oa_reg *b_counter_regs; const struct i915_oa_reg *b_counter_regs;
......
drivers/gpu/drm/i915/i915_oa_bdw.c
View file @ fc599211
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/gpu/drm/i915/i915_oa_bxt.c
View file @ fc599211
...@@ -33,9 +33,23 @@ ...@@ -33,9 +33,23 @@
enum metric_set_id { enum metric_set_id {
METRIC_SET_ID_RENDER_BASIC = 1, METRIC_SET_ID_RENDER_BASIC = 1,
METRIC_SET_ID_COMPUTE_BASIC,
METRIC_SET_ID_RENDER_PIPE_PROFILE,
METRIC_SET_ID_MEMORY_READS,
METRIC_SET_ID_MEMORY_WRITES,
METRIC_SET_ID_COMPUTE_EXTENDED,
METRIC_SET_ID_COMPUTE_L3_CACHE,
METRIC_SET_ID_HDC_AND_SF,
METRIC_SET_ID_L3_1,
METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
METRIC_SET_ID_SAMPLER,
METRIC_SET_ID_TDL_1,
METRIC_SET_ID_TDL_2,
METRIC_SET_ID_COMPUTE_EXTRA,
METRIC_SET_ID_TEST_OA,
}; };
int i915_oa_n_builtin_metric_sets_bxt = 1; int i915_oa_n_builtin_metric_sets_bxt = 15;
static const struct i915_oa_reg b_counter_config_render_basic[] = { static const struct i915_oa_reg b_counter_config_render_basic[] = {
{ _MMIO(0x2710), 0x00000000 }, { _MMIO(0x2710), 0x00000000 },
...@@ -156,6 +170,1622 @@ get_render_basic_mux_config(struct drm_i915_private *dev_priv, ...@@ -156,6 +170,1622 @@ get_render_basic_mux_config(struct drm_i915_private *dev_priv,
return n; return n;
} }
static const struct i915_oa_reg b_counter_config_compute_basic[] = {
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x00800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2740), 0x00000000 },
};
static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00000003 },
{ _MMIO(0xe658), 0x00002001 },
{ _MMIO(0xe758), 0x00778008 },
{ _MMIO(0xe45c), 0x00088078 },
{ _MMIO(0xe55c), 0x00808708 },
{ _MMIO(0xe65c), 0x00a08908 },
};
static const struct i915_oa_reg mux_config_compute_basic[] = {
{ _MMIO(0x9888), 0x104f00e0 },
{ _MMIO(0x9888), 0x124f1c00 },
{ _MMIO(0x9888), 0x39900340 },
{ _MMIO(0x9888), 0x3f900c00 },
{ _MMIO(0x9888), 0x41900000 },
{ _MMIO(0x9888), 0x002d5000 },
{ _MMIO(0x9888), 0x062d4000 },
{ _MMIO(0x9888), 0x082d4000 },
{ _MMIO(0x9888), 0x0a2d1000 },
{ _MMIO(0x9888), 0x0c2d5000 },
{ _MMIO(0x9888), 0x0e2d4000 },
{ _MMIO(0x9888), 0x0c2e1400 },
{ _MMIO(0x9888), 0x0e2e5100 },
{ _MMIO(0x9888), 0x102e0114 },
{ _MMIO(0x9888), 0x044cc000 },
{ _MMIO(0x9888), 0x0a4c8000 },
{ _MMIO(0x9888), 0x0c4c8000 },
{ _MMIO(0x9888), 0x0e4c4000 },
{ _MMIO(0x9888), 0x104c8000 },
{ _MMIO(0x9888), 0x124c8000 },
{ _MMIO(0x9888), 0x164c2000 },
{ _MMIO(0x9888), 0x004ea000 },
{ _MMIO(0x9888), 0x064e8000 },
{ _MMIO(0x9888), 0x084e8000 },
{ _MMIO(0x9888), 0x0a4e2000 },
{ _MMIO(0x9888), 0x0c4ea000 },
{ _MMIO(0x9888), 0x0e4e8000 },
{ _MMIO(0x9888), 0x004f6b42 },
{ _MMIO(0x9888), 0x064f6200 },
{ _MMIO(0x9888), 0x084f4100 },
{ _MMIO(0x9888), 0x0a4f0061 },
{ _MMIO(0x9888), 0x0c4f6c4c },
{ _MMIO(0x9888), 0x0e4f4b00 },
{ _MMIO(0x9888), 0x1a4f0000 },
{ _MMIO(0x9888), 0x1c4f0000 },
{ _MMIO(0x9888), 0x180f5000 },
{ _MMIO(0x9888), 0x1a0f8800 },
{ _MMIO(0x9888), 0x1c0f08a2 },
{ _MMIO(0x9888), 0x182c4000 },
{ _MMIO(0x9888), 0x1c2c1451 },
{ _MMIO(0x9888), 0x1e2c0001 },
{ _MMIO(0x9888), 0x1a2c0010 },
{ _MMIO(0x9888), 0x01938000 },
{ _MMIO(0x9888), 0x0f938000 },
{ _MMIO(0x9888), 0x19938a28 },
{ _MMIO(0x9888), 0x03938000 },
{ _MMIO(0x9888), 0x19900177 },
{ _MMIO(0x9888), 0x1b900178 },
{ _MMIO(0x9888), 0x1d900125 },
{ _MMIO(0x9888), 0x1f900123 },
{ _MMIO(0x9888), 0x35900000 },
{ _MMIO(0x9888), 0x13904000 },
{ _MMIO(0x9888), 0x21904000 },
{ _MMIO(0x9888), 0x25904000 },
{ _MMIO(0x9888), 0x27904000 },
{ _MMIO(0x9888), 0x2b904000 },
{ _MMIO(0x9888), 0x2d904000 },
{ _MMIO(0x9888), 0x31904000 },
{ _MMIO(0x9888), 0x15904000 },
{ _MMIO(0x9888), 0x53901000 },
{ _MMIO(0x9888), 0x43900000 },
{ _MMIO(0x9888), 0x55900111 },
{ _MMIO(0x9888), 0x47900000 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900000 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x4b900000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4d900000 },
{ _MMIO(0x9888), 0x45900000 },
};
static int
get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_basic;
lens[n] = ARRAY_SIZE(mux_config_compute_basic);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2770), 0x0007ffea },
{ _MMIO(0x2774), 0x00007ffc },
{ _MMIO(0x2778), 0x0007affa },
{ _MMIO(0x277c), 0x0000f5fd },
{ _MMIO(0x2780), 0x00079ffa },
{ _MMIO(0x2784), 0x0000f3fb },
{ _MMIO(0x2788), 0x0007bf7a },
{ _MMIO(0x278c), 0x0000f7e7 },
{ _MMIO(0x2790), 0x0007fefa },
{ _MMIO(0x2794), 0x0000f7cf },
{ _MMIO(0x2798), 0x00077ffa },
{ _MMIO(0x279c), 0x0000efdf },
{ _MMIO(0x27a0), 0x0006fffa },
{ _MMIO(0x27a4), 0x0000cfbf },
{ _MMIO(0x27a8), 0x0003fffa },
{ _MMIO(0x27ac), 0x00005f7f },
};
static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00015014 },
{ _MMIO(0xe658), 0x00025024 },
{ _MMIO(0xe758), 0x00035034 },
{ _MMIO(0xe45c), 0x00045044 },
{ _MMIO(0xe55c), 0x00055054 },
{ _MMIO(0xe65c), 0x00065064 },
};
static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
{ _MMIO(0x9888), 0x0c2e001f },
{ _MMIO(0x9888), 0x0a2f0000 },
{ _MMIO(0x9888), 0x10186800 },
{ _MMIO(0x9888), 0x11810019 },
{ _MMIO(0x9888), 0x15810013 },
{ _MMIO(0x9888), 0x13820020 },
{ _MMIO(0x9888), 0x11830020 },
{ _MMIO(0x9888), 0x17840000 },
{ _MMIO(0x9888), 0x11860007 },
{ _MMIO(0x9888), 0x21860000 },
{ _MMIO(0x9888), 0x178703e0 },
{ _MMIO(0x9888), 0x0c2d8000 },
{ _MMIO(0x9888), 0x042d4000 },
{ _MMIO(0x9888), 0x062d1000 },
{ _MMIO(0x9888), 0x022e5400 },
{ _MMIO(0x9888), 0x002e0000 },
{ _MMIO(0x9888), 0x0e2e0080 },
{ _MMIO(0x9888), 0x082f0040 },
{ _MMIO(0x9888), 0x002f0000 },
{ _MMIO(0x9888), 0x06143000 },
{ _MMIO(0x9888), 0x06174000 },
{ _MMIO(0x9888), 0x06180012 },
{ _MMIO(0x9888), 0x00180000 },
{ _MMIO(0x9888), 0x0d804000 },
{ _MMIO(0x9888), 0x0f804000 },
{ _MMIO(0x9888), 0x05804000 },
{ _MMIO(0x9888), 0x09810200 },
{ _MMIO(0x9888), 0x0b810030 },
{ _MMIO(0x9888), 0x03810003 },
{ _MMIO(0x9888), 0x21819140 },
{ _MMIO(0x9888), 0x23819050 },
{ _MMIO(0x9888), 0x25810018 },
{ _MMIO(0x9888), 0x0b820980 },
{ _MMIO(0x9888), 0x03820d80 },
{ _MMIO(0x9888), 0x11820000 },
{ _MMIO(0x9888), 0x0182c000 },
{ _MMIO(0x9888), 0x07828000 },
{ _MMIO(0x9888), 0x09824000 },
{ _MMIO(0x9888), 0x0f828000 },
{ _MMIO(0x9888), 0x0d830004 },
{ _MMIO(0x9888), 0x0583000c },
{ _MMIO(0x9888), 0x0f831000 },
{ _MMIO(0x9888), 0x01848072 },
{ _MMIO(0x9888), 0x11840000 },
{ _MMIO(0x9888), 0x07848000 },
{ _MMIO(0x9888), 0x09844000 },
{ _MMIO(0x9888), 0x0f848000 },
{ _MMIO(0x9888), 0x07860000 },
{ _MMIO(0x9888), 0x09860092 },
{ _MMIO(0x9888), 0x0f860400 },
{ _MMIO(0x9888), 0x01869100 },
{ _MMIO(0x9888), 0x0f870065 },
{ _MMIO(0x9888), 0x01870000 },
{ _MMIO(0x9888), 0x19930800 },
{ _MMIO(0x9888), 0x0b938000 },
{ _MMIO(0x9888), 0x0d938000 },
{ _MMIO(0x9888), 0x1b952000 },
{ _MMIO(0x9888), 0x1d955055 },
{ _MMIO(0x9888), 0x1f951455 },
{ _MMIO(0x9888), 0x0992a000 },
{ _MMIO(0x9888), 0x0f928000 },
{ _MMIO(0x9888), 0x1192a800 },
{ _MMIO(0x9888), 0x1392028a },
{ _MMIO(0x9888), 0x0b92a000 },
{ _MMIO(0x9888), 0x0d922000 },
{ _MMIO(0x9888), 0x13908000 },
{ _MMIO(0x9888), 0x21908000 },
{ _MMIO(0x9888), 0x23908000 },
{ _MMIO(0x9888), 0x25908000 },
{ _MMIO(0x9888), 0x27908000 },
{ _MMIO(0x9888), 0x29908000 },
{ _MMIO(0x9888), 0x2b908000 },
{ _MMIO(0x9888), 0x2d904000 },
{ _MMIO(0x9888), 0x2f908000 },
{ _MMIO(0x9888), 0x31908000 },
{ _MMIO(0x9888), 0x15908000 },
{ _MMIO(0x9888), 0x17908000 },
{ _MMIO(0x9888), 0x19908000 },
{ _MMIO(0x9888), 0x1b908000 },
{ _MMIO(0x9888), 0x1d904000 },
{ _MMIO(0x9888), 0x1f904000 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x43900c01 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x47900000 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900863 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x4b900061 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4d900000 },
{ _MMIO(0x9888), 0x45900c22 },
};
static int
get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_render_pipe_profile;
lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_memory_reads[] = {
{ _MMIO(0x272c), 0xffffffff },
{ _MMIO(0x2728), 0xffffffff },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x271c), 0xffffffff },
{ _MMIO(0x2718), 0xffffffff },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x274c), 0x86543210 },
{ _MMIO(0x2748), 0x86543210 },
{ _MMIO(0x2744), 0x00006667 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x275c), 0x86543210 },
{ _MMIO(0x2758), 0x86543210 },
{ _MMIO(0x2754), 0x00006465 },
{ _MMIO(0x2750), 0x00000000 },
{ _MMIO(0x2770), 0x0007f81a },
{ _MMIO(0x2774), 0x0000fe00 },
{ _MMIO(0x2778), 0x0007f82a },
{ _MMIO(0x277c), 0x0000fe00 },
{ _MMIO(0x2780), 0x0007f872 },
{ _MMIO(0x2784), 0x0000fe00 },
{ _MMIO(0x2788), 0x0007f8ba },
{ _MMIO(0x278c), 0x0000fe00 },
{ _MMIO(0x2790), 0x0007f87a },
{ _MMIO(0x2794), 0x0000fe00 },
{ _MMIO(0x2798), 0x0007f8ea },
{ _MMIO(0x279c), 0x0000fe00 },
{ _MMIO(0x27a0), 0x0007f8e2 },
{ _MMIO(0x27a4), 0x0000fe00 },
{ _MMIO(0x27a8), 0x0007f8f2 },
{ _MMIO(0x27ac), 0x0000fe00 },
};
static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00015014 },
{ _MMIO(0xe658), 0x00025024 },
{ _MMIO(0xe758), 0x00035034 },
{ _MMIO(0xe45c), 0x00045044 },
{ _MMIO(0xe55c), 0x00055054 },
{ _MMIO(0xe65c), 0x00065064 },
};
static const struct i915_oa_reg mux_config_memory_reads[] = {
{ _MMIO(0x9888), 0x19800343 },
{ _MMIO(0x9888), 0x39900340 },
{ _MMIO(0x9888), 0x3f901000 },
{ _MMIO(0x9888), 0x41900003 },
{ _MMIO(0x9888), 0x03803180 },
{ _MMIO(0x9888), 0x058035e2 },
{ _MMIO(0x9888), 0x0780006a },
{ _MMIO(0x9888), 0x11800000 },
{ _MMIO(0x9888), 0x2181a000 },
{ _MMIO(0x9888), 0x2381000a },
{ _MMIO(0x9888), 0x1d950550 },
{ _MMIO(0x9888), 0x0b928000 },
{ _MMIO(0x9888), 0x0d92a000 },
{ _MMIO(0x9888), 0x0f922000 },
{ _MMIO(0x9888), 0x13900170 },
{ _MMIO(0x9888), 0x21900171 },
{ _MMIO(0x9888), 0x23900172 },
{ _MMIO(0x9888), 0x25900173 },
{ _MMIO(0x9888), 0x27900174 },
{ _MMIO(0x9888), 0x29900175 },
{ _MMIO(0x9888), 0x2b900176 },
{ _MMIO(0x9888), 0x2d900177 },
{ _MMIO(0x9888), 0x2f90017f },
{ _MMIO(0x9888), 0x31900125 },
{ _MMIO(0x9888), 0x15900123 },
{ _MMIO(0x9888), 0x17900121 },
{ _MMIO(0x9888), 0x35900000 },
{ _MMIO(0x9888), 0x19908000 },
{ _MMIO(0x9888), 0x1b908000 },
{ _MMIO(0x9888), 0x1d908000 },
{ _MMIO(0x9888), 0x1f908000 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x43901084 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x47901080 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49901084 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x4b901084 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4d900004 },
{ _MMIO(0x9888), 0x45900000 },
};
static int
get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_memory_reads;
lens[n] = ARRAY_SIZE(mux_config_memory_reads);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_memory_writes[] = {
{ _MMIO(0x272c), 0xffffffff },
{ _MMIO(0x2728), 0xffffffff },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x271c), 0xffffffff },
{ _MMIO(0x2718), 0xffffffff },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x274c), 0x86543210 },
{ _MMIO(0x2748), 0x86543210 },
{ _MMIO(0x2744), 0x00006667 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x275c), 0x86543210 },
{ _MMIO(0x2758), 0x86543210 },
{ _MMIO(0x2754), 0x00006465 },
{ _MMIO(0x2750), 0x00000000 },
{ _MMIO(0x2770), 0x0007f81a },
{ _MMIO(0x2774), 0x0000fe00 },
{ _MMIO(0x2778), 0x0007f82a },
{ _MMIO(0x277c), 0x0000fe00 },
{ _MMIO(0x2780), 0x0007f822 },
{ _MMIO(0x2784), 0x0000fe00 },
{ _MMIO(0x2788), 0x0007f8ba },
{ _MMIO(0x278c), 0x0000fe00 },
{ _MMIO(0x2790), 0x0007f87a },
{ _MMIO(0x2794), 0x0000fe00 },
{ _MMIO(0x2798), 0x0007f8ea },
{ _MMIO(0x279c), 0x0000fe00 },
{ _MMIO(0x27a0), 0x0007f8e2 },
{ _MMIO(0x27a4), 0x0000fe00 },
{ _MMIO(0x27a8), 0x0007f8f2 },
{ _MMIO(0x27ac), 0x0000fe00 },
};
static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00015014 },
{ _MMIO(0xe658), 0x00025024 },
{ _MMIO(0xe758), 0x00035034 },
{ _MMIO(0xe45c), 0x00045044 },
{ _MMIO(0xe55c), 0x00055054 },
{ _MMIO(0xe65c), 0x00065064 },
};
static const struct i915_oa_reg mux_config_memory_writes[] = {
{ _MMIO(0x9888), 0x19800343 },
{ _MMIO(0x9888), 0x39900340 },
{ _MMIO(0x9888), 0x3f900000 },
{ _MMIO(0x9888), 0x41900080 },
{ _MMIO(0x9888), 0x03803180 },
{ _MMIO(0x9888), 0x058035e2 },
{ _MMIO(0x9888), 0x0780006a },
{ _MMIO(0x9888), 0x11800000 },
{ _MMIO(0x9888), 0x2181a000 },
{ _MMIO(0x9888), 0x2381000a },
{ _MMIO(0x9888), 0x1d950550 },
{ _MMIO(0x9888), 0x0b928000 },
{ _MMIO(0x9888), 0x0d92a000 },
{ _MMIO(0x9888), 0x0f922000 },
{ _MMIO(0x9888), 0x13900180 },
{ _MMIO(0x9888), 0x21900181 },
{ _MMIO(0x9888), 0x23900182 },
{ _MMIO(0x9888), 0x25900183 },
{ _MMIO(0x9888), 0x27900184 },
{ _MMIO(0x9888), 0x29900185 },
{ _MMIO(0x9888), 0x2b900186 },
{ _MMIO(0x9888), 0x2d900187 },
{ _MMIO(0x9888), 0x2f900170 },
{ _MMIO(0x9888), 0x31900125 },
{ _MMIO(0x9888), 0x15900123 },
{ _MMIO(0x9888), 0x17900121 },
{ _MMIO(0x9888), 0x35900000 },
{ _MMIO(0x9888), 0x19908000 },
{ _MMIO(0x9888), 0x1b908000 },
{ _MMIO(0x9888), 0x1d908000 },
{ _MMIO(0x9888), 0x1f908000 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x43901084 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x47901080 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49901084 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x4b901084 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4d900004 },
{ _MMIO(0x9888), 0x45900000 },
};
static int
get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_memory_writes;
lens[n] = ARRAY_SIZE(mux_config_memory_writes);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_compute_extended[] = {
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2770), 0x0007fc2a },
{ _MMIO(0x2774), 0x0000bf00 },
{ _MMIO(0x2778), 0x0007fc6a },
{ _MMIO(0x277c), 0x0000bf00 },
{ _MMIO(0x2780), 0x0007fc92 },
{ _MMIO(0x2784), 0x0000bf00 },
{ _MMIO(0x2788), 0x0007fca2 },
{ _MMIO(0x278c), 0x0000bf00 },
{ _MMIO(0x2790), 0x0007fc32 },
{ _MMIO(0x2794), 0x0000bf00 },
{ _MMIO(0x2798), 0x0007fc9a },
{ _MMIO(0x279c), 0x0000bf00 },
{ _MMIO(0x27a0), 0x0007fe6a },
{ _MMIO(0x27a4), 0x0000bf00 },
{ _MMIO(0x27a8), 0x0007fe7a },
{ _MMIO(0x27ac), 0x0000bf00 },
};
static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00000003 },
{ _MMIO(0xe658), 0x00002001 },
{ _MMIO(0xe758), 0x00778008 },
{ _MMIO(0xe45c), 0x00088078 },
{ _MMIO(0xe55c), 0x00808708 },
{ _MMIO(0xe65c), 0x00a08908 },
};
static const struct i915_oa_reg mux_config_compute_extended[] = {
{ _MMIO(0x9888), 0x104f00e0 },
{ _MMIO(0x9888), 0x141c0160 },
{ _MMIO(0x9888), 0x161c0015 },
{ _MMIO(0x9888), 0x181c0120 },
{ _MMIO(0x9888), 0x002d5000 },
{ _MMIO(0x9888), 0x062d4000 },
{ _MMIO(0x9888), 0x082d5000 },
{ _MMIO(0x9888), 0x0a2d5000 },
{ _MMIO(0x9888), 0x0c2d5000 },
{ _MMIO(0x9888), 0x0e2d5000 },
{ _MMIO(0x9888), 0x022d5000 },
{ _MMIO(0x9888), 0x042d5000 },
{ _MMIO(0x9888), 0x0c2e5400 },
{ _MMIO(0x9888), 0x0e2e5515 },
{ _MMIO(0x9888), 0x102e0155 },
{ _MMIO(0x9888), 0x044cc000 },
{ _MMIO(0x9888), 0x0a4c8000 },
{ _MMIO(0x9888), 0x0c4cc000 },
{ _MMIO(0x9888), 0x0e4cc000 },
{ _MMIO(0x9888), 0x104c8000 },
{ _MMIO(0x9888), 0x124c8000 },
{ _MMIO(0x9888), 0x144c8000 },
{ _MMIO(0x9888), 0x164c2000 },
{ _MMIO(0x9888), 0x064cc000 },
{ _MMIO(0x9888), 0x084cc000 },
{ _MMIO(0x9888), 0x004ea000 },
{ _MMIO(0x9888), 0x064e8000 },
{ _MMIO(0x9888), 0x084ea000 },
{ _MMIO(0x9888), 0x0a4ea000 },
{ _MMIO(0x9888), 0x0c4ea000 },
{ _MMIO(0x9888), 0x0e4ea000 },
{ _MMIO(0x9888), 0x024ea000 },
{ _MMIO(0x9888), 0x044ea000 },
{ _MMIO(0x9888), 0x0e4f4b41 },
{ _MMIO(0x9888), 0x004f4200 },
{ _MMIO(0x9888), 0x024f404c },
{ _MMIO(0x9888), 0x1c4f0000 },
{ _MMIO(0x9888), 0x1a4f0000 },
{ _MMIO(0x9888), 0x001b4000 },
{ _MMIO(0x9888), 0x061b8000 },
{ _MMIO(0x9888), 0x081bc000 },
{ _MMIO(0x9888), 0x0a1bc000 },
{ _MMIO(0x9888), 0x0c1bc000 },
{ _MMIO(0x9888), 0x041bc000 },
{ _MMIO(0x9888), 0x001c0031 },
{ _MMIO(0x9888), 0x061c1900 },
{ _MMIO(0x9888), 0x081c1a33 },
{ _MMIO(0x9888), 0x0a1c1b35 },
{ _MMIO(0x9888), 0x0c1c3337 },
{ _MMIO(0x9888), 0x041c31c7 },
{ _MMIO(0x9888), 0x180f5000 },
{ _MMIO(0x9888), 0x1a0fa8aa },
{ _MMIO(0x9888), 0x1c0f0aaa },
{ _MMIO(0x9888), 0x182c8000 },
{ _MMIO(0x9888), 0x1c2c6aaa },
{ _MMIO(0x9888), 0x1e2c0001 },
{ _MMIO(0x9888), 0x1a2c2950 },
{ _MMIO(0x9888), 0x01938000 },
{ _MMIO(0x9888), 0x0f938000 },
{ _MMIO(0x9888), 0x1993aaaa },
{ _MMIO(0x9888), 0x03938000 },
{ _MMIO(0x9888), 0x05938000 },
{ _MMIO(0x9888), 0x07938000 },
{ _MMIO(0x9888), 0x09938000 },
{ _MMIO(0x9888), 0x0b938000 },
{ _MMIO(0x9888), 0x13904000 },
{ _MMIO(0x9888), 0x21904000 },
{ _MMIO(0x9888), 0x23904000 },
{ _MMIO(0x9888), 0x25904000 },
{ _MMIO(0x9888), 0x27904000 },
{ _MMIO(0x9888), 0x29904000 },
{ _MMIO(0x9888), 0x2b904000 },
{ _MMIO(0x9888), 0x2d904000 },
{ _MMIO(0x9888), 0x2f904000 },
{ _MMIO(0x9888), 0x31904000 },
{ _MMIO(0x9888), 0x15904000 },
{ _MMIO(0x9888), 0x17904000 },
{ _MMIO(0x9888), 0x19904000 },
{ _MMIO(0x9888), 0x1b904000 },
{ _MMIO(0x9888), 0x1d904000 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x43900420 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x47900000 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900000 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x4b900400 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4d900001 },
{ _MMIO(0x9888), 0x45900001 },
};
static int
get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_extended;
lens[n] = ARRAY_SIZE(mux_config_compute_extended);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x30800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x30800000 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2770), 0x0007fffa },
{ _MMIO(0x2774), 0x0000fefe },
{ _MMIO(0x2778), 0x0007fffa },
{ _MMIO(0x277c), 0x0000fefd },
{ _MMIO(0x2790), 0x0007fffa },
{ _MMIO(0x2794), 0x0000fbef },
{ _MMIO(0x2798), 0x0007fffa },
{ _MMIO(0x279c), 0x0000fbdf },
};
static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00000003 },
{ _MMIO(0xe658), 0x00002001 },
{ _MMIO(0xe758), 0x00101100 },
{ _MMIO(0xe45c), 0x00201200 },
{ _MMIO(0xe55c), 0x00301300 },
{ _MMIO(0xe65c), 0x00401400 },
};
static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
{ _MMIO(0x9888), 0x166c03b0 },
{ _MMIO(0x9888), 0x1593001e },
{ _MMIO(0x9888), 0x3f900c00 },
{ _MMIO(0x9888), 0x41900000 },
{ _MMIO(0x9888), 0x002d1000 },
{ _MMIO(0x9888), 0x062d4000 },
{ _MMIO(0x9888), 0x082d5000 },
{ _MMIO(0x9888), 0x0e2d5000 },
{ _MMIO(0x9888), 0x0c2e0400 },
{ _MMIO(0x9888), 0x0e2e1500 },
{ _MMIO(0x9888), 0x102e0140 },
{ _MMIO(0x9888), 0x044c4000 },
{ _MMIO(0x9888), 0x0a4c8000 },
{ _MMIO(0x9888), 0x0c4cc000 },
{ _MMIO(0x9888), 0x144c8000 },
{ _MMIO(0x9888), 0x164c2000 },
{ _MMIO(0x9888), 0x004e2000 },
{ _MMIO(0x9888), 0x064e8000 },
{ _MMIO(0x9888), 0x084ea000 },
{ _MMIO(0x9888), 0x0e4ea000 },
{ _MMIO(0x9888), 0x1a4f4001 },
{ _MMIO(0x9888), 0x1c4f5005 },
{ _MMIO(0x9888), 0x006c0051 },
{ _MMIO(0x9888), 0x066c5000 },
{ _MMIO(0x9888), 0x086c5c5d },
{ _MMIO(0x9888), 0x0e6c5e5f },
{ _MMIO(0x9888), 0x106c0000 },
{ _MMIO(0x9888), 0x146c0000 },
{ _MMIO(0x9888), 0x1a6c0000 },
{ _MMIO(0x9888), 0x1c6c0000 },
{ _MMIO(0x9888), 0x180f1000 },
{ _MMIO(0x9888), 0x1a0fa800 },
{ _MMIO(0x9888), 0x1c0f0a00 },
{ _MMIO(0x9888), 0x182c4000 },
{ _MMIO(0x9888), 0x1c2c4015 },
{ _MMIO(0x9888), 0x1e2c0001 },
{ _MMIO(0x9888), 0x03931980 },
{ _MMIO(0x9888), 0x05930032 },
{ _MMIO(0x9888), 0x11930000 },
{ _MMIO(0x9888), 0x01938000 },
{ _MMIO(0x9888), 0x0f938000 },
{ _MMIO(0x9888), 0x1993a00a },
{ _MMIO(0x9888), 0x07930000 },
{ _MMIO(0x9888), 0x09930000 },
{ _MMIO(0x9888), 0x1d900177 },
{ _MMIO(0x9888), 0x1f900178 },
{ _MMIO(0x9888), 0x35900000 },
{ _MMIO(0x9888), 0x13904000 },
{ _MMIO(0x9888), 0x21904000 },
{ _MMIO(0x9888), 0x23904000 },
{ _MMIO(0x9888), 0x25904000 },
{ _MMIO(0x9888), 0x2f904000 },
{ _MMIO(0x9888), 0x31904000 },
{ _MMIO(0x9888), 0x19904000 },
{ _MMIO(0x9888), 0x1b904000 },
{ _MMIO(0x9888), 0x53901000 },
{ _MMIO(0x9888), 0x43900000 },
{ _MMIO(0x9888), 0x55900111 },
{ _MMIO(0x9888), 0x47900001 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x4b900000 },
{ _MMIO(0x9888), 0x4d900000 },
{ _MMIO(0x9888), 0x45900400 },
};
static int
get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_l3_cache;
lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x10800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x00000002 },
{ _MMIO(0x2774), 0x0000fdff },
};
static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
{ _MMIO(0x9888), 0x104f0232 },
{ _MMIO(0x9888), 0x124f4640 },
{ _MMIO(0x9888), 0x11834400 },
{ _MMIO(0x9888), 0x022d4000 },
{ _MMIO(0x9888), 0x042d5000 },
{ _MMIO(0x9888), 0x062d1000 },
{ _MMIO(0x9888), 0x0e2e0055 },
{ _MMIO(0x9888), 0x064c8000 },
{ _MMIO(0x9888), 0x084cc000 },
{ _MMIO(0x9888), 0x0a4c4000 },
{ _MMIO(0x9888), 0x024e8000 },
{ _MMIO(0x9888), 0x044ea000 },
{ _MMIO(0x9888), 0x064e2000 },
{ _MMIO(0x9888), 0x024f6100 },
{ _MMIO(0x9888), 0x044f416b },
{ _MMIO(0x9888), 0x064f004b },
{ _MMIO(0x9888), 0x1a4f0000 },
{ _MMIO(0x9888), 0x1a0f02a8 },
{ _MMIO(0x9888), 0x1a2c5500 },
{ _MMIO(0x9888), 0x0f808000 },
{ _MMIO(0x9888), 0x25810020 },
{ _MMIO(0x9888), 0x0f8305c0 },
{ _MMIO(0x9888), 0x07938000 },
{ _MMIO(0x9888), 0x09938000 },
{ _MMIO(0x9888), 0x0b938000 },
{ _MMIO(0x9888), 0x0d938000 },
{ _MMIO(0x9888), 0x1f951000 },
{ _MMIO(0x9888), 0x13920200 },
{ _MMIO(0x9888), 0x31908000 },
{ _MMIO(0x9888), 0x19904000 },
{ _MMIO(0x9888), 0x1b904000 },
{ _MMIO(0x9888), 0x1d904000 },
{ _MMIO(0x9888), 0x1f904000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x4d900003 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900000 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x47900000 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_hdc_and_sf;
lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_l3_1[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2770), 0x00100070 },
{ _MMIO(0x2774), 0x0000fff1 },
{ _MMIO(0x2778), 0x00014002 },
{ _MMIO(0x277c), 0x0000c3ff },
{ _MMIO(0x2780), 0x00010002 },
{ _MMIO(0x2784), 0x0000c7ff },
{ _MMIO(0x2788), 0x00004002 },
{ _MMIO(0x278c), 0x0000d3ff },
{ _MMIO(0x2790), 0x00100700 },
{ _MMIO(0x2794), 0x0000ff1f },
{ _MMIO(0x2798), 0x00001402 },
{ _MMIO(0x279c), 0x0000fc3f },
{ _MMIO(0x27a0), 0x00001002 },
{ _MMIO(0x27a4), 0x0000fc7f },
{ _MMIO(0x27a8), 0x00000402 },
{ _MMIO(0x27ac), 0x0000fd3f },
};
static const struct i915_oa_reg flex_eu_config_l3_1[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_l3_1_0_sku_gte_0x03[] = {
{ _MMIO(0x9888), 0x12643400 },
{ _MMIO(0x9888), 0x12653400 },
{ _MMIO(0x9888), 0x106c6800 },
{ _MMIO(0x9888), 0x126c001e },
{ _MMIO(0x9888), 0x166c0010 },
{ _MMIO(0x9888), 0x0c2d5000 },
{ _MMIO(0x9888), 0x0e2d5000 },
{ _MMIO(0x9888), 0x002d4000 },
{ _MMIO(0x9888), 0x022d5000 },
{ _MMIO(0x9888), 0x042d5000 },
{ _MMIO(0x9888), 0x062d1000 },
{ _MMIO(0x9888), 0x102e0154 },
{ _MMIO(0x9888), 0x0c2e5000 },
{ _MMIO(0x9888), 0x0e2e0055 },
{ _MMIO(0x9888), 0x104c8000 },
{ _MMIO(0x9888), 0x124c8000 },
{ _MMIO(0x9888), 0x144c8000 },
{ _MMIO(0x9888), 0x164c2000 },
{ _MMIO(0x9888), 0x044c8000 },
{ _MMIO(0x9888), 0x064cc000 },
{ _MMIO(0x9888), 0x084cc000 },
{ _MMIO(0x9888), 0x0a4c4000 },
{ _MMIO(0x9888), 0x0c4ea000 },
{ _MMIO(0x9888), 0x0e4ea000 },
{ _MMIO(0x9888), 0x004e8000 },
{ _MMIO(0x9888), 0x024ea000 },
{ _MMIO(0x9888), 0x044ea000 },
{ _MMIO(0x9888), 0x064e2000 },
{ _MMIO(0x9888), 0x1c4f5500 },
{ _MMIO(0x9888), 0x1a4f1554 },
{ _MMIO(0x9888), 0x0a640024 },
{ _MMIO(0x9888), 0x10640000 },
{ _MMIO(0x9888), 0x04640000 },
{ _MMIO(0x9888), 0x0c650024 },
{ _MMIO(0x9888), 0x10650000 },
{ _MMIO(0x9888), 0x06650000 },
{ _MMIO(0x9888), 0x0c6c5327 },
{ _MMIO(0x9888), 0x0e6c5425 },
{ _MMIO(0x9888), 0x006c2a00 },
{ _MMIO(0x9888), 0x026c285b },
{ _MMIO(0x9888), 0x046c005c },
{ _MMIO(0x9888), 0x1c6c0000 },
{ _MMIO(0x9888), 0x1a6c0900 },
{ _MMIO(0x9888), 0x1c0f0aa0 },
{ _MMIO(0x9888), 0x180f4000 },
{ _MMIO(0x9888), 0x1a0f02aa },
{ _MMIO(0x9888), 0x1c2c5400 },
{ _MMIO(0x9888), 0x1e2c0001 },
{ _MMIO(0x9888), 0x1a2c5550 },
{ _MMIO(0x9888), 0x1993aa00 },
{ _MMIO(0x9888), 0x03938000 },
{ _MMIO(0x9888), 0x05938000 },
{ _MMIO(0x9888), 0x07938000 },
{ _MMIO(0x9888), 0x09938000 },
{ _MMIO(0x9888), 0x0b938000 },
{ _MMIO(0x9888), 0x0d938000 },
{ _MMIO(0x9888), 0x2b904000 },
{ _MMIO(0x9888), 0x2d904000 },
{ _MMIO(0x9888), 0x2f904000 },
{ _MMIO(0x9888), 0x31904000 },
{ _MMIO(0x9888), 0x15904000 },
{ _MMIO(0x9888), 0x17904000 },
{ _MMIO(0x9888), 0x19904000 },
{ _MMIO(0x9888), 0x1b904000 },
{ _MMIO(0x9888), 0x1d904000 },
{ _MMIO(0x9888), 0x1f904000 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x4b900421 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4d900001 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x43900420 },
{ _MMIO(0x9888), 0x45900021 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x47900000 },
};
static const struct i915_oa_reg mux_config_l3_1_0_sku_lt_0x03[] = {
{ _MMIO(0x9888), 0x14640340 },
{ _MMIO(0x9888), 0x14650340 },
{ _MMIO(0x9888), 0x106c6800 },
{ _MMIO(0x9888), 0x126c001e },
{ _MMIO(0x9888), 0x166c0010 },
{ _MMIO(0x9888), 0x0c2d5000 },
{ _MMIO(0x9888), 0x0e2d5000 },
{ _MMIO(0x9888), 0x002d4000 },
{ _MMIO(0x9888), 0x022d5000 },
{ _MMIO(0x9888), 0x042d5000 },
{ _MMIO(0x9888), 0x062d1000 },
{ _MMIO(0x9888), 0x102e0154 },
{ _MMIO(0x9888), 0x0c2e5000 },
{ _MMIO(0x9888), 0x0e2e0055 },
{ _MMIO(0x9888), 0x104c8000 },
{ _MMIO(0x9888), 0x124c8000 },
{ _MMIO(0x9888), 0x144c8000 },
{ _MMIO(0x9888), 0x164c2000 },
{ _MMIO(0x9888), 0x044c8000 },
{ _MMIO(0x9888), 0x064cc000 },
{ _MMIO(0x9888), 0x084cc000 },
{ _MMIO(0x9888), 0x0a4c4000 },
{ _MMIO(0x9888), 0x0c4ea000 },
{ _MMIO(0x9888), 0x0e4ea000 },
{ _MMIO(0x9888), 0x004e8000 },
{ _MMIO(0x9888), 0x024ea000 },
{ _MMIO(0x9888), 0x044ea000 },
{ _MMIO(0x9888), 0x064e2000 },
{ _MMIO(0x9888), 0x1c4f5500 },
{ _MMIO(0x9888), 0x1a4f1554 },
{ _MMIO(0x9888), 0x04642400 },
{ _MMIO(0x9888), 0x22640000 },
{ _MMIO(0x9888), 0x1a640000 },
{ _MMIO(0x9888), 0x06650024 },
{ _MMIO(0x9888), 0x22650000 },
{ _MMIO(0x9888), 0x1c650000 },
{ _MMIO(0x9888), 0x0c6c5327 },
{ _MMIO(0x9888), 0x0e6c5425 },
{ _MMIO(0x9888), 0x006c2a00 },
{ _MMIO(0x9888), 0x026c285b },
{ _MMIO(0x9888), 0x046c005c },
{ _MMIO(0x9888), 0x1c6c0000 },
{ _MMIO(0x9888), 0x1a6c0900 },
{ _MMIO(0x9888), 0x1c0f0aa0 },
{ _MMIO(0x9888), 0x180f4000 },
{ _MMIO(0x9888), 0x1a0f02aa },
{ _MMIO(0x9888), 0x1c2c5400 },
{ _MMIO(0x9888), 0x1e2c0001 },
{ _MMIO(0x9888), 0x1a2c5550 },
{ _MMIO(0x9888), 0x1993aa00 },
{ _MMIO(0x9888), 0x03938000 },
{ _MMIO(0x9888), 0x05938000 },
{ _MMIO(0x9888), 0x07938000 },
{ _MMIO(0x9888), 0x09938000 },
{ _MMIO(0x9888), 0x0b938000 },
{ _MMIO(0x9888), 0x0d938000 },
{ _MMIO(0x9888), 0x2b904000 },
{ _MMIO(0x9888), 0x2d904000 },
{ _MMIO(0x9888), 0x2f904000 },
{ _MMIO(0x9888), 0x31904000 },
{ _MMIO(0x9888), 0x15904000 },
{ _MMIO(0x9888), 0x17904000 },
{ _MMIO(0x9888), 0x19904000 },
{ _MMIO(0x9888), 0x1b904000 },
{ _MMIO(0x9888), 0x1d904000 },
{ _MMIO(0x9888), 0x1f904000 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x4b900421 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4d900001 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x43900420 },
{ _MMIO(0x9888), 0x45900021 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x47900000 },
};
static int
get_l3_1_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2);
if (dev_priv->drm.pdev->revision >= 0x03) {
regs[n] = mux_config_l3_1_0_sku_gte_0x03;
lens[n] = ARRAY_SIZE(mux_config_l3_1_0_sku_gte_0x03);
n++;
}
if (dev_priv->drm.pdev->revision < 0x03) {
regs[n] = mux_config_l3_1_0_sku_lt_0x03;
lens[n] = ARRAY_SIZE(mux_config_l3_1_0_sku_lt_0x03);
n++;
}
return n;
}
static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x30800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x00000002 },
{ _MMIO(0x2774), 0x0000efff },
{ _MMIO(0x2778), 0x00006000 },
{ _MMIO(0x277c), 0x0000f3ff },
};
static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
{ _MMIO(0x9888), 0x102d7800 },
{ _MMIO(0x9888), 0x122d79e0 },
{ _MMIO(0x9888), 0x0c2f0004 },
{ _MMIO(0x9888), 0x100e3800 },
{ _MMIO(0x9888), 0x180f0005 },
{ _MMIO(0x9888), 0x002d0940 },
{ _MMIO(0x9888), 0x022d802f },
{ _MMIO(0x9888), 0x042d4013 },
{ _MMIO(0x9888), 0x062d1000 },
{ _MMIO(0x9888), 0x0e2e0050 },
{ _MMIO(0x9888), 0x022f0010 },
{ _MMIO(0x9888), 0x002f0000 },
{ _MMIO(0x9888), 0x084c8000 },
{ _MMIO(0x9888), 0x0a4c4000 },
{ _MMIO(0x9888), 0x044e8000 },
{ _MMIO(0x9888), 0x064e2000 },
{ _MMIO(0x9888), 0x040e0480 },
{ _MMIO(0x9888), 0x000e0000 },
{ _MMIO(0x9888), 0x060f0027 },
{ _MMIO(0x9888), 0x100f0000 },
{ _MMIO(0x9888), 0x1a0f0040 },
{ _MMIO(0x9888), 0x03938000 },
{ _MMIO(0x9888), 0x05938000 },
{ _MMIO(0x9888), 0x07938000 },
{ _MMIO(0x9888), 0x09938000 },
{ _MMIO(0x9888), 0x0b938000 },
{ _MMIO(0x9888), 0x0d938000 },
{ _MMIO(0x9888), 0x15904000 },
{ _MMIO(0x9888), 0x17904000 },
{ _MMIO(0x9888), 0x19904000 },
{ _MMIO(0x9888), 0x1b904000 },
{ _MMIO(0x9888), 0x1d904000 },
{ _MMIO(0x9888), 0x1f904000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x439014a0 },
{ _MMIO(0x9888), 0x459000a4 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x47900001 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_rasterizer_and_pixel_backend;
lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_sampler[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x70800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x0000c000 },
{ _MMIO(0x2774), 0x0000e7ff },
{ _MMIO(0x2778), 0x00003000 },
{ _MMIO(0x277c), 0x0000f9ff },
{ _MMIO(0x2780), 0x00000c00 },
{ _MMIO(0x2784), 0x0000fe7f },
};
static const struct i915_oa_reg flex_eu_config_sampler[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_sampler[] = {
{ _MMIO(0x9888), 0x121300a0 },
{ _MMIO(0x9888), 0x141600ab },
{ _MMIO(0x9888), 0x123300a0 },
{ _MMIO(0x9888), 0x143600ab },
{ _MMIO(0x9888), 0x125300a0 },
{ _MMIO(0x9888), 0x145600ab },
{ _MMIO(0x9888), 0x0c2d4000 },
{ _MMIO(0x9888), 0x0e2d5000 },
{ _MMIO(0x9888), 0x002d4000 },
{ _MMIO(0x9888), 0x022d5000 },
{ _MMIO(0x9888), 0x042d5000 },
{ _MMIO(0x9888), 0x062d1000 },
{ _MMIO(0x9888), 0x102e01a0 },
{ _MMIO(0x9888), 0x0c2e5000 },
{ _MMIO(0x9888), 0x0e2e0065 },
{ _MMIO(0x9888), 0x164c2000 },
{ _MMIO(0x9888), 0x044c8000 },
{ _MMIO(0x9888), 0x064cc000 },
{ _MMIO(0x9888), 0x084c4000 },
{ _MMIO(0x9888), 0x0a4c4000 },
{ _MMIO(0x9888), 0x0e4e8000 },
{ _MMIO(0x9888), 0x004e8000 },
{ _MMIO(0x9888), 0x024ea000 },
{ _MMIO(0x9888), 0x044e2000 },
{ _MMIO(0x9888), 0x064e2000 },
{ _MMIO(0x9888), 0x1c0f0800 },
{ _MMIO(0x9888), 0x180f4000 },
{ _MMIO(0x9888), 0x1a0f023f },
{ _MMIO(0x9888), 0x1e2c0003 },
{ _MMIO(0x9888), 0x1a2cc030 },
{ _MMIO(0x9888), 0x04132180 },
{ _MMIO(0x9888), 0x02130000 },
{ _MMIO(0x9888), 0x0c148000 },
{ _MMIO(0x9888), 0x0e142000 },
{ _MMIO(0x9888), 0x04148000 },
{ _MMIO(0x9888), 0x1e150140 },
{ _MMIO(0x9888), 0x1c150040 },
{ _MMIO(0x9888), 0x0c163000 },
{ _MMIO(0x9888), 0x0e160068 },
{ _MMIO(0x9888), 0x10160000 },
{ _MMIO(0x9888), 0x18160000 },
{ _MMIO(0x9888), 0x0a164000 },
{ _MMIO(0x9888), 0x04330043 },
{ _MMIO(0x9888), 0x02330000 },
{ _MMIO(0x9888), 0x0234a000 },
{ _MMIO(0x9888), 0x04342000 },
{ _MMIO(0x9888), 0x1c350015 },
{ _MMIO(0x9888), 0x02363460 },
{ _MMIO(0x9888), 0x10360000 },
{ _MMIO(0x9888), 0x04360000 },
{ _MMIO(0x9888), 0x06360000 },
{ _MMIO(0x9888), 0x08364000 },
{ _MMIO(0x9888), 0x06530043 },
{ _MMIO(0x9888), 0x02530000 },
{ _MMIO(0x9888), 0x0e548000 },
{ _MMIO(0x9888), 0x00548000 },
{ _MMIO(0x9888), 0x06542000 },
{ _MMIO(0x9888), 0x1e550400 },
{ _MMIO(0x9888), 0x1a552000 },
{ _MMIO(0x9888), 0x1c550100 },
{ _MMIO(0x9888), 0x0e563000 },
{ _MMIO(0x9888), 0x00563400 },
{ _MMIO(0x9888), 0x10560000 },
{ _MMIO(0x9888), 0x18560000 },
{ _MMIO(0x9888), 0x02560000 },
{ _MMIO(0x9888), 0x0c564000 },
{ _MMIO(0x9888), 0x1993a800 },
{ _MMIO(0x9888), 0x03938000 },
{ _MMIO(0x9888), 0x05938000 },
{ _MMIO(0x9888), 0x07938000 },
{ _MMIO(0x9888), 0x09938000 },
{ _MMIO(0x9888), 0x0b938000 },
{ _MMIO(0x9888), 0x0d938000 },
{ _MMIO(0x9888), 0x2d904000 },
{ _MMIO(0x9888), 0x2f904000 },
{ _MMIO(0x9888), 0x31904000 },
{ _MMIO(0x9888), 0x15904000 },
{ _MMIO(0x9888), 0x17904000 },
{ _MMIO(0x9888), 0x19904000 },
{ _MMIO(0x9888), 0x1b904000 },
{ _MMIO(0x9888), 0x1d904000 },
{ _MMIO(0x9888), 0x1f904000 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x4b9014a0 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4d900001 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x43900820 },
{ _MMIO(0x9888), 0x45901022 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x47900000 },
};
static int
get_sampler_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_sampler;
lens[n] = ARRAY_SIZE(mux_config_sampler);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_tdl_1[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x30800000 },
{ _MMIO(0x2770), 0x00000002 },
{ _MMIO(0x2774), 0x00007fff },
{ _MMIO(0x2778), 0x00000000 },
{ _MMIO(0x277c), 0x00009fff },
{ _MMIO(0x2780), 0x00000002 },
{ _MMIO(0x2784), 0x0000efff },
{ _MMIO(0x2788), 0x00000000 },
{ _MMIO(0x278c), 0x0000f3ff },
{ _MMIO(0x2790), 0x00000002 },
{ _MMIO(0x2794), 0x0000fdff },
{ _MMIO(0x2798), 0x00000000 },
{ _MMIO(0x279c), 0x0000fe7f },
};
static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_tdl_1[] = {
{ _MMIO(0x9888), 0x141a0000 },
{ _MMIO(0x9888), 0x143a0000 },
{ _MMIO(0x9888), 0x145a0000 },
{ _MMIO(0x9888), 0x0c2d4000 },
{ _MMIO(0x9888), 0x0e2d5000 },
{ _MMIO(0x9888), 0x002d4000 },
{ _MMIO(0x9888), 0x022d5000 },
{ _MMIO(0x9888), 0x042d5000 },
{ _MMIO(0x9888), 0x062d1000 },
{ _MMIO(0x9888), 0x102e0150 },
{ _MMIO(0x9888), 0x0c2e5000 },
{ _MMIO(0x9888), 0x0e2e006a },
{ _MMIO(0x9888), 0x124c8000 },
{ _MMIO(0x9888), 0x144c8000 },
{ _MMIO(0x9888), 0x164c2000 },
{ _MMIO(0x9888), 0x044c8000 },
{ _MMIO(0x9888), 0x064c4000 },
{ _MMIO(0x9888), 0x0a4c4000 },
{ _MMIO(0x9888), 0x0c4e8000 },
{ _MMIO(0x9888), 0x0e4ea000 },
{ _MMIO(0x9888), 0x004e8000 },
{ _MMIO(0x9888), 0x024e2000 },
{ _MMIO(0x9888), 0x064e2000 },
{ _MMIO(0x9888), 0x1c0f0bc0 },
{ _MMIO(0x9888), 0x180f4000 },
{ _MMIO(0x9888), 0x1a0f0302 },
{ _MMIO(0x9888), 0x1e2c0003 },
{ _MMIO(0x9888), 0x1a2c00f0 },
{ _MMIO(0x9888), 0x021a3080 },
{ _MMIO(0x9888), 0x041a31e5 },
{ _MMIO(0x9888), 0x02148000 },
{ _MMIO(0x9888), 0x0414a000 },
{ _MMIO(0x9888), 0x1c150054 },
{ _MMIO(0x9888), 0x06168000 },
{ _MMIO(0x9888), 0x08168000 },
{ _MMIO(0x9888), 0x0a168000 },
{ _MMIO(0x9888), 0x0c3a3280 },
{ _MMIO(0x9888), 0x0e3a0063 },
{ _MMIO(0x9888), 0x063a0061 },
{ _MMIO(0x9888), 0x023a0000 },
{ _MMIO(0x9888), 0x0c348000 },
{ _MMIO(0x9888), 0x0e342000 },
{ _MMIO(0x9888), 0x06342000 },
{ _MMIO(0x9888), 0x1e350140 },
{ _MMIO(0x9888), 0x1c350100 },
{ _MMIO(0x9888), 0x18360028 },
{ _MMIO(0x9888), 0x0c368000 },
{ _MMIO(0x9888), 0x0e5a3080 },
{ _MMIO(0x9888), 0x005a3280 },
{ _MMIO(0x9888), 0x025a0063 },
{ _MMIO(0x9888), 0x0e548000 },
{ _MMIO(0x9888), 0x00548000 },
{ _MMIO(0x9888), 0x02542000 },
{ _MMIO(0x9888), 0x1e550400 },
{ _MMIO(0x9888), 0x1a552000 },
{ _MMIO(0x9888), 0x1c550001 },
{ _MMIO(0x9888), 0x18560080 },
{ _MMIO(0x9888), 0x02568000 },
{ _MMIO(0x9888), 0x04568000 },
{ _MMIO(0x9888), 0x1993a800 },
{ _MMIO(0x9888), 0x03938000 },
{ _MMIO(0x9888), 0x05938000 },
{ _MMIO(0x9888), 0x07938000 },
{ _MMIO(0x9888), 0x09938000 },
{ _MMIO(0x9888), 0x0b938000 },
{ _MMIO(0x9888), 0x0d938000 },
{ _MMIO(0x9888), 0x2d904000 },
{ _MMIO(0x9888), 0x2f904000 },
{ _MMIO(0x9888), 0x31904000 },
{ _MMIO(0x9888), 0x15904000 },
{ _MMIO(0x9888), 0x17904000 },
{ _MMIO(0x9888), 0x19904000 },
{ _MMIO(0x9888), 0x1b904000 },
{ _MMIO(0x9888), 0x1d904000 },
{ _MMIO(0x9888), 0x1f904000 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x4b900420 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4d900000 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x43900000 },
{ _MMIO(0x9888), 0x45901084 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x47900001 },
};
static int
get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_tdl_1;
lens[n] = ARRAY_SIZE(mux_config_tdl_1);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_tdl_2[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x00800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
};
static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_tdl_2[] = {
{ _MMIO(0x9888), 0x141a026b },
{ _MMIO(0x9888), 0x143a0173 },
{ _MMIO(0x9888), 0x145a026b },
{ _MMIO(0x9888), 0x002d4000 },
{ _MMIO(0x9888), 0x022d5000 },
{ _MMIO(0x9888), 0x042d5000 },
{ _MMIO(0x9888), 0x062d1000 },
{ _MMIO(0x9888), 0x0c2e5000 },
{ _MMIO(0x9888), 0x0e2e0069 },
{ _MMIO(0x9888), 0x044c8000 },
{ _MMIO(0x9888), 0x064cc000 },
{ _MMIO(0x9888), 0x0a4c4000 },
{ _MMIO(0x9888), 0x004e8000 },
{ _MMIO(0x9888), 0x024ea000 },
{ _MMIO(0x9888), 0x064e2000 },
{ _MMIO(0x9888), 0x180f6000 },
{ _MMIO(0x9888), 0x1a0f030a },
{ _MMIO(0x9888), 0x1a2c03c0 },
{ _MMIO(0x9888), 0x041a37e7 },
{ _MMIO(0x9888), 0x021a0000 },
{ _MMIO(0x9888), 0x0414a000 },
{ _MMIO(0x9888), 0x1c150050 },
{ _MMIO(0x9888), 0x08168000 },
{ _MMIO(0x9888), 0x0a168000 },
{ _MMIO(0x9888), 0x003a3380 },
{ _MMIO(0x9888), 0x063a006f },
{ _MMIO(0x9888), 0x023a0000 },
{ _MMIO(0x9888), 0x00348000 },
{ _MMIO(0x9888), 0x06342000 },
{ _MMIO(0x9888), 0x1a352000 },
{ _MMIO(0x9888), 0x1c350100 },
{ _MMIO(0x9888), 0x02368000 },
{ _MMIO(0x9888), 0x0c368000 },
{ _MMIO(0x9888), 0x025a37e7 },
{ _MMIO(0x9888), 0x0254a000 },
{ _MMIO(0x9888), 0x1c550005 },
{ _MMIO(0x9888), 0x04568000 },
{ _MMIO(0x9888), 0x06568000 },
{ _MMIO(0x9888), 0x03938000 },
{ _MMIO(0x9888), 0x05938000 },
{ _MMIO(0x9888), 0x07938000 },
{ _MMIO(0x9888), 0x09938000 },
{ _MMIO(0x9888), 0x0b938000 },
{ _MMIO(0x9888), 0x0d938000 },
{ _MMIO(0x9888), 0x15904000 },
{ _MMIO(0x9888), 0x17904000 },
{ _MMIO(0x9888), 0x19904000 },
{ _MMIO(0x9888), 0x1b904000 },
{ _MMIO(0x9888), 0x1d904000 },
{ _MMIO(0x9888), 0x1f904000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x43900020 },
{ _MMIO(0x9888), 0x45901080 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x47900001 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_tdl_2;
lens[n] = ARRAY_SIZE(mux_config_tdl_2);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_compute_extra[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x00800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
};
static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
{ _MMIO(0xe458), 0x00001000 },
{ _MMIO(0xe558), 0x00003002 },
{ _MMIO(0xe658), 0x00005004 },
{ _MMIO(0xe758), 0x00011010 },
{ _MMIO(0xe45c), 0x00050012 },
{ _MMIO(0xe55c), 0x00052051 },
{ _MMIO(0xe65c), 0x00000008 },
};
static const struct i915_oa_reg mux_config_compute_extra[] = {
{ _MMIO(0x9888), 0x141a001f },
{ _MMIO(0x9888), 0x143a001f },
{ _MMIO(0x9888), 0x145a001f },
{ _MMIO(0x9888), 0x042d5000 },
{ _MMIO(0x9888), 0x062d1000 },
{ _MMIO(0x9888), 0x0e2e0094 },
{ _MMIO(0x9888), 0x084cc000 },
{ _MMIO(0x9888), 0x044ea000 },
{ _MMIO(0x9888), 0x1a0f00e0 },
{ _MMIO(0x9888), 0x1a2c0c00 },
{ _MMIO(0x9888), 0x061a0063 },
{ _MMIO(0x9888), 0x021a0000 },
{ _MMIO(0x9888), 0x06142000 },
{ _MMIO(0x9888), 0x1c150100 },
{ _MMIO(0x9888), 0x0c168000 },
{ _MMIO(0x9888), 0x043a3180 },
{ _MMIO(0x9888), 0x023a0000 },
{ _MMIO(0x9888), 0x04348000 },
{ _MMIO(0x9888), 0x1c350040 },
{ _MMIO(0x9888), 0x0a368000 },
{ _MMIO(0x9888), 0x045a0063 },
{ _MMIO(0x9888), 0x025a0000 },
{ _MMIO(0x9888), 0x04542000 },
{ _MMIO(0x9888), 0x1c550010 },
{ _MMIO(0x9888), 0x08568000 },
{ _MMIO(0x9888), 0x09938000 },
{ _MMIO(0x9888), 0x0b938000 },
{ _MMIO(0x9888), 0x0d938000 },
{ _MMIO(0x9888), 0x1b904000 },
{ _MMIO(0x9888), 0x1d904000 },
{ _MMIO(0x9888), 0x1f904000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x45900400 },
{ _MMIO(0x9888), 0x47900004 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_extra;
lens[n] = ARRAY_SIZE(mux_config_compute_extra);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_test_oa[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2770), 0x00000004 },
{ _MMIO(0x2774), 0x00000000 },
{ _MMIO(0x2778), 0x00000003 },
{ _MMIO(0x277c), 0x00000000 },
{ _MMIO(0x2780), 0x00000007 },
{ _MMIO(0x2784), 0x00000000 },
{ _MMIO(0x2788), 0x00100002 },
{ _MMIO(0x278c), 0x0000fff7 },
{ _MMIO(0x2790), 0x00100002 },
{ _MMIO(0x2794), 0x0000ffcf },
{ _MMIO(0x2798), 0x00100082 },
{ _MMIO(0x279c), 0x0000ffef },
{ _MMIO(0x27a0), 0x001000c2 },
{ _MMIO(0x27a4), 0x0000ffe7 },
{ _MMIO(0x27a8), 0x00100001 },
{ _MMIO(0x27ac), 0x0000ffe7 },
};
static const struct i915_oa_reg flex_eu_config_test_oa[] = {
};
static const struct i915_oa_reg mux_config_test_oa[] = {
{ _MMIO(0x9888), 0x19800000 },
{ _MMIO(0x9888), 0x07800063 },
{ _MMIO(0x9888), 0x11800000 },
{ _MMIO(0x9888), 0x23810008 },
{ _MMIO(0x9888), 0x1d950400 },
{ _MMIO(0x9888), 0x0f922000 },
{ _MMIO(0x9888), 0x1f908000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x47900000 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_test_oa_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_test_oa;
lens[n] = ARRAY_SIZE(mux_config_test_oa);
n++;
return n;
}
int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv) int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv)
{ {
dev_priv->perf.oa.n_mux_configs = 0; dev_priv->perf.oa.n_mux_configs = 0;
...@@ -164,14 +1794,352 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv) ...@@ -164,14 +1794,352 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.flex_regs = NULL; dev_priv->perf.oa.flex_regs = NULL;
dev_priv->perf.oa.flex_regs_len = 0; dev_priv->perf.oa.flex_regs_len = 0;
switch (dev_priv->perf.oa.metrics_set) { switch (dev_priv->perf.oa.metrics_set) {
case METRIC_SET_ID_RENDER_BASIC: case METRIC_SET_ID_RENDER_BASIC:
dev_priv->perf.oa.n_mux_configs =
get_render_basic_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_render_basic;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_render_basic);
dev_priv->perf.oa.flex_regs =
flex_eu_config_render_basic;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_render_basic);
return 0;
case METRIC_SET_ID_COMPUTE_BASIC:
dev_priv->perf.oa.n_mux_configs =
get_compute_basic_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_compute_basic;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_basic);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_basic;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_basic);
return 0;
case METRIC_SET_ID_RENDER_PIPE_PROFILE:
dev_priv->perf.oa.n_mux_configs =
get_render_pipe_profile_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_render_pipe_profile;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_render_pipe_profile);
dev_priv->perf.oa.flex_regs =
flex_eu_config_render_pipe_profile;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_render_pipe_profile);
return 0;
case METRIC_SET_ID_MEMORY_READS:
dev_priv->perf.oa.n_mux_configs =
get_memory_reads_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_memory_reads;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_memory_reads);
dev_priv->perf.oa.flex_regs =
flex_eu_config_memory_reads;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_memory_reads);
return 0;
case METRIC_SET_ID_MEMORY_WRITES:
dev_priv->perf.oa.n_mux_configs =
get_memory_writes_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_memory_writes;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_memory_writes);
dev_priv->perf.oa.flex_regs =
flex_eu_config_memory_writes;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_memory_writes);
return 0;
case METRIC_SET_ID_COMPUTE_EXTENDED:
dev_priv->perf.oa.n_mux_configs =
get_compute_extended_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_compute_extended;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_extended);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_extended;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_extended);
return 0;
case METRIC_SET_ID_COMPUTE_L3_CACHE:
dev_priv->perf.oa.n_mux_configs =
get_compute_l3_cache_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_compute_l3_cache;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_l3_cache);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_l3_cache;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_l3_cache);
return 0;
case METRIC_SET_ID_HDC_AND_SF:
dev_priv->perf.oa.n_mux_configs =
get_hdc_and_sf_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_hdc_and_sf;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_hdc_and_sf);
dev_priv->perf.oa.flex_regs =
flex_eu_config_hdc_and_sf;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_hdc_and_sf);
return 0;
case METRIC_SET_ID_L3_1:
dev_priv->perf.oa.n_mux_configs =
get_l3_1_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_l3_1;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_l3_1);
dev_priv->perf.oa.flex_regs =
flex_eu_config_l3_1;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_l3_1);
return 0;
case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
dev_priv->perf.oa.n_mux_configs =
get_rasterizer_and_pixel_backend_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_rasterizer_and_pixel_backend;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
dev_priv->perf.oa.flex_regs =
flex_eu_config_rasterizer_and_pixel_backend;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
return 0;
case METRIC_SET_ID_SAMPLER:
dev_priv->perf.oa.n_mux_configs =
get_sampler_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_sampler;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_sampler);
dev_priv->perf.oa.flex_regs =
flex_eu_config_sampler;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_sampler);
return 0;
case METRIC_SET_ID_TDL_1:
dev_priv->perf.oa.n_mux_configs =
get_tdl_1_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_tdl_1;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_tdl_1);
dev_priv->perf.oa.flex_regs =
flex_eu_config_tdl_1;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_tdl_1);
return 0;
case METRIC_SET_ID_TDL_2:
dev_priv->perf.oa.n_mux_configs =
get_tdl_2_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_tdl_2;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_tdl_2);
dev_priv->perf.oa.flex_regs =
flex_eu_config_tdl_2;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_tdl_2);
return 0;
case METRIC_SET_ID_COMPUTE_EXTRA:
dev_priv->perf.oa.n_mux_configs = dev_priv->perf.oa.n_mux_configs =
get_render_basic_mux_config(dev_priv, get_compute_extra_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs, dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens); dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) { if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n");
/* EINVAL because *_register_sysfs already checked this /* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and * and so it wouldn't have been advertised to userspace and
...@@ -181,14 +2149,40 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv) ...@@ -181,14 +2149,40 @@ int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv)
} }
dev_priv->perf.oa.b_counter_regs = dev_priv->perf.oa.b_counter_regs =
b_counter_config_render_basic; b_counter_config_compute_extra;
dev_priv->perf.oa.b_counter_regs_len = dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_render_basic); ARRAY_SIZE(b_counter_config_compute_extra);
dev_priv->perf.oa.flex_regs = dev_priv->perf.oa.flex_regs =
flex_eu_config_render_basic; flex_eu_config_compute_extra;
dev_priv->perf.oa.flex_regs_len = dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_render_basic); ARRAY_SIZE(flex_eu_config_compute_extra);
return 0;
case METRIC_SET_ID_TEST_OA:
dev_priv->perf.oa.n_mux_configs =
get_test_oa_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_test_oa;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_test_oa);
dev_priv->perf.oa.flex_regs =
flex_eu_config_test_oa;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_test_oa);
return 0; return 0;
default: default:
...@@ -218,6 +2212,314 @@ static struct attribute_group group_render_basic = { ...@@ -218,6 +2212,314 @@ static struct attribute_group group_render_basic = {
.attrs = attrs_render_basic, .attrs = attrs_render_basic,
}; };
static ssize_t
show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
}
static struct device_attribute dev_attr_compute_basic_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_basic_id,
.store = NULL,
};
static struct attribute *attrs_compute_basic[] = {
&dev_attr_compute_basic_id.attr,
NULL,
};
static struct attribute_group group_compute_basic = {
.name = "012d72cf-82a9-4d25-8ddf-74076fd30797",
.attrs = attrs_compute_basic,
};
static ssize_t
show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
}
static struct device_attribute dev_attr_render_pipe_profile_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_render_pipe_profile_id,
.store = NULL,
};
static struct attribute *attrs_render_pipe_profile[] = {
&dev_attr_render_pipe_profile_id.attr,
NULL,
};
static struct attribute_group group_render_pipe_profile = {
.name = "ce416533-e49e-4211-80af-ec513590a914",
.attrs = attrs_render_pipe_profile,
};
static ssize_t
show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
}
static struct device_attribute dev_attr_memory_reads_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_memory_reads_id,
.store = NULL,
};
static struct attribute *attrs_memory_reads[] = {
&dev_attr_memory_reads_id.attr,
NULL,
};
static struct attribute_group group_memory_reads = {
.name = "398e2452-18d7-42d0-b241-e4d0a9148ada",
.attrs = attrs_memory_reads,
};
static ssize_t
show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
}
static struct device_attribute dev_attr_memory_writes_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_memory_writes_id,
.store = NULL,
};
static struct attribute *attrs_memory_writes[] = {
&dev_attr_memory_writes_id.attr,
NULL,
};
static struct attribute_group group_memory_writes = {
.name = "d324a0d6-7269-4847-a5c2-6f71ddc7fed5",
.attrs = attrs_memory_writes,
};
static ssize_t
show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
}
static struct device_attribute dev_attr_compute_extended_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_extended_id,
.store = NULL,
};
static struct attribute *attrs_compute_extended[] = {
&dev_attr_compute_extended_id.attr,
NULL,
};
static struct attribute_group group_compute_extended = {
.name = "caf3596a-7bb1-4dec-b3b3-2a080d283b49",
.attrs = attrs_compute_extended,
};
static ssize_t
show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
}
static struct device_attribute dev_attr_compute_l3_cache_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_l3_cache_id,
.store = NULL,
};
static struct attribute *attrs_compute_l3_cache[] = {
&dev_attr_compute_l3_cache_id.attr,
NULL,
};
static struct attribute_group group_compute_l3_cache = {
.name = "49b956e2-d5b9-47e0-9d8a-cee5e8cec527",
.attrs = attrs_compute_l3_cache,
};
static ssize_t
show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
}
static struct device_attribute dev_attr_hdc_and_sf_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_hdc_and_sf_id,
.store = NULL,
};
static struct attribute *attrs_hdc_and_sf[] = {
&dev_attr_hdc_and_sf_id.attr,
NULL,
};
static struct attribute_group group_hdc_and_sf = {
.name = "f64ef50a-bdba-4b35-8f09-203c13d8ee5a",
.attrs = attrs_hdc_and_sf,
};
static ssize_t
show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
}
static struct device_attribute dev_attr_l3_1_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_l3_1_id,
.store = NULL,
};
static struct attribute *attrs_l3_1[] = {
&dev_attr_l3_1_id.attr,
NULL,
};
static struct attribute_group group_l3_1 = {
.name = "00ad5a41-7eab-4f7a-9103-49d411c67219",
.attrs = attrs_l3_1,
};
static ssize_t
show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
}
static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_rasterizer_and_pixel_backend_id,
.store = NULL,
};
static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
&dev_attr_rasterizer_and_pixel_backend_id.attr,
NULL,
};
static struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "46dc44ca-491c-4cc1-a951-e7b3e62bf02b",
.attrs = attrs_rasterizer_and_pixel_backend,
};
static ssize_t
show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
}
static struct device_attribute dev_attr_sampler_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_sampler_id,
.store = NULL,
};
static struct attribute *attrs_sampler[] = {
&dev_attr_sampler_id.attr,
NULL,
};
static struct attribute_group group_sampler = {
.name = "8364e2a8-af63-40af-b0d5-42969a255654",
.attrs = attrs_sampler,
};
static ssize_t
show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
}
static struct device_attribute dev_attr_tdl_1_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_tdl_1_id,
.store = NULL,
};
static struct attribute *attrs_tdl_1[] = {
&dev_attr_tdl_1_id.attr,
NULL,
};
static struct attribute_group group_tdl_1 = {
.name = "175c8092-cb25-4d1e-8dc7-b4fdd39e2d92",
.attrs = attrs_tdl_1,
};
static ssize_t
show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
}
static struct device_attribute dev_attr_tdl_2_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_tdl_2_id,
.store = NULL,
};
static struct attribute *attrs_tdl_2[] = {
&dev_attr_tdl_2_id.attr,
NULL,
};
static struct attribute_group group_tdl_2 = {
.name = "d260f03f-b34d-4b49-a44e-436819117332",
.attrs = attrs_tdl_2,
};
static ssize_t
show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
}
static struct device_attribute dev_attr_compute_extra_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_extra_id,
.store = NULL,
};
static struct attribute *attrs_compute_extra[] = {
&dev_attr_compute_extra_id.attr,
NULL,
};
static struct attribute_group group_compute_extra = {
.name = "fa6ecf21-2cb8-4d0b-9308-6e4a7b4ca87a",
.attrs = attrs_compute_extra,
};
static ssize_t
show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
}
static struct device_attribute dev_attr_test_oa_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_test_oa_id,
.store = NULL,
};
static struct attribute *attrs_test_oa[] = {
&dev_attr_test_oa_id.attr,
NULL,
};
static struct attribute_group group_test_oa = {
.name = "5ee72f5c-092f-421e-8b70-225f7c3e9612",
.attrs = attrs_test_oa,
};
int int
i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv) i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv)
{ {
...@@ -230,9 +2532,121 @@ i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv) ...@@ -230,9 +2532,121 @@ i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv)
if (ret) if (ret)
goto error_render_basic; goto error_render_basic;
} }
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
if (ret)
goto error_compute_basic;
}
if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
if (ret)
goto error_render_pipe_profile;
}
if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
if (ret)
goto error_memory_reads;
}
if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
if (ret)
goto error_memory_writes;
}
if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
if (ret)
goto error_compute_extended;
}
if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
if (ret)
goto error_compute_l3_cache;
}
if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
if (ret)
goto error_hdc_and_sf;
}
if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
if (ret)
goto error_l3_1;
}
if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
if (ret)
goto error_rasterizer_and_pixel_backend;
}
if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
if (ret)
goto error_sampler;
}
if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
if (ret)
goto error_tdl_1;
}
if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
if (ret)
goto error_tdl_2;
}
if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
if (ret)
goto error_compute_extra;
}
if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
if (ret)
goto error_test_oa;
}
return 0; return 0;
error_test_oa:
if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
error_compute_extra:
if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
error_tdl_2:
if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
error_tdl_1:
if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
error_sampler:
if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
error_rasterizer_and_pixel_backend:
if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
error_l3_1:
if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
error_hdc_and_sf:
if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
error_compute_l3_cache:
if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
error_compute_extended:
if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
error_memory_writes:
if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
error_memory_reads:
if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
error_render_pipe_profile:
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
error_compute_basic:
if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
error_render_basic: error_render_basic:
return ret; return ret;
} }
...@@ -245,4 +2659,32 @@ i915_perf_unregister_sysfs_bxt(struct drm_i915_private *dev_priv) ...@@ -245,4 +2659,32 @@ i915_perf_unregister_sysfs_bxt(struct drm_i915_private *dev_priv)
if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
} }
drivers/gpu/drm/i915/i915_oa_chv.c
View file @ fc599211
...@@ -33,9 +33,22 @@ ...@@ -33,9 +33,22 @@
enum metric_set_id { enum metric_set_id {
METRIC_SET_ID_RENDER_BASIC = 1, METRIC_SET_ID_RENDER_BASIC = 1,
METRIC_SET_ID_COMPUTE_BASIC,
METRIC_SET_ID_RENDER_PIPE_PROFILE,
METRIC_SET_ID_HDC_AND_SF,
METRIC_SET_ID_L3_1,
METRIC_SET_ID_L3_2,
METRIC_SET_ID_L3_3,
METRIC_SET_ID_L3_4,
METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
METRIC_SET_ID_SAMPLER_1,
METRIC_SET_ID_SAMPLER_2,
METRIC_SET_ID_TDL_1,
METRIC_SET_ID_TDL_2,
METRIC_SET_ID_TEST_OA,
}; };
int i915_oa_n_builtin_metric_sets_chv = 1; int i915_oa_n_builtin_metric_sets_chv = 14;
static const struct i915_oa_reg b_counter_config_render_basic[] = { static const struct i915_oa_reg b_counter_config_render_basic[] = {
{ _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2740), 0x00000000 },
...@@ -146,6 +159,1874 @@ get_render_basic_mux_config(struct drm_i915_private *dev_priv, ...@@ -146,6 +159,1874 @@ get_render_basic_mux_config(struct drm_i915_private *dev_priv,
return n; return n;
} }
static const struct i915_oa_reg b_counter_config_compute_basic[] = {
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x00800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
};
static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00000003 },
{ _MMIO(0xe658), 0x00002001 },
{ _MMIO(0xe758), 0x00778008 },
{ _MMIO(0xe45c), 0x00088078 },
{ _MMIO(0xe55c), 0x00808708 },
{ _MMIO(0xe65c), 0x00a08908 },
};
static const struct i915_oa_reg mux_config_compute_basic[] = {
{ _MMIO(0x9888), 0x59800000 },
{ _MMIO(0x9888), 0x59800001 },
{ _MMIO(0x9888), 0x2e5800e0 },
{ _MMIO(0x9888), 0x2e3800e0 },
{ _MMIO(0x9888), 0x3580024f },
{ _MMIO(0x9888), 0x3d800140 },
{ _MMIO(0x9888), 0x08580042 },
{ _MMIO(0x9888), 0x0c580040 },
{ _MMIO(0x9888), 0x1058004c },
{ _MMIO(0x9888), 0x1458004b },
{ _MMIO(0x9888), 0x04580000 },
{ _MMIO(0x9888), 0x00580000 },
{ _MMIO(0x9888), 0x00195555 },
{ _MMIO(0x9888), 0x06380042 },
{ _MMIO(0x9888), 0x0a380040 },
{ _MMIO(0x9888), 0x0e38004c },
{ _MMIO(0x9888), 0x1238004b },
{ _MMIO(0x9888), 0x04380000 },
{ _MMIO(0x9888), 0x00384444 },
{ _MMIO(0x9888), 0x003a5555 },
{ _MMIO(0x9888), 0x018bffff },
{ _MMIO(0x9888), 0x01845555 },
{ _MMIO(0x9888), 0x17800074 },
{ _MMIO(0x9888), 0x1980007d },
{ _MMIO(0x9888), 0x1b80007c },
{ _MMIO(0x9888), 0x1d8000b6 },
{ _MMIO(0x9888), 0x1f8000b7 },
{ _MMIO(0x9888), 0x05800000 },
{ _MMIO(0x9888), 0x03800000 },
{ _MMIO(0x9888), 0x418000aa },
{ _MMIO(0x9888), 0x438000aa },
{ _MMIO(0x9888), 0x45800000 },
{ _MMIO(0x9888), 0x47800000 },
{ _MMIO(0x9888), 0x4980012a },
{ _MMIO(0x9888), 0x4b80012a },
{ _MMIO(0x9888), 0x4d80012a },
{ _MMIO(0x9888), 0x4f80012a },
{ _MMIO(0x9888), 0x518001ce },
{ _MMIO(0x9888), 0x538001ce },
{ _MMIO(0x9888), 0x5580000e },
{ _MMIO(0x9888), 0x59800000 },
};
static int
get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_basic;
lens[n] = ARRAY_SIZE(mux_config_compute_basic);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2770), 0x0007ffea },
{ _MMIO(0x2774), 0x00007ffc },
{ _MMIO(0x2778), 0x0007affa },
{ _MMIO(0x277c), 0x0000f5fd },
{ _MMIO(0x2780), 0x00079ffa },
{ _MMIO(0x2784), 0x0000f3fb },
{ _MMIO(0x2788), 0x0007bf7a },
{ _MMIO(0x278c), 0x0000f7e7 },
{ _MMIO(0x2790), 0x0007fefa },
{ _MMIO(0x2794), 0x0000f7cf },
{ _MMIO(0x2798), 0x00077ffa },
{ _MMIO(0x279c), 0x0000efdf },
{ _MMIO(0x27a0), 0x0006fffa },
{ _MMIO(0x27a4), 0x0000cfbf },
{ _MMIO(0x27a8), 0x0003fffa },
{ _MMIO(0x27ac), 0x00005f7f },
};
static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00015014 },
{ _MMIO(0xe658), 0x00025024 },
{ _MMIO(0xe758), 0x00035034 },
{ _MMIO(0xe45c), 0x00045044 },
{ _MMIO(0xe55c), 0x00055054 },
{ _MMIO(0xe65c), 0x00065064 },
};
static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
{ _MMIO(0x9888), 0x59800000 },
{ _MMIO(0x9888), 0x59800001 },
{ _MMIO(0x9888), 0x261e0000 },
{ _MMIO(0x9888), 0x281f000f },
{ _MMIO(0x9888), 0x2817001a },
{ _MMIO(0x9888), 0x2791001f },
{ _MMIO(0x9888), 0x27880019 },
{ _MMIO(0x9888), 0x2d890000 },
{ _MMIO(0x9888), 0x278a0007 },
{ _MMIO(0x9888), 0x298d001f },
{ _MMIO(0x9888), 0x278e0020 },
{ _MMIO(0x9888), 0x2b8f0012 },
{ _MMIO(0x9888), 0x29900000 },
{ _MMIO(0x9888), 0x00184000 },
{ _MMIO(0x9888), 0x02181000 },
{ _MMIO(0x9888), 0x02194000 },
{ _MMIO(0x9888), 0x141e0002 },
{ _MMIO(0x9888), 0x041e0000 },
{ _MMIO(0x9888), 0x001e0000 },
{ _MMIO(0x9888), 0x221f0015 },
{ _MMIO(0x9888), 0x041f0000 },
{ _MMIO(0x9888), 0x001f4000 },
{ _MMIO(0x9888), 0x021f0000 },
{ _MMIO(0x9888), 0x023a8000 },
{ _MMIO(0x9888), 0x0213c000 },
{ _MMIO(0x9888), 0x02164000 },
{ _MMIO(0x9888), 0x24170012 },
{ _MMIO(0x9888), 0x04170000 },
{ _MMIO(0x9888), 0x07910005 },
{ _MMIO(0x9888), 0x05910000 },
{ _MMIO(0x9888), 0x01911500 },
{ _MMIO(0x9888), 0x03910501 },
{ _MMIO(0x9888), 0x0d880002 },
{ _MMIO(0x9888), 0x1d880003 },
{ _MMIO(0x9888), 0x05880000 },
{ _MMIO(0x9888), 0x0b890032 },
{ _MMIO(0x9888), 0x1b890031 },
{ _MMIO(0x9888), 0x05890000 },
{ _MMIO(0x9888), 0x01890040 },
{ _MMIO(0x9888), 0x03890040 },
{ _MMIO(0x9888), 0x098a0000 },
{ _MMIO(0x9888), 0x198a0004 },
{ _MMIO(0x9888), 0x058a0000 },
{ _MMIO(0x9888), 0x018a8050 },
{ _MMIO(0x9888), 0x038a2050 },
{ _MMIO(0x9888), 0x018b95a9 },
{ _MMIO(0x9888), 0x038be5a9 },
{ _MMIO(0x9888), 0x018c1500 },
{ _MMIO(0x9888), 0x038c0501 },
{ _MMIO(0x9888), 0x178d0015 },
{ _MMIO(0x9888), 0x058d0000 },
{ _MMIO(0x9888), 0x138e0004 },
{ _MMIO(0x9888), 0x218e000c },
{ _MMIO(0x9888), 0x058e0000 },
{ _MMIO(0x9888), 0x018e0500 },
{ _MMIO(0x9888), 0x038e0101 },
{ _MMIO(0x9888), 0x0f8f0027 },
{ _MMIO(0x9888), 0x058f0000 },
{ _MMIO(0x9888), 0x018f0000 },
{ _MMIO(0x9888), 0x038f0001 },
{ _MMIO(0x9888), 0x11900013 },
{ _MMIO(0x9888), 0x1f900017 },
{ _MMIO(0x9888), 0x05900000 },
{ _MMIO(0x9888), 0x01900100 },
{ _MMIO(0x9888), 0x03900001 },
{ _MMIO(0x9888), 0x01845555 },
{ _MMIO(0x9888), 0x03845555 },
{ _MMIO(0x9888), 0x418000aa },
{ _MMIO(0x9888), 0x438000aa },
{ _MMIO(0x9888), 0x458000aa },
{ _MMIO(0x9888), 0x478000aa },
{ _MMIO(0x9888), 0x4980018c },
{ _MMIO(0x9888), 0x4b80014b },
{ _MMIO(0x9888), 0x4d800128 },
{ _MMIO(0x9888), 0x4f80012a },
{ _MMIO(0x9888), 0x51800187 },
{ _MMIO(0x9888), 0x5380014b },
{ _MMIO(0x9888), 0x55800149 },
{ _MMIO(0x9888), 0x5780010a },
{ _MMIO(0x9888), 0x59800000 },
};
static int
get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_render_pipe_profile;
lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x10800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x00000002 },
{ _MMIO(0x2774), 0x0000fff7 },
};
static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
{ _MMIO(0x9888), 0x105c0232 },
{ _MMIO(0x9888), 0x10580232 },
{ _MMIO(0x9888), 0x10380232 },
{ _MMIO(0x9888), 0x10dc0232 },
{ _MMIO(0x9888), 0x10d80232 },
{ _MMIO(0x9888), 0x10b80232 },
{ _MMIO(0x9888), 0x118e4400 },
{ _MMIO(0x9888), 0x025c6080 },
{ _MMIO(0x9888), 0x045c004b },
{ _MMIO(0x9888), 0x005c8000 },
{ _MMIO(0x9888), 0x00582080 },
{ _MMIO(0x9888), 0x0258004b },
{ _MMIO(0x9888), 0x025b4000 },
{ _MMIO(0x9888), 0x045b4000 },
{ _MMIO(0x9888), 0x0c1fa000 },
{ _MMIO(0x9888), 0x0e1f00aa },
{ _MMIO(0x9888), 0x04386080 },
{ _MMIO(0x9888), 0x0638404b },
{ _MMIO(0x9888), 0x02384000 },
{ _MMIO(0x9888), 0x08384000 },
{ _MMIO(0x9888), 0x0a380000 },
{ _MMIO(0x9888), 0x0c380000 },
{ _MMIO(0x9888), 0x00398000 },
{ _MMIO(0x9888), 0x0239a000 },
{ _MMIO(0x9888), 0x0439a000 },
{ _MMIO(0x9888), 0x06392000 },
{ _MMIO(0x9888), 0x0cdc25c1 },
{ _MMIO(0x9888), 0x0adcc000 },
{ _MMIO(0x9888), 0x0ad825c1 },
{ _MMIO(0x9888), 0x18db4000 },
{ _MMIO(0x9888), 0x1adb0001 },
{ _MMIO(0x9888), 0x0e9f8000 },
{ _MMIO(0x9888), 0x109f02aa },
{ _MMIO(0x9888), 0x0eb825c1 },
{ _MMIO(0x9888), 0x18b80154 },
{ _MMIO(0x9888), 0x0ab9a000 },
{ _MMIO(0x9888), 0x0cb9a000 },
{ _MMIO(0x9888), 0x0eb9a000 },
{ _MMIO(0x9888), 0x0d88c000 },
{ _MMIO(0x9888), 0x0f88000f },
{ _MMIO(0x9888), 0x038a8000 },
{ _MMIO(0x9888), 0x058a8000 },
{ _MMIO(0x9888), 0x078a8000 },
{ _MMIO(0x9888), 0x098a8000 },
{ _MMIO(0x9888), 0x0b8a8000 },
{ _MMIO(0x9888), 0x0d8a8000 },
{ _MMIO(0x9888), 0x258baa05 },
{ _MMIO(0x9888), 0x278b002a },
{ _MMIO(0x9888), 0x238b2a80 },
{ _MMIO(0x9888), 0x198c5400 },
{ _MMIO(0x9888), 0x1b8c0015 },
{ _MMIO(0x9888), 0x098dc000 },
{ _MMIO(0x9888), 0x0b8da000 },
{ _MMIO(0x9888), 0x0d8da000 },
{ _MMIO(0x9888), 0x0f8da000 },
{ _MMIO(0x9888), 0x098e05c0 },
{ _MMIO(0x9888), 0x058e0000 },
{ _MMIO(0x9888), 0x198f0020 },
{ _MMIO(0x9888), 0x2185aa0a },
{ _MMIO(0x9888), 0x2385002a },
{ _MMIO(0x9888), 0x1f85aa00 },
{ _MMIO(0x9888), 0x19835000 },
{ _MMIO(0x9888), 0x1b830155 },
{ _MMIO(0x9888), 0x03834000 },
{ _MMIO(0x9888), 0x05834000 },
{ _MMIO(0x9888), 0x07834000 },
{ _MMIO(0x9888), 0x09834000 },
{ _MMIO(0x9888), 0x0b834000 },
{ _MMIO(0x9888), 0x0d834000 },
{ _MMIO(0x9888), 0x09848000 },
{ _MMIO(0x9888), 0x0b84c000 },
{ _MMIO(0x9888), 0x0d84c000 },
{ _MMIO(0x9888), 0x0f84c000 },
{ _MMIO(0x9888), 0x01848000 },
{ _MMIO(0x9888), 0x0384c000 },
{ _MMIO(0x9888), 0x0584c000 },
{ _MMIO(0x9888), 0x07844000 },
{ _MMIO(0x9888), 0x19808000 },
{ _MMIO(0x9888), 0x1b80c000 },
{ _MMIO(0x9888), 0x1d80c000 },
{ _MMIO(0x9888), 0x1f80c000 },
{ _MMIO(0x9888), 0x11808000 },
{ _MMIO(0x9888), 0x1380c000 },
{ _MMIO(0x9888), 0x1580c000 },
{ _MMIO(0x9888), 0x17804000 },
{ _MMIO(0x9888), 0x51800040 },
{ _MMIO(0x9888), 0x43800400 },
{ _MMIO(0x9888), 0x45800800 },
{ _MMIO(0x9888), 0x53800000 },
{ _MMIO(0x9888), 0x47800c62 },
{ _MMIO(0x9888), 0x21800000 },
{ _MMIO(0x9888), 0x31800000 },
{ _MMIO(0x9888), 0x4d800000 },
{ _MMIO(0x9888), 0x3f801042 },
{ _MMIO(0x9888), 0x4f800000 },
{ _MMIO(0x9888), 0x418014a4 },
};
static int
get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_hdc_and_sf;
lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_l3_1[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2770), 0x00100070 },
{ _MMIO(0x2774), 0x0000fff1 },
{ _MMIO(0x2778), 0x00014002 },
{ _MMIO(0x277c), 0x0000c3ff },
{ _MMIO(0x2780), 0x00010002 },
{ _MMIO(0x2784), 0x0000c7ff },
{ _MMIO(0x2788), 0x00004002 },
{ _MMIO(0x278c), 0x0000d3ff },
{ _MMIO(0x2790), 0x00100700 },
{ _MMIO(0x2794), 0x0000ff1f },
{ _MMIO(0x2798), 0x00001402 },
{ _MMIO(0x279c), 0x0000fc3f },
{ _MMIO(0x27a0), 0x00001002 },
{ _MMIO(0x27a4), 0x0000fc7f },
{ _MMIO(0x27a8), 0x00000402 },
{ _MMIO(0x27ac), 0x0000fd3f },
};
static const struct i915_oa_reg flex_eu_config_l3_1[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_l3_1[] = {
{ _MMIO(0x9888), 0x10bf03da },
{ _MMIO(0x9888), 0x14bf0001 },
{ _MMIO(0x9888), 0x12980340 },
{ _MMIO(0x9888), 0x12990340 },
{ _MMIO(0x9888), 0x0cbf1187 },
{ _MMIO(0x9888), 0x0ebf1205 },
{ _MMIO(0x9888), 0x00bf0500 },
{ _MMIO(0x9888), 0x02bf042b },
{ _MMIO(0x9888), 0x04bf002c },
{ _MMIO(0x9888), 0x0cdac000 },
{ _MMIO(0x9888), 0x0edac000 },
{ _MMIO(0x9888), 0x00da8000 },
{ _MMIO(0x9888), 0x02dac000 },
{ _MMIO(0x9888), 0x04da4000 },
{ _MMIO(0x9888), 0x04983400 },
{ _MMIO(0x9888), 0x10980000 },
{ _MMIO(0x9888), 0x06990034 },
{ _MMIO(0x9888), 0x10990000 },
{ _MMIO(0x9888), 0x0c9dc000 },
{ _MMIO(0x9888), 0x0e9dc000 },
{ _MMIO(0x9888), 0x009d8000 },
{ _MMIO(0x9888), 0x029dc000 },
{ _MMIO(0x9888), 0x049d4000 },
{ _MMIO(0x9888), 0x109f02a8 },
{ _MMIO(0x9888), 0x0c9fa000 },
{ _MMIO(0x9888), 0x0e9f00ba },
{ _MMIO(0x9888), 0x0cb88000 },
{ _MMIO(0x9888), 0x0cb95000 },
{ _MMIO(0x9888), 0x0eb95000 },
{ _MMIO(0x9888), 0x00b94000 },
{ _MMIO(0x9888), 0x02b95000 },
{ _MMIO(0x9888), 0x04b91000 },
{ _MMIO(0x9888), 0x06b92000 },
{ _MMIO(0x9888), 0x0cba4000 },
{ _MMIO(0x9888), 0x0f88000f },
{ _MMIO(0x9888), 0x03888000 },
{ _MMIO(0x9888), 0x05888000 },
{ _MMIO(0x9888), 0x07888000 },
{ _MMIO(0x9888), 0x09888000 },
{ _MMIO(0x9888), 0x0b888000 },
{ _MMIO(0x9888), 0x0d880400 },
{ _MMIO(0x9888), 0x258b800a },
{ _MMIO(0x9888), 0x278b002a },
{ _MMIO(0x9888), 0x238b5500 },
{ _MMIO(0x9888), 0x198c4000 },
{ _MMIO(0x9888), 0x1b8c0015 },
{ _MMIO(0x9888), 0x038c4000 },
{ _MMIO(0x9888), 0x058c4000 },
{ _MMIO(0x9888), 0x078c4000 },
{ _MMIO(0x9888), 0x098c4000 },
{ _MMIO(0x9888), 0x0b8c4000 },
{ _MMIO(0x9888), 0x0d8c4000 },
{ _MMIO(0x9888), 0x0d8da000 },
{ _MMIO(0x9888), 0x0f8da000 },
{ _MMIO(0x9888), 0x018d8000 },
{ _MMIO(0x9888), 0x038da000 },
{ _MMIO(0x9888), 0x058da000 },
{ _MMIO(0x9888), 0x078d2000 },
{ _MMIO(0x9888), 0x2185800a },
{ _MMIO(0x9888), 0x2385002a },
{ _MMIO(0x9888), 0x1f85aa00 },
{ _MMIO(0x9888), 0x1b830154 },
{ _MMIO(0x9888), 0x03834000 },
{ _MMIO(0x9888), 0x05834000 },
{ _MMIO(0x9888), 0x07834000 },
{ _MMIO(0x9888), 0x09834000 },
{ _MMIO(0x9888), 0x0b834000 },
{ _MMIO(0x9888), 0x0d834000 },
{ _MMIO(0x9888), 0x0d84c000 },
{ _MMIO(0x9888), 0x0f84c000 },
{ _MMIO(0x9888), 0x01848000 },
{ _MMIO(0x9888), 0x0384c000 },
{ _MMIO(0x9888), 0x0584c000 },
{ _MMIO(0x9888), 0x07844000 },
{ _MMIO(0x9888), 0x1d80c000 },
{ _MMIO(0x9888), 0x1f80c000 },
{ _MMIO(0x9888), 0x11808000 },
{ _MMIO(0x9888), 0x1380c000 },
{ _MMIO(0x9888), 0x1580c000 },
{ _MMIO(0x9888), 0x17804000 },
{ _MMIO(0x9888), 0x53800000 },
{ _MMIO(0x9888), 0x45800000 },
{ _MMIO(0x9888), 0x47800000 },
{ _MMIO(0x9888), 0x21800000 },
{ _MMIO(0x9888), 0x31800000 },
{ _MMIO(0x9888), 0x4d800000 },
{ _MMIO(0x9888), 0x3f800000 },
{ _MMIO(0x9888), 0x4f800000 },
{ _MMIO(0x9888), 0x41800060 },
};
static int
get_l3_1_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_l3_1;
lens[n] = ARRAY_SIZE(mux_config_l3_1);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_l3_2[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2770), 0x00100070 },
{ _MMIO(0x2774), 0x0000fff1 },
{ _MMIO(0x2778), 0x00014002 },
{ _MMIO(0x277c), 0x0000c3ff },
{ _MMIO(0x2780), 0x00010002 },
{ _MMIO(0x2784), 0x0000c7ff },
{ _MMIO(0x2788), 0x00004002 },
{ _MMIO(0x278c), 0x0000d3ff },
{ _MMIO(0x2790), 0x00100700 },
{ _MMIO(0x2794), 0x0000ff1f },
{ _MMIO(0x2798), 0x00001402 },
{ _MMIO(0x279c), 0x0000fc3f },
{ _MMIO(0x27a0), 0x00001002 },
{ _MMIO(0x27a4), 0x0000fc7f },
{ _MMIO(0x27a8), 0x00000402 },
{ _MMIO(0x27ac), 0x0000fd3f },
};
static const struct i915_oa_reg flex_eu_config_l3_2[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_l3_2[] = {
{ _MMIO(0x9888), 0x103f03da },
{ _MMIO(0x9888), 0x143f0001 },
{ _MMIO(0x9888), 0x12180340 },
{ _MMIO(0x9888), 0x12190340 },
{ _MMIO(0x9888), 0x0c3f1187 },
{ _MMIO(0x9888), 0x0e3f1205 },
{ _MMIO(0x9888), 0x003f0500 },
{ _MMIO(0x9888), 0x023f042b },
{ _MMIO(0x9888), 0x043f002c },
{ _MMIO(0x9888), 0x0c5ac000 },
{ _MMIO(0x9888), 0x0e5ac000 },
{ _MMIO(0x9888), 0x005a8000 },
{ _MMIO(0x9888), 0x025ac000 },
{ _MMIO(0x9888), 0x045a4000 },
{ _MMIO(0x9888), 0x04183400 },
{ _MMIO(0x9888), 0x10180000 },
{ _MMIO(0x9888), 0x06190034 },
{ _MMIO(0x9888), 0x10190000 },
{ _MMIO(0x9888), 0x0c1dc000 },
{ _MMIO(0x9888), 0x0e1dc000 },
{ _MMIO(0x9888), 0x001d8000 },
{ _MMIO(0x9888), 0x021dc000 },
{ _MMIO(0x9888), 0x041d4000 },
{ _MMIO(0x9888), 0x101f02a8 },
{ _MMIO(0x9888), 0x0c1fa000 },
{ _MMIO(0x9888), 0x0e1f00ba },
{ _MMIO(0x9888), 0x0c388000 },
{ _MMIO(0x9888), 0x0c395000 },
{ _MMIO(0x9888), 0x0e395000 },
{ _MMIO(0x9888), 0x00394000 },
{ _MMIO(0x9888), 0x02395000 },
{ _MMIO(0x9888), 0x04391000 },
{ _MMIO(0x9888), 0x06392000 },
{ _MMIO(0x9888), 0x0c3a4000 },
{ _MMIO(0x9888), 0x1b8aa800 },
{ _MMIO(0x9888), 0x1d8a0002 },
{ _MMIO(0x9888), 0x038a8000 },
{ _MMIO(0x9888), 0x058a8000 },
{ _MMIO(0x9888), 0x078a8000 },
{ _MMIO(0x9888), 0x098a8000 },
{ _MMIO(0x9888), 0x0b8a8000 },
{ _MMIO(0x9888), 0x0d8a8000 },
{ _MMIO(0x9888), 0x258b4005 },
{ _MMIO(0x9888), 0x278b0015 },
{ _MMIO(0x9888), 0x238b2a80 },
{ _MMIO(0x9888), 0x2185800a },
{ _MMIO(0x9888), 0x2385002a },
{ _MMIO(0x9888), 0x1f85aa00 },
{ _MMIO(0x9888), 0x1b830154 },
{ _MMIO(0x9888), 0x03834000 },
{ _MMIO(0x9888), 0x05834000 },
{ _MMIO(0x9888), 0x07834000 },
{ _MMIO(0x9888), 0x09834000 },
{ _MMIO(0x9888), 0x0b834000 },
{ _MMIO(0x9888), 0x0d834000 },
{ _MMIO(0x9888), 0x0d84c000 },
{ _MMIO(0x9888), 0x0f84c000 },
{ _MMIO(0x9888), 0x01848000 },
{ _MMIO(0x9888), 0x0384c000 },
{ _MMIO(0x9888), 0x0584c000 },
{ _MMIO(0x9888), 0x07844000 },
{ _MMIO(0x9888), 0x1d80c000 },
{ _MMIO(0x9888), 0x1f80c000 },
{ _MMIO(0x9888), 0x11808000 },
{ _MMIO(0x9888), 0x1380c000 },
{ _MMIO(0x9888), 0x1580c000 },
{ _MMIO(0x9888), 0x17804000 },
{ _MMIO(0x9888), 0x53800000 },
{ _MMIO(0x9888), 0x45800000 },
{ _MMIO(0x9888), 0x47800000 },
{ _MMIO(0x9888), 0x21800000 },
{ _MMIO(0x9888), 0x31800000 },
{ _MMIO(0x9888), 0x4d800000 },
{ _MMIO(0x9888), 0x3f800000 },
{ _MMIO(0x9888), 0x4f800000 },
{ _MMIO(0x9888), 0x41800060 },
};
static int
get_l3_2_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_l3_2;
lens[n] = ARRAY_SIZE(mux_config_l3_2);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_l3_3[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2770), 0x00100070 },
{ _MMIO(0x2774), 0x0000fff1 },
{ _MMIO(0x2778), 0x00014002 },
{ _MMIO(0x277c), 0x0000c3ff },
{ _MMIO(0x2780), 0x00010002 },
{ _MMIO(0x2784), 0x0000c7ff },
{ _MMIO(0x2788), 0x00004002 },
{ _MMIO(0x278c), 0x0000d3ff },
{ _MMIO(0x2790), 0x00100700 },
{ _MMIO(0x2794), 0x0000ff1f },
{ _MMIO(0x2798), 0x00001402 },
{ _MMIO(0x279c), 0x0000fc3f },
{ _MMIO(0x27a0), 0x00001002 },
{ _MMIO(0x27a4), 0x0000fc7f },
{ _MMIO(0x27a8), 0x00000402 },
{ _MMIO(0x27ac), 0x0000fd3f },
};
static const struct i915_oa_reg flex_eu_config_l3_3[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_l3_3[] = {
{ _MMIO(0x9888), 0x121b0340 },
{ _MMIO(0x9888), 0x103f0274 },
{ _MMIO(0x9888), 0x123f0000 },
{ _MMIO(0x9888), 0x129b0340 },
{ _MMIO(0x9888), 0x10bf0274 },
{ _MMIO(0x9888), 0x12bf0000 },
{ _MMIO(0x9888), 0x041b3400 },
{ _MMIO(0x9888), 0x101b0000 },
{ _MMIO(0x9888), 0x045c8000 },
{ _MMIO(0x9888), 0x0a3d4000 },
{ _MMIO(0x9888), 0x003f0080 },
{ _MMIO(0x9888), 0x023f0793 },
{ _MMIO(0x9888), 0x043f0014 },
{ _MMIO(0x9888), 0x04588000 },
{ _MMIO(0x9888), 0x005a8000 },
{ _MMIO(0x9888), 0x025ac000 },
{ _MMIO(0x9888), 0x045a4000 },
{ _MMIO(0x9888), 0x0a5b4000 },
{ _MMIO(0x9888), 0x001d8000 },
{ _MMIO(0x9888), 0x021dc000 },
{ _MMIO(0x9888), 0x041d4000 },
{ _MMIO(0x9888), 0x0c1fa000 },
{ _MMIO(0x9888), 0x0e1f002a },
{ _MMIO(0x9888), 0x0a384000 },
{ _MMIO(0x9888), 0x00394000 },
{ _MMIO(0x9888), 0x02395000 },
{ _MMIO(0x9888), 0x04399000 },
{ _MMIO(0x9888), 0x069b0034 },
{ _MMIO(0x9888), 0x109b0000 },
{ _MMIO(0x9888), 0x06dc4000 },
{ _MMIO(0x9888), 0x0cbd4000 },
{ _MMIO(0x9888), 0x0cbf0981 },
{ _MMIO(0x9888), 0x0ebf0a0f },
{ _MMIO(0x9888), 0x06d84000 },
{ _MMIO(0x9888), 0x0cdac000 },
{ _MMIO(0x9888), 0x0edac000 },
{ _MMIO(0x9888), 0x0cdb4000 },
{ _MMIO(0x9888), 0x0c9dc000 },
{ _MMIO(0x9888), 0x0e9dc000 },
{ _MMIO(0x9888), 0x109f02a8 },
{ _MMIO(0x9888), 0x0e9f0080 },
{ _MMIO(0x9888), 0x0cb84000 },
{ _MMIO(0x9888), 0x0cb95000 },
{ _MMIO(0x9888), 0x0eb95000 },
{ _MMIO(0x9888), 0x06b92000 },
{ _MMIO(0x9888), 0x0f88000f },
{ _MMIO(0x9888), 0x0d880400 },
{ _MMIO(0x9888), 0x038a8000 },
{ _MMIO(0x9888), 0x058a8000 },
{ _MMIO(0x9888), 0x078a8000 },
{ _MMIO(0x9888), 0x098a8000 },
{ _MMIO(0x9888), 0x0b8a8000 },
{ _MMIO(0x9888), 0x258b8009 },
{ _MMIO(0x9888), 0x278b002a },
{ _MMIO(0x9888), 0x238b2a80 },
{ _MMIO(0x9888), 0x198c4000 },
{ _MMIO(0x9888), 0x1b8c0015 },
{ _MMIO(0x9888), 0x0d8c4000 },
{ _MMIO(0x9888), 0x0d8da000 },
{ _MMIO(0x9888), 0x0f8da000 },
{ _MMIO(0x9888), 0x078d2000 },
{ _MMIO(0x9888), 0x2185800a },
{ _MMIO(0x9888), 0x2385002a },
{ _MMIO(0x9888), 0x1f85aa00 },
{ _MMIO(0x9888), 0x1b830154 },
{ _MMIO(0x9888), 0x03834000 },
{ _MMIO(0x9888), 0x05834000 },
{ _MMIO(0x9888), 0x07834000 },
{ _MMIO(0x9888), 0x09834000 },
{ _MMIO(0x9888), 0x0b834000 },
{ _MMIO(0x9888), 0x0d834000 },
{ _MMIO(0x9888), 0x0d84c000 },
{ _MMIO(0x9888), 0x0f84c000 },
{ _MMIO(0x9888), 0x01848000 },
{ _MMIO(0x9888), 0x0384c000 },
{ _MMIO(0x9888), 0x0584c000 },
{ _MMIO(0x9888), 0x07844000 },
{ _MMIO(0x9888), 0x1d80c000 },
{ _MMIO(0x9888), 0x1f80c000 },
{ _MMIO(0x9888), 0x11808000 },
{ _MMIO(0x9888), 0x1380c000 },
{ _MMIO(0x9888), 0x1580c000 },
{ _MMIO(0x9888), 0x17804000 },
{ _MMIO(0x9888), 0x53800000 },
{ _MMIO(0x9888), 0x45800c00 },
{ _MMIO(0x9888), 0x47800c63 },
{ _MMIO(0x9888), 0x21800000 },
{ _MMIO(0x9888), 0x31800000 },
{ _MMIO(0x9888), 0x4d800000 },
{ _MMIO(0x9888), 0x3f8014a5 },
{ _MMIO(0x9888), 0x4f800000 },
{ _MMIO(0x9888), 0x41800045 },
};
static int
get_l3_3_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_l3_3;
lens[n] = ARRAY_SIZE(mux_config_l3_3);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_l3_4[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2770), 0x00100070 },
{ _MMIO(0x2774), 0x0000fff1 },
{ _MMIO(0x2778), 0x00014002 },
{ _MMIO(0x277c), 0x0000c3ff },
{ _MMIO(0x2780), 0x00010002 },
{ _MMIO(0x2784), 0x0000c7ff },
{ _MMIO(0x2788), 0x00004002 },
{ _MMIO(0x278c), 0x0000d3ff },
{ _MMIO(0x2790), 0x00100700 },
{ _MMIO(0x2794), 0x0000ff1f },
{ _MMIO(0x2798), 0x00001402 },
{ _MMIO(0x279c), 0x0000fc3f },
{ _MMIO(0x27a0), 0x00001002 },
{ _MMIO(0x27a4), 0x0000fc7f },
{ _MMIO(0x27a8), 0x00000402 },
{ _MMIO(0x27ac), 0x0000fd3f },
};
static const struct i915_oa_reg flex_eu_config_l3_4[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_l3_4[] = {
{ _MMIO(0x9888), 0x121a0340 },
{ _MMIO(0x9888), 0x103f0017 },
{ _MMIO(0x9888), 0x123f0020 },
{ _MMIO(0x9888), 0x129a0340 },
{ _MMIO(0x9888), 0x10bf0017 },
{ _MMIO(0x9888), 0x12bf0020 },
{ _MMIO(0x9888), 0x041a3400 },
{ _MMIO(0x9888), 0x101a0000 },
{ _MMIO(0x9888), 0x043b8000 },
{ _MMIO(0x9888), 0x0a3e0010 },
{ _MMIO(0x9888), 0x003f0200 },
{ _MMIO(0x9888), 0x023f0113 },
{ _MMIO(0x9888), 0x043f0014 },
{ _MMIO(0x9888), 0x02592000 },
{ _MMIO(0x9888), 0x005a8000 },
{ _MMIO(0x9888), 0x025ac000 },
{ _MMIO(0x9888), 0x045a4000 },
{ _MMIO(0x9888), 0x0a1c8000 },
{ _MMIO(0x9888), 0x001d8000 },
{ _MMIO(0x9888), 0x021dc000 },
{ _MMIO(0x9888), 0x041d4000 },
{ _MMIO(0x9888), 0x0a1e8000 },
{ _MMIO(0x9888), 0x0c1fa000 },
{ _MMIO(0x9888), 0x0e1f001a },
{ _MMIO(0x9888), 0x00394000 },
{ _MMIO(0x9888), 0x02395000 },
{ _MMIO(0x9888), 0x04391000 },
{ _MMIO(0x9888), 0x069a0034 },
{ _MMIO(0x9888), 0x109a0000 },
{ _MMIO(0x9888), 0x06bb4000 },
{ _MMIO(0x9888), 0x0abe0040 },
{ _MMIO(0x9888), 0x0cbf0984 },
{ _MMIO(0x9888), 0x0ebf0a02 },
{ _MMIO(0x9888), 0x02d94000 },
{ _MMIO(0x9888), 0x0cdac000 },
{ _MMIO(0x9888), 0x0edac000 },
{ _MMIO(0x9888), 0x0c9c0400 },
{ _MMIO(0x9888), 0x0c9dc000 },
{ _MMIO(0x9888), 0x0e9dc000 },
{ _MMIO(0x9888), 0x0c9e0400 },
{ _MMIO(0x9888), 0x109f02a8 },
{ _MMIO(0x9888), 0x0e9f0040 },
{ _MMIO(0x9888), 0x0cb95000 },
{ _MMIO(0x9888), 0x0eb95000 },
{ _MMIO(0x9888), 0x0f88000f },
{ _MMIO(0x9888), 0x0d880400 },
{ _MMIO(0x9888), 0x038a8000 },
{ _MMIO(0x9888), 0x058a8000 },
{ _MMIO(0x9888), 0x078a8000 },
{ _MMIO(0x9888), 0x098a8000 },
{ _MMIO(0x9888), 0x0b8a8000 },
{ _MMIO(0x9888), 0x258b8009 },
{ _MMIO(0x9888), 0x278b002a },
{ _MMIO(0x9888), 0x238b2a80 },
{ _MMIO(0x9888), 0x198c4000 },
{ _MMIO(0x9888), 0x1b8c0015 },
{ _MMIO(0x9888), 0x0d8c4000 },
{ _MMIO(0x9888), 0x0d8da000 },
{ _MMIO(0x9888), 0x0f8da000 },
{ _MMIO(0x9888), 0x078d2000 },
{ _MMIO(0x9888), 0x2185800a },
{ _MMIO(0x9888), 0x2385002a },
{ _MMIO(0x9888), 0x1f85aa00 },
{ _MMIO(0x9888), 0x1b830154 },
{ _MMIO(0x9888), 0x03834000 },
{ _MMIO(0x9888), 0x05834000 },
{ _MMIO(0x9888), 0x07834000 },
{ _MMIO(0x9888), 0x09834000 },
{ _MMIO(0x9888), 0x0b834000 },
{ _MMIO(0x9888), 0x0d834000 },
{ _MMIO(0x9888), 0x0d84c000 },
{ _MMIO(0x9888), 0x0f84c000 },
{ _MMIO(0x9888), 0x01848000 },
{ _MMIO(0x9888), 0x0384c000 },
{ _MMIO(0x9888), 0x0584c000 },
{ _MMIO(0x9888), 0x07844000 },
{ _MMIO(0x9888), 0x1d80c000 },
{ _MMIO(0x9888), 0x1f80c000 },
{ _MMIO(0x9888), 0x11808000 },
{ _MMIO(0x9888), 0x1380c000 },
{ _MMIO(0x9888), 0x1580c000 },
{ _MMIO(0x9888), 0x17804000 },
{ _MMIO(0x9888), 0x53800000 },
{ _MMIO(0x9888), 0x45800800 },
{ _MMIO(0x9888), 0x47800842 },
{ _MMIO(0x9888), 0x21800000 },
{ _MMIO(0x9888), 0x31800000 },
{ _MMIO(0x9888), 0x4d800000 },
{ _MMIO(0x9888), 0x3f801084 },
{ _MMIO(0x9888), 0x4f800000 },
{ _MMIO(0x9888), 0x41800044 },
};
static int
get_l3_4_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_l3_4;
lens[n] = ARRAY_SIZE(mux_config_l3_4);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x30800000 },
{ _MMIO(0x2770), 0x00006000 },
{ _MMIO(0x2774), 0x0000f3ff },
{ _MMIO(0x2778), 0x00001800 },
{ _MMIO(0x277c), 0x0000fcff },
{ _MMIO(0x2780), 0x00000600 },
{ _MMIO(0x2784), 0x0000ff3f },
{ _MMIO(0x2788), 0x00000180 },
{ _MMIO(0x278c), 0x0000ffcf },
{ _MMIO(0x2790), 0x00000060 },
{ _MMIO(0x2794), 0x0000fff3 },
{ _MMIO(0x2798), 0x00000018 },
{ _MMIO(0x279c), 0x0000fffc },
};
static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
{ _MMIO(0x9888), 0x143b000e },
{ _MMIO(0x9888), 0x043c55c0 },
{ _MMIO(0x9888), 0x0a1e0280 },
{ _MMIO(0x9888), 0x0c1e0408 },
{ _MMIO(0x9888), 0x10390000 },
{ _MMIO(0x9888), 0x12397a1f },
{ _MMIO(0x9888), 0x14bb000e },
{ _MMIO(0x9888), 0x04bc5000 },
{ _MMIO(0x9888), 0x0a9e0296 },
{ _MMIO(0x9888), 0x0c9e0008 },
{ _MMIO(0x9888), 0x10b90000 },
{ _MMIO(0x9888), 0x12b97a1f },
{ _MMIO(0x9888), 0x063b0042 },
{ _MMIO(0x9888), 0x103b0000 },
{ _MMIO(0x9888), 0x083c0000 },
{ _MMIO(0x9888), 0x0a3e0040 },
{ _MMIO(0x9888), 0x043f8000 },
{ _MMIO(0x9888), 0x02594000 },
{ _MMIO(0x9888), 0x045a8000 },
{ _MMIO(0x9888), 0x0c1c0400 },
{ _MMIO(0x9888), 0x041d8000 },
{ _MMIO(0x9888), 0x081e02c0 },
{ _MMIO(0x9888), 0x0e1e0000 },
{ _MMIO(0x9888), 0x0c1fa800 },
{ _MMIO(0x9888), 0x0e1f0260 },
{ _MMIO(0x9888), 0x101f0014 },
{ _MMIO(0x9888), 0x003905e0 },
{ _MMIO(0x9888), 0x06390bc0 },
{ _MMIO(0x9888), 0x02390018 },
{ _MMIO(0x9888), 0x04394000 },
{ _MMIO(0x9888), 0x04bb0042 },
{ _MMIO(0x9888), 0x10bb0000 },
{ _MMIO(0x9888), 0x02bc05c0 },
{ _MMIO(0x9888), 0x08bc0000 },
{ _MMIO(0x9888), 0x0abe0004 },
{ _MMIO(0x9888), 0x02bf8000 },
{ _MMIO(0x9888), 0x02d91000 },
{ _MMIO(0x9888), 0x02da8000 },
{ _MMIO(0x9888), 0x089c8000 },
{ _MMIO(0x9888), 0x029d8000 },
{ _MMIO(0x9888), 0x089e8000 },
{ _MMIO(0x9888), 0x0e9e0000 },
{ _MMIO(0x9888), 0x0e9fa806 },
{ _MMIO(0x9888), 0x109f0142 },
{ _MMIO(0x9888), 0x08b90617 },
{ _MMIO(0x9888), 0x0ab90be0 },
{ _MMIO(0x9888), 0x02b94000 },
{ _MMIO(0x9888), 0x0d88f000 },
{ _MMIO(0x9888), 0x0f88000c },
{ _MMIO(0x9888), 0x07888000 },
{ _MMIO(0x9888), 0x09888000 },
{ _MMIO(0x9888), 0x018a8000 },
{ _MMIO(0x9888), 0x0f8a8000 },
{ _MMIO(0x9888), 0x1b8a2800 },
{ _MMIO(0x9888), 0x038a8000 },
{ _MMIO(0x9888), 0x058a8000 },
{ _MMIO(0x9888), 0x0b8a8000 },
{ _MMIO(0x9888), 0x0d8a8000 },
{ _MMIO(0x9888), 0x238b52a0 },
{ _MMIO(0x9888), 0x258b6a95 },
{ _MMIO(0x9888), 0x278b0029 },
{ _MMIO(0x9888), 0x178c2000 },
{ _MMIO(0x9888), 0x198c1500 },
{ _MMIO(0x9888), 0x1b8c0014 },
{ _MMIO(0x9888), 0x078c4000 },
{ _MMIO(0x9888), 0x098c4000 },
{ _MMIO(0x9888), 0x098da000 },
{ _MMIO(0x9888), 0x0b8da000 },
{ _MMIO(0x9888), 0x0f8da000 },
{ _MMIO(0x9888), 0x038d8000 },
{ _MMIO(0x9888), 0x058d2000 },
{ _MMIO(0x9888), 0x1f85aa80 },
{ _MMIO(0x9888), 0x2185aaaa },
{ _MMIO(0x9888), 0x2385002a },
{ _MMIO(0x9888), 0x01834000 },
{ _MMIO(0x9888), 0x0f834000 },
{ _MMIO(0x9888), 0x19835400 },
{ _MMIO(0x9888), 0x1b830155 },
{ _MMIO(0x9888), 0x03834000 },
{ _MMIO(0x9888), 0x05834000 },
{ _MMIO(0x9888), 0x07834000 },
{ _MMIO(0x9888), 0x09834000 },
{ _MMIO(0x9888), 0x0b834000 },
{ _MMIO(0x9888), 0x0d834000 },
{ _MMIO(0x9888), 0x0184c000 },
{ _MMIO(0x9888), 0x0784c000 },
{ _MMIO(0x9888), 0x0984c000 },
{ _MMIO(0x9888), 0x0b84c000 },
{ _MMIO(0x9888), 0x0d84c000 },
{ _MMIO(0x9888), 0x0f84c000 },
{ _MMIO(0x9888), 0x0384c000 },
{ _MMIO(0x9888), 0x0584c000 },
{ _MMIO(0x9888), 0x1180c000 },
{ _MMIO(0x9888), 0x1780c000 },
{ _MMIO(0x9888), 0x1980c000 },
{ _MMIO(0x9888), 0x1b80c000 },
{ _MMIO(0x9888), 0x1d80c000 },
{ _MMIO(0x9888), 0x1f80c000 },
{ _MMIO(0x9888), 0x1380c000 },
{ _MMIO(0x9888), 0x1580c000 },
{ _MMIO(0x9888), 0x4d800444 },
{ _MMIO(0x9888), 0x3d800000 },
{ _MMIO(0x9888), 0x4f804000 },
{ _MMIO(0x9888), 0x43801080 },
{ _MMIO(0x9888), 0x51800000 },
{ _MMIO(0x9888), 0x45800084 },
{ _MMIO(0x9888), 0x53800044 },
{ _MMIO(0x9888), 0x47801080 },
{ _MMIO(0x9888), 0x21800000 },
{ _MMIO(0x9888), 0x31800000 },
{ _MMIO(0x9888), 0x3f800000 },
{ _MMIO(0x9888), 0x41800840 },
};
static int
get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_rasterizer_and_pixel_backend;
lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_sampler_1[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x70800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x0000c000 },
{ _MMIO(0x2774), 0x0000e7ff },
{ _MMIO(0x2778), 0x00003000 },
{ _MMIO(0x277c), 0x0000f9ff },
{ _MMIO(0x2780), 0x00000c00 },
{ _MMIO(0x2784), 0x0000fe7f },
};
static const struct i915_oa_reg flex_eu_config_sampler_1[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_sampler_1[] = {
{ _MMIO(0x9888), 0x18921400 },
{ _MMIO(0x9888), 0x149500ab },
{ _MMIO(0x9888), 0x18b21400 },
{ _MMIO(0x9888), 0x14b500ab },
{ _MMIO(0x9888), 0x18d21400 },
{ _MMIO(0x9888), 0x14d500ab },
{ _MMIO(0x9888), 0x0cdc8000 },
{ _MMIO(0x9888), 0x0edc4000 },
{ _MMIO(0x9888), 0x02dcc000 },
{ _MMIO(0x9888), 0x04dcc000 },
{ _MMIO(0x9888), 0x1abd00a0 },
{ _MMIO(0x9888), 0x0abd8000 },
{ _MMIO(0x9888), 0x0cd88000 },
{ _MMIO(0x9888), 0x0ed84000 },
{ _MMIO(0x9888), 0x04d88000 },
{ _MMIO(0x9888), 0x1adb0050 },
{ _MMIO(0x9888), 0x04db8000 },
{ _MMIO(0x9888), 0x06db8000 },
{ _MMIO(0x9888), 0x08db8000 },
{ _MMIO(0x9888), 0x0adb4000 },
{ _MMIO(0x9888), 0x109f02a0 },
{ _MMIO(0x9888), 0x0c9fa000 },
{ _MMIO(0x9888), 0x0e9f00aa },
{ _MMIO(0x9888), 0x18b82500 },
{ _MMIO(0x9888), 0x02b88000 },
{ _MMIO(0x9888), 0x04b84000 },
{ _MMIO(0x9888), 0x06b84000 },
{ _MMIO(0x9888), 0x08b84000 },
{ _MMIO(0x9888), 0x0ab84000 },
{ _MMIO(0x9888), 0x0cb88000 },
{ _MMIO(0x9888), 0x0cb98000 },
{ _MMIO(0x9888), 0x0eb9a000 },
{ _MMIO(0x9888), 0x00b98000 },
{ _MMIO(0x9888), 0x02b9a000 },
{ _MMIO(0x9888), 0x04b9a000 },
{ _MMIO(0x9888), 0x06b92000 },
{ _MMIO(0x9888), 0x1aba0200 },
{ _MMIO(0x9888), 0x02ba8000 },
{ _MMIO(0x9888), 0x0cba8000 },
{ _MMIO(0x9888), 0x04908000 },
{ _MMIO(0x9888), 0x04918000 },
{ _MMIO(0x9888), 0x04927300 },
{ _MMIO(0x9888), 0x10920000 },
{ _MMIO(0x9888), 0x1893000a },
{ _MMIO(0x9888), 0x0a934000 },
{ _MMIO(0x9888), 0x0a946000 },
{ _MMIO(0x9888), 0x0c959000 },
{ _MMIO(0x9888), 0x0e950098 },
{ _MMIO(0x9888), 0x10950000 },
{ _MMIO(0x9888), 0x04b04000 },
{ _MMIO(0x9888), 0x04b14000 },
{ _MMIO(0x9888), 0x04b20073 },
{ _MMIO(0x9888), 0x10b20000 },
{ _MMIO(0x9888), 0x04b38000 },
{ _MMIO(0x9888), 0x06b38000 },
{ _MMIO(0x9888), 0x08b34000 },
{ _MMIO(0x9888), 0x04b4c000 },
{ _MMIO(0x9888), 0x02b59890 },
{ _MMIO(0x9888), 0x10b50000 },
{ _MMIO(0x9888), 0x06d04000 },
{ _MMIO(0x9888), 0x06d14000 },
{ _MMIO(0x9888), 0x06d20073 },
{ _MMIO(0x9888), 0x10d20000 },
{ _MMIO(0x9888), 0x18d30020 },
{ _MMIO(0x9888), 0x02d38000 },
{ _MMIO(0x9888), 0x0cd34000 },
{ _MMIO(0x9888), 0x0ad48000 },
{ _MMIO(0x9888), 0x04d42000 },
{ _MMIO(0x9888), 0x0ed59000 },
{ _MMIO(0x9888), 0x00d59800 },
{ _MMIO(0x9888), 0x10d50000 },
{ _MMIO(0x9888), 0x0f88000e },
{ _MMIO(0x9888), 0x03888000 },
{ _MMIO(0x9888), 0x05888000 },
{ _MMIO(0x9888), 0x07888000 },
{ _MMIO(0x9888), 0x09888000 },
{ _MMIO(0x9888), 0x0b888000 },
{ _MMIO(0x9888), 0x0d880400 },
{ _MMIO(0x9888), 0x278b002a },
{ _MMIO(0x9888), 0x238b5500 },
{ _MMIO(0x9888), 0x258b000a },
{ _MMIO(0x9888), 0x1b8c0015 },
{ _MMIO(0x9888), 0x038c4000 },
{ _MMIO(0x9888), 0x058c4000 },
{ _MMIO(0x9888), 0x078c4000 },
{ _MMIO(0x9888), 0x098c4000 },
{ _MMIO(0x9888), 0x0b8c4000 },
{ _MMIO(0x9888), 0x0d8c4000 },
{ _MMIO(0x9888), 0x0d8d8000 },
{ _MMIO(0x9888), 0x0f8da000 },
{ _MMIO(0x9888), 0x018d8000 },
{ _MMIO(0x9888), 0x038da000 },
{ _MMIO(0x9888), 0x058da000 },
{ _MMIO(0x9888), 0x078d2000 },
{ _MMIO(0x9888), 0x2385002a },
{ _MMIO(0x9888), 0x1f85aa00 },
{ _MMIO(0x9888), 0x2185000a },
{ _MMIO(0x9888), 0x1b830150 },
{ _MMIO(0x9888), 0x03834000 },
{ _MMIO(0x9888), 0x05834000 },
{ _MMIO(0x9888), 0x07834000 },
{ _MMIO(0x9888), 0x09834000 },
{ _MMIO(0x9888), 0x0b834000 },
{ _MMIO(0x9888), 0x0d834000 },
{ _MMIO(0x9888), 0x0d848000 },
{ _MMIO(0x9888), 0x0f84c000 },
{ _MMIO(0x9888), 0x01848000 },
{ _MMIO(0x9888), 0x0384c000 },
{ _MMIO(0x9888), 0x0584c000 },
{ _MMIO(0x9888), 0x07844000 },
{ _MMIO(0x9888), 0x1d808000 },
{ _MMIO(0x9888), 0x1f80c000 },
{ _MMIO(0x9888), 0x11808000 },
{ _MMIO(0x9888), 0x1380c000 },
{ _MMIO(0x9888), 0x1580c000 },
{ _MMIO(0x9888), 0x17804000 },
{ _MMIO(0x9888), 0x53800000 },
{ _MMIO(0x9888), 0x47801021 },
{ _MMIO(0x9888), 0x21800000 },
{ _MMIO(0x9888), 0x31800000 },
{ _MMIO(0x9888), 0x4d800000 },
{ _MMIO(0x9888), 0x3f800c64 },
{ _MMIO(0x9888), 0x4f800000 },
{ _MMIO(0x9888), 0x41800c02 },
};
static int
get_sampler_1_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_sampler_1;
lens[n] = ARRAY_SIZE(mux_config_sampler_1);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_sampler_2[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x70800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x0000c000 },
{ _MMIO(0x2774), 0x0000e7ff },
{ _MMIO(0x2778), 0x00003000 },
{ _MMIO(0x277c), 0x0000f9ff },
{ _MMIO(0x2780), 0x00000c00 },
{ _MMIO(0x2784), 0x0000fe7f },
};
static const struct i915_oa_reg flex_eu_config_sampler_2[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_sampler_2[] = {
{ _MMIO(0x9888), 0x18121400 },
{ _MMIO(0x9888), 0x141500ab },
{ _MMIO(0x9888), 0x18321400 },
{ _MMIO(0x9888), 0x143500ab },
{ _MMIO(0x9888), 0x18521400 },
{ _MMIO(0x9888), 0x145500ab },
{ _MMIO(0x9888), 0x0c5c8000 },
{ _MMIO(0x9888), 0x0e5c4000 },
{ _MMIO(0x9888), 0x025cc000 },
{ _MMIO(0x9888), 0x045cc000 },
{ _MMIO(0x9888), 0x1a3d00a0 },
{ _MMIO(0x9888), 0x0a3d8000 },
{ _MMIO(0x9888), 0x0c588000 },
{ _MMIO(0x9888), 0x0e584000 },
{ _MMIO(0x9888), 0x04588000 },
{ _MMIO(0x9888), 0x1a5b0050 },
{ _MMIO(0x9888), 0x045b8000 },
{ _MMIO(0x9888), 0x065b8000 },
{ _MMIO(0x9888), 0x085b8000 },
{ _MMIO(0x9888), 0x0a5b4000 },
{ _MMIO(0x9888), 0x101f02a0 },
{ _MMIO(0x9888), 0x0c1fa000 },
{ _MMIO(0x9888), 0x0e1f00aa },
{ _MMIO(0x9888), 0x18382500 },
{ _MMIO(0x9888), 0x02388000 },
{ _MMIO(0x9888), 0x04384000 },
{ _MMIO(0x9888), 0x06384000 },
{ _MMIO(0x9888), 0x08384000 },
{ _MMIO(0x9888), 0x0a384000 },
{ _MMIO(0x9888), 0x0c388000 },
{ _MMIO(0x9888), 0x0c398000 },
{ _MMIO(0x9888), 0x0e39a000 },
{ _MMIO(0x9888), 0x00398000 },
{ _MMIO(0x9888), 0x0239a000 },
{ _MMIO(0x9888), 0x0439a000 },
{ _MMIO(0x9888), 0x06392000 },
{ _MMIO(0x9888), 0x1a3a0200 },
{ _MMIO(0x9888), 0x023a8000 },
{ _MMIO(0x9888), 0x0c3a8000 },
{ _MMIO(0x9888), 0x04108000 },
{ _MMIO(0x9888), 0x04118000 },
{ _MMIO(0x9888), 0x04127300 },
{ _MMIO(0x9888), 0x10120000 },
{ _MMIO(0x9888), 0x1813000a },
{ _MMIO(0x9888), 0x0a134000 },
{ _MMIO(0x9888), 0x0a146000 },
{ _MMIO(0x9888), 0x0c159000 },
{ _MMIO(0x9888), 0x0e150098 },
{ _MMIO(0x9888), 0x10150000 },
{ _MMIO(0x9888), 0x04304000 },
{ _MMIO(0x9888), 0x04314000 },
{ _MMIO(0x9888), 0x04320073 },
{ _MMIO(0x9888), 0x10320000 },
{ _MMIO(0x9888), 0x04338000 },
{ _MMIO(0x9888), 0x06338000 },
{ _MMIO(0x9888), 0x08334000 },
{ _MMIO(0x9888), 0x0434c000 },
{ _MMIO(0x9888), 0x02359890 },
{ _MMIO(0x9888), 0x10350000 },
{ _MMIO(0x9888), 0x06504000 },
{ _MMIO(0x9888), 0x06514000 },
{ _MMIO(0x9888), 0x06520073 },
{ _MMIO(0x9888), 0x10520000 },
{ _MMIO(0x9888), 0x18530020 },
{ _MMIO(0x9888), 0x02538000 },
{ _MMIO(0x9888), 0x0c534000 },
{ _MMIO(0x9888), 0x0a548000 },
{ _MMIO(0x9888), 0x04542000 },
{ _MMIO(0x9888), 0x0e559000 },
{ _MMIO(0x9888), 0x00559800 },
{ _MMIO(0x9888), 0x10550000 },
{ _MMIO(0x9888), 0x1b8aa000 },
{ _MMIO(0x9888), 0x1d8a0002 },
{ _MMIO(0x9888), 0x038a8000 },
{ _MMIO(0x9888), 0x058a8000 },
{ _MMIO(0x9888), 0x078a8000 },
{ _MMIO(0x9888), 0x098a8000 },
{ _MMIO(0x9888), 0x0b8a8000 },
{ _MMIO(0x9888), 0x0d8a8000 },
{ _MMIO(0x9888), 0x278b0015 },
{ _MMIO(0x9888), 0x238b2a80 },
{ _MMIO(0x9888), 0x258b0005 },
{ _MMIO(0x9888), 0x2385002a },
{ _MMIO(0x9888), 0x1f85aa00 },
{ _MMIO(0x9888), 0x2185000a },
{ _MMIO(0x9888), 0x1b830150 },
{ _MMIO(0x9888), 0x03834000 },
{ _MMIO(0x9888), 0x05834000 },
{ _MMIO(0x9888), 0x07834000 },
{ _MMIO(0x9888), 0x09834000 },
{ _MMIO(0x9888), 0x0b834000 },
{ _MMIO(0x9888), 0x0d834000 },
{ _MMIO(0x9888), 0x0d848000 },
{ _MMIO(0x9888), 0x0f84c000 },
{ _MMIO(0x9888), 0x01848000 },
{ _MMIO(0x9888), 0x0384c000 },
{ _MMIO(0x9888), 0x0584c000 },
{ _MMIO(0x9888), 0x07844000 },
{ _MMIO(0x9888), 0x1d808000 },
{ _MMIO(0x9888), 0x1f80c000 },
{ _MMIO(0x9888), 0x11808000 },
{ _MMIO(0x9888), 0x1380c000 },
{ _MMIO(0x9888), 0x1580c000 },
{ _MMIO(0x9888), 0x17804000 },
{ _MMIO(0x9888), 0x53800000 },
{ _MMIO(0x9888), 0x47801021 },
{ _MMIO(0x9888), 0x21800000 },
{ _MMIO(0x9888), 0x31800000 },
{ _MMIO(0x9888), 0x4d800000 },
{ _MMIO(0x9888), 0x3f800c64 },
{ _MMIO(0x9888), 0x4f800000 },
{ _MMIO(0x9888), 0x41800c02 },
};
static int
get_sampler_2_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_sampler_2;
lens[n] = ARRAY_SIZE(mux_config_sampler_2);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_tdl_1[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x30800000 },
{ _MMIO(0x2770), 0x00000002 },
{ _MMIO(0x2774), 0x0000fdff },
{ _MMIO(0x2778), 0x00000000 },
{ _MMIO(0x277c), 0x0000fe7f },
{ _MMIO(0x2780), 0x00000002 },
{ _MMIO(0x2784), 0x0000ffbf },
{ _MMIO(0x2788), 0x00000000 },
{ _MMIO(0x278c), 0x0000ffcf },
{ _MMIO(0x2790), 0x00000002 },
{ _MMIO(0x2794), 0x0000fff7 },
{ _MMIO(0x2798), 0x00000000 },
{ _MMIO(0x279c), 0x0000fff9 },
};
static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_tdl_1[] = {
{ _MMIO(0x9888), 0x16154d60 },
{ _MMIO(0x9888), 0x16352e60 },
{ _MMIO(0x9888), 0x16554d60 },
{ _MMIO(0x9888), 0x16950000 },
{ _MMIO(0x9888), 0x16b50000 },
{ _MMIO(0x9888), 0x16d50000 },
{ _MMIO(0x9888), 0x005c8000 },
{ _MMIO(0x9888), 0x045cc000 },
{ _MMIO(0x9888), 0x065c4000 },
{ _MMIO(0x9888), 0x083d8000 },
{ _MMIO(0x9888), 0x0a3d8000 },
{ _MMIO(0x9888), 0x0458c000 },
{ _MMIO(0x9888), 0x025b8000 },
{ _MMIO(0x9888), 0x085b4000 },
{ _MMIO(0x9888), 0x0a5b4000 },
{ _MMIO(0x9888), 0x0c5b8000 },
{ _MMIO(0x9888), 0x0c1fa000 },
{ _MMIO(0x9888), 0x0e1f00aa },
{ _MMIO(0x9888), 0x02384000 },
{ _MMIO(0x9888), 0x04388000 },
{ _MMIO(0x9888), 0x06388000 },
{ _MMIO(0x9888), 0x08384000 },
{ _MMIO(0x9888), 0x0a384000 },
{ _MMIO(0x9888), 0x0c384000 },
{ _MMIO(0x9888), 0x00398000 },
{ _MMIO(0x9888), 0x0239a000 },
{ _MMIO(0x9888), 0x0439a000 },
{ _MMIO(0x9888), 0x06392000 },
{ _MMIO(0x9888), 0x043a8000 },
{ _MMIO(0x9888), 0x063a8000 },
{ _MMIO(0x9888), 0x08138000 },
{ _MMIO(0x9888), 0x0a138000 },
{ _MMIO(0x9888), 0x06143000 },
{ _MMIO(0x9888), 0x0415cfc7 },
{ _MMIO(0x9888), 0x10150000 },
{ _MMIO(0x9888), 0x02338000 },
{ _MMIO(0x9888), 0x0c338000 },
{ _MMIO(0x9888), 0x04342000 },
{ _MMIO(0x9888), 0x06344000 },
{ _MMIO(0x9888), 0x0035c700 },
{ _MMIO(0x9888), 0x063500cf },
{ _MMIO(0x9888), 0x10350000 },
{ _MMIO(0x9888), 0x04538000 },
{ _MMIO(0x9888), 0x06538000 },
{ _MMIO(0x9888), 0x0454c000 },
{ _MMIO(0x9888), 0x0255cfc7 },
{ _MMIO(0x9888), 0x10550000 },
{ _MMIO(0x9888), 0x06dc8000 },
{ _MMIO(0x9888), 0x08dc4000 },
{ _MMIO(0x9888), 0x0cdcc000 },
{ _MMIO(0x9888), 0x0edcc000 },
{ _MMIO(0x9888), 0x1abd00a8 },
{ _MMIO(0x9888), 0x0cd8c000 },
{ _MMIO(0x9888), 0x0ed84000 },
{ _MMIO(0x9888), 0x0edb8000 },
{ _MMIO(0x9888), 0x18db0800 },
{ _MMIO(0x9888), 0x1adb0254 },
{ _MMIO(0x9888), 0x0e9faa00 },
{ _MMIO(0x9888), 0x109f02aa },
{ _MMIO(0x9888), 0x0eb84000 },
{ _MMIO(0x9888), 0x16b84000 },
{ _MMIO(0x9888), 0x18b8156a },
{ _MMIO(0x9888), 0x06b98000 },
{ _MMIO(0x9888), 0x08b9a000 },
{ _MMIO(0x9888), 0x0ab9a000 },
{ _MMIO(0x9888), 0x0cb9a000 },
{ _MMIO(0x9888), 0x0eb9a000 },
{ _MMIO(0x9888), 0x18baa000 },
{ _MMIO(0x9888), 0x1aba0002 },
{ _MMIO(0x9888), 0x16934000 },
{ _MMIO(0x9888), 0x1893000a },
{ _MMIO(0x9888), 0x0a947000 },
{ _MMIO(0x9888), 0x0c95c5c1 },
{ _MMIO(0x9888), 0x0e9500c3 },
{ _MMIO(0x9888), 0x10950000 },
{ _MMIO(0x9888), 0x0eb38000 },
{ _MMIO(0x9888), 0x16b30040 },
{ _MMIO(0x9888), 0x18b30020 },
{ _MMIO(0x9888), 0x06b48000 },
{ _MMIO(0x9888), 0x08b41000 },
{ _MMIO(0x9888), 0x0ab48000 },
{ _MMIO(0x9888), 0x06b5c500 },
{ _MMIO(0x9888), 0x08b500c3 },
{ _MMIO(0x9888), 0x0eb5c100 },
{ _MMIO(0x9888), 0x10b50000 },
{ _MMIO(0x9888), 0x16d31500 },
{ _MMIO(0x9888), 0x08d4e000 },
{ _MMIO(0x9888), 0x08d5c100 },
{ _MMIO(0x9888), 0x0ad5c3c5 },
{ _MMIO(0x9888), 0x10d50000 },
{ _MMIO(0x9888), 0x0d88f800 },
{ _MMIO(0x9888), 0x0f88000f },
{ _MMIO(0x9888), 0x038a8000 },
{ _MMIO(0x9888), 0x058a8000 },
{ _MMIO(0x9888), 0x078a8000 },
{ _MMIO(0x9888), 0x098a8000 },
{ _MMIO(0x9888), 0x0b8a8000 },
{ _MMIO(0x9888), 0x0d8a8000 },
{ _MMIO(0x9888), 0x258baaa5 },
{ _MMIO(0x9888), 0x278b002a },
{ _MMIO(0x9888), 0x238b2a80 },
{ _MMIO(0x9888), 0x0f8c4000 },
{ _MMIO(0x9888), 0x178c2000 },
{ _MMIO(0x9888), 0x198c5500 },
{ _MMIO(0x9888), 0x1b8c0015 },
{ _MMIO(0x9888), 0x078d8000 },
{ _MMIO(0x9888), 0x098da000 },
{ _MMIO(0x9888), 0x0b8da000 },
{ _MMIO(0x9888), 0x0d8da000 },
{ _MMIO(0x9888), 0x0f8da000 },
{ _MMIO(0x9888), 0x2185aaaa },
{ _MMIO(0x9888), 0x2385002a },
{ _MMIO(0x9888), 0x1f85aa00 },
{ _MMIO(0x9888), 0x0f834000 },
{ _MMIO(0x9888), 0x19835400 },
{ _MMIO(0x9888), 0x1b830155 },
{ _MMIO(0x9888), 0x03834000 },
{ _MMIO(0x9888), 0x05834000 },
{ _MMIO(0x9888), 0x07834000 },
{ _MMIO(0x9888), 0x09834000 },
{ _MMIO(0x9888), 0x0b834000 },
{ _MMIO(0x9888), 0x0d834000 },
{ _MMIO(0x9888), 0x0784c000 },
{ _MMIO(0x9888), 0x0984c000 },
{ _MMIO(0x9888), 0x0b84c000 },
{ _MMIO(0x9888), 0x0d84c000 },
{ _MMIO(0x9888), 0x0f84c000 },
{ _MMIO(0x9888), 0x01848000 },
{ _MMIO(0x9888), 0x0384c000 },
{ _MMIO(0x9888), 0x0584c000 },
{ _MMIO(0x9888), 0x1780c000 },
{ _MMIO(0x9888), 0x1980c000 },
{ _MMIO(0x9888), 0x1b80c000 },
{ _MMIO(0x9888), 0x1d80c000 },
{ _MMIO(0x9888), 0x1f80c000 },
{ _MMIO(0x9888), 0x11808000 },
{ _MMIO(0x9888), 0x1380c000 },
{ _MMIO(0x9888), 0x1580c000 },
{ _MMIO(0x9888), 0x4f800000 },
{ _MMIO(0x9888), 0x43800c42 },
{ _MMIO(0x9888), 0x51800000 },
{ _MMIO(0x9888), 0x45800063 },
{ _MMIO(0x9888), 0x53800000 },
{ _MMIO(0x9888), 0x47800800 },
{ _MMIO(0x9888), 0x21800000 },
{ _MMIO(0x9888), 0x31800000 },
{ _MMIO(0x9888), 0x4d800000 },
{ _MMIO(0x9888), 0x3f8014a4 },
{ _MMIO(0x9888), 0x41801042 },
};
static int
get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_tdl_1;
lens[n] = ARRAY_SIZE(mux_config_tdl_1);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_tdl_2[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x30800000 },
{ _MMIO(0x2770), 0x00000002 },
{ _MMIO(0x2774), 0x0000fdff },
{ _MMIO(0x2778), 0x00000000 },
{ _MMIO(0x277c), 0x0000fe7f },
{ _MMIO(0x2780), 0x00000000 },
{ _MMIO(0x2784), 0x0000ff9f },
{ _MMIO(0x2788), 0x00000000 },
{ _MMIO(0x278c), 0x0000ffe7 },
{ _MMIO(0x2790), 0x00000002 },
{ _MMIO(0x2794), 0x0000fffb },
{ _MMIO(0x2798), 0x00000002 },
{ _MMIO(0x279c), 0x0000fffd },
};
static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_tdl_2[] = {
{ _MMIO(0x9888), 0x16150000 },
{ _MMIO(0x9888), 0x16350000 },
{ _MMIO(0x9888), 0x16550000 },
{ _MMIO(0x9888), 0x16952e60 },
{ _MMIO(0x9888), 0x16b54d60 },
{ _MMIO(0x9888), 0x16d52e60 },
{ _MMIO(0x9888), 0x065c8000 },
{ _MMIO(0x9888), 0x085cc000 },
{ _MMIO(0x9888), 0x0a5cc000 },
{ _MMIO(0x9888), 0x0c5c4000 },
{ _MMIO(0x9888), 0x0e3d8000 },
{ _MMIO(0x9888), 0x183da000 },
{ _MMIO(0x9888), 0x06588000 },
{ _MMIO(0x9888), 0x08588000 },
{ _MMIO(0x9888), 0x0a584000 },
{ _MMIO(0x9888), 0x0e5b4000 },
{ _MMIO(0x9888), 0x185b5800 },
{ _MMIO(0x9888), 0x1a5b000a },
{ _MMIO(0x9888), 0x0e1faa00 },
{ _MMIO(0x9888), 0x101f02aa },
{ _MMIO(0x9888), 0x0e384000 },
{ _MMIO(0x9888), 0x16384000 },
{ _MMIO(0x9888), 0x18382a55 },
{ _MMIO(0x9888), 0x06398000 },
{ _MMIO(0x9888), 0x0839a000 },
{ _MMIO(0x9888), 0x0a39a000 },
{ _MMIO(0x9888), 0x0c39a000 },
{ _MMIO(0x9888), 0x0e39a000 },
{ _MMIO(0x9888), 0x1a3a02a0 },
{ _MMIO(0x9888), 0x0e138000 },
{ _MMIO(0x9888), 0x16130500 },
{ _MMIO(0x9888), 0x06148000 },
{ _MMIO(0x9888), 0x08146000 },
{ _MMIO(0x9888), 0x0615c100 },
{ _MMIO(0x9888), 0x0815c500 },
{ _MMIO(0x9888), 0x0a1500c3 },
{ _MMIO(0x9888), 0x10150000 },
{ _MMIO(0x9888), 0x16335040 },
{ _MMIO(0x9888), 0x08349000 },
{ _MMIO(0x9888), 0x0a341000 },
{ _MMIO(0x9888), 0x083500c1 },
{ _MMIO(0x9888), 0x0a35c500 },
{ _MMIO(0x9888), 0x0c3500c3 },
{ _MMIO(0x9888), 0x10350000 },
{ _MMIO(0x9888), 0x1853002a },
{ _MMIO(0x9888), 0x0a54e000 },
{ _MMIO(0x9888), 0x0c55c500 },
{ _MMIO(0x9888), 0x0e55c1c3 },
{ _MMIO(0x9888), 0x10550000 },
{ _MMIO(0x9888), 0x00dc8000 },
{ _MMIO(0x9888), 0x02dcc000 },
{ _MMIO(0x9888), 0x04dc4000 },
{ _MMIO(0x9888), 0x04bd8000 },
{ _MMIO(0x9888), 0x06bd8000 },
{ _MMIO(0x9888), 0x02d8c000 },
{ _MMIO(0x9888), 0x02db8000 },
{ _MMIO(0x9888), 0x04db4000 },
{ _MMIO(0x9888), 0x06db4000 },
{ _MMIO(0x9888), 0x08db8000 },
{ _MMIO(0x9888), 0x0c9fa000 },
{ _MMIO(0x9888), 0x0e9f00aa },
{ _MMIO(0x9888), 0x02b84000 },
{ _MMIO(0x9888), 0x04b84000 },
{ _MMIO(0x9888), 0x06b84000 },
{ _MMIO(0x9888), 0x08b84000 },
{ _MMIO(0x9888), 0x0ab88000 },
{ _MMIO(0x9888), 0x0cb88000 },
{ _MMIO(0x9888), 0x00b98000 },
{ _MMIO(0x9888), 0x02b9a000 },
{ _MMIO(0x9888), 0x04b9a000 },
{ _MMIO(0x9888), 0x06b92000 },
{ _MMIO(0x9888), 0x0aba8000 },
{ _MMIO(0x9888), 0x0cba8000 },
{ _MMIO(0x9888), 0x04938000 },
{ _MMIO(0x9888), 0x06938000 },
{ _MMIO(0x9888), 0x0494c000 },
{ _MMIO(0x9888), 0x0295cfc7 },
{ _MMIO(0x9888), 0x10950000 },
{ _MMIO(0x9888), 0x02b38000 },
{ _MMIO(0x9888), 0x08b38000 },
{ _MMIO(0x9888), 0x04b42000 },
{ _MMIO(0x9888), 0x06b41000 },
{ _MMIO(0x9888), 0x00b5c700 },
{ _MMIO(0x9888), 0x04b500cf },
{ _MMIO(0x9888), 0x10b50000 },
{ _MMIO(0x9888), 0x0ad38000 },
{ _MMIO(0x9888), 0x0cd38000 },
{ _MMIO(0x9888), 0x06d46000 },
{ _MMIO(0x9888), 0x04d5c700 },
{ _MMIO(0x9888), 0x06d500cf },
{ _MMIO(0x9888), 0x10d50000 },
{ _MMIO(0x9888), 0x03888000 },
{ _MMIO(0x9888), 0x05888000 },
{ _MMIO(0x9888), 0x07888000 },
{ _MMIO(0x9888), 0x09888000 },
{ _MMIO(0x9888), 0x0b888000 },
{ _MMIO(0x9888), 0x0d880400 },
{ _MMIO(0x9888), 0x0f8a8000 },
{ _MMIO(0x9888), 0x198a8000 },
{ _MMIO(0x9888), 0x1b8aaaa0 },
{ _MMIO(0x9888), 0x1d8a0002 },
{ _MMIO(0x9888), 0x258b555a },
{ _MMIO(0x9888), 0x278b0015 },
{ _MMIO(0x9888), 0x238b5500 },
{ _MMIO(0x9888), 0x038c4000 },
{ _MMIO(0x9888), 0x058c4000 },
{ _MMIO(0x9888), 0x078c4000 },
{ _MMIO(0x9888), 0x098c4000 },
{ _MMIO(0x9888), 0x0b8c4000 },
{ _MMIO(0x9888), 0x0d8c4000 },
{ _MMIO(0x9888), 0x018d8000 },
{ _MMIO(0x9888), 0x038da000 },
{ _MMIO(0x9888), 0x058da000 },
{ _MMIO(0x9888), 0x078d2000 },
{ _MMIO(0x9888), 0x2185aaaa },
{ _MMIO(0x9888), 0x2385002a },
{ _MMIO(0x9888), 0x1f85aa00 },
{ _MMIO(0x9888), 0x0f834000 },
{ _MMIO(0x9888), 0x19835400 },
{ _MMIO(0x9888), 0x1b830155 },
{ _MMIO(0x9888), 0x03834000 },
{ _MMIO(0x9888), 0x05834000 },
{ _MMIO(0x9888), 0x07834000 },
{ _MMIO(0x9888), 0x09834000 },
{ _MMIO(0x9888), 0x0b834000 },
{ _MMIO(0x9888), 0x0d834000 },
{ _MMIO(0x9888), 0x0784c000 },
{ _MMIO(0x9888), 0x0984c000 },
{ _MMIO(0x9888), 0x0b84c000 },
{ _MMIO(0x9888), 0x0d84c000 },
{ _MMIO(0x9888), 0x0f84c000 },
{ _MMIO(0x9888), 0x01848000 },
{ _MMIO(0x9888), 0x0384c000 },
{ _MMIO(0x9888), 0x0584c000 },
{ _MMIO(0x9888), 0x1780c000 },
{ _MMIO(0x9888), 0x1980c000 },
{ _MMIO(0x9888), 0x1b80c000 },
{ _MMIO(0x9888), 0x1d80c000 },
{ _MMIO(0x9888), 0x1f80c000 },
{ _MMIO(0x9888), 0x11808000 },
{ _MMIO(0x9888), 0x1380c000 },
{ _MMIO(0x9888), 0x1580c000 },
{ _MMIO(0x9888), 0x4f800000 },
{ _MMIO(0x9888), 0x43800882 },
{ _MMIO(0x9888), 0x51800000 },
{ _MMIO(0x9888), 0x45801082 },
{ _MMIO(0x9888), 0x53800000 },
{ _MMIO(0x9888), 0x478014a5 },
{ _MMIO(0x9888), 0x21800000 },
{ _MMIO(0x9888), 0x31800000 },
{ _MMIO(0x9888), 0x4d800000 },
{ _MMIO(0x9888), 0x3f800002 },
{ _MMIO(0x9888), 0x41800c62 },
};
static int
get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_tdl_2;
lens[n] = ARRAY_SIZE(mux_config_tdl_2);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_test_oa[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2770), 0x00000004 },
{ _MMIO(0x2774), 0x00000000 },
{ _MMIO(0x2778), 0x00000003 },
{ _MMIO(0x277c), 0x00000000 },
{ _MMIO(0x2780), 0x00000007 },
{ _MMIO(0x2784), 0x00000000 },
{ _MMIO(0x2788), 0x00100002 },
{ _MMIO(0x278c), 0x0000fff7 },
{ _MMIO(0x2790), 0x00100002 },
{ _MMIO(0x2794), 0x0000ffcf },
{ _MMIO(0x2798), 0x00100082 },
{ _MMIO(0x279c), 0x0000ffef },
{ _MMIO(0x27a0), 0x001000c2 },
{ _MMIO(0x27a4), 0x0000ffe7 },
{ _MMIO(0x27a8), 0x00100001 },
{ _MMIO(0x27ac), 0x0000ffe7 },
};
static const struct i915_oa_reg flex_eu_config_test_oa[] = {
};
static const struct i915_oa_reg mux_config_test_oa[] = {
{ _MMIO(0x9888), 0x59800000 },
{ _MMIO(0x9888), 0x59800001 },
{ _MMIO(0x9888), 0x338b0000 },
{ _MMIO(0x9888), 0x258b0066 },
{ _MMIO(0x9888), 0x058b0000 },
{ _MMIO(0x9888), 0x038b0000 },
{ _MMIO(0x9888), 0x03844000 },
{ _MMIO(0x9888), 0x47800080 },
{ _MMIO(0x9888), 0x57800000 },
{ _MMIO(0x1823a4), 0x00000000 },
{ _MMIO(0x9888), 0x59800000 },
};
static int
get_test_oa_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_test_oa;
lens[n] = ARRAY_SIZE(mux_config_test_oa);
n++;
return n;
}
int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv) int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv)
{ {
dev_priv->perf.oa.n_mux_configs = 0; dev_priv->perf.oa.n_mux_configs = 0;
...@@ -154,14 +2035,300 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv) ...@@ -154,14 +2035,300 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.flex_regs = NULL; dev_priv->perf.oa.flex_regs = NULL;
dev_priv->perf.oa.flex_regs_len = 0; dev_priv->perf.oa.flex_regs_len = 0;
switch (dev_priv->perf.oa.metrics_set) { switch (dev_priv->perf.oa.metrics_set) {
case METRIC_SET_ID_RENDER_BASIC: case METRIC_SET_ID_RENDER_BASIC:
dev_priv->perf.oa.n_mux_configs =
get_render_basic_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_render_basic;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_render_basic);
dev_priv->perf.oa.flex_regs =
flex_eu_config_render_basic;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_render_basic);
return 0;
case METRIC_SET_ID_COMPUTE_BASIC:
dev_priv->perf.oa.n_mux_configs =
get_compute_basic_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_compute_basic;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_basic);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_basic;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_basic);
return 0;
case METRIC_SET_ID_RENDER_PIPE_PROFILE:
dev_priv->perf.oa.n_mux_configs =
get_render_pipe_profile_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_render_pipe_profile;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_render_pipe_profile);
dev_priv->perf.oa.flex_regs =
flex_eu_config_render_pipe_profile;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_render_pipe_profile);
return 0;
case METRIC_SET_ID_HDC_AND_SF:
dev_priv->perf.oa.n_mux_configs =
get_hdc_and_sf_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_hdc_and_sf;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_hdc_and_sf);
dev_priv->perf.oa.flex_regs =
flex_eu_config_hdc_and_sf;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_hdc_and_sf);
return 0;
case METRIC_SET_ID_L3_1:
dev_priv->perf.oa.n_mux_configs =
get_l3_1_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_l3_1;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_l3_1);
dev_priv->perf.oa.flex_regs =
flex_eu_config_l3_1;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_l3_1);
return 0;
case METRIC_SET_ID_L3_2:
dev_priv->perf.oa.n_mux_configs =
get_l3_2_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_l3_2;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_l3_2);
dev_priv->perf.oa.flex_regs =
flex_eu_config_l3_2;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_l3_2);
return 0;
case METRIC_SET_ID_L3_3:
dev_priv->perf.oa.n_mux_configs =
get_l3_3_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_l3_3;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_l3_3);
dev_priv->perf.oa.flex_regs =
flex_eu_config_l3_3;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_l3_3);
return 0;
case METRIC_SET_ID_L3_4:
dev_priv->perf.oa.n_mux_configs =
get_l3_4_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_4\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_l3_4;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_l3_4);
dev_priv->perf.oa.flex_regs =
flex_eu_config_l3_4;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_l3_4);
return 0;
case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
dev_priv->perf.oa.n_mux_configs =
get_rasterizer_and_pixel_backend_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_rasterizer_and_pixel_backend;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
dev_priv->perf.oa.flex_regs =
flex_eu_config_rasterizer_and_pixel_backend;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
return 0;
case METRIC_SET_ID_SAMPLER_1:
dev_priv->perf.oa.n_mux_configs =
get_sampler_1_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_1\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_sampler_1;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_sampler_1);
dev_priv->perf.oa.flex_regs =
flex_eu_config_sampler_1;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_sampler_1);
return 0;
case METRIC_SET_ID_SAMPLER_2:
dev_priv->perf.oa.n_mux_configs =
get_sampler_2_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_2\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_sampler_2;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_sampler_2);
dev_priv->perf.oa.flex_regs =
flex_eu_config_sampler_2;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_sampler_2);
return 0;
case METRIC_SET_ID_TDL_1:
dev_priv->perf.oa.n_mux_configs = dev_priv->perf.oa.n_mux_configs =
get_render_basic_mux_config(dev_priv, get_tdl_1_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs, dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens); dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) { if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
/* EINVAL because *_register_sysfs already checked this /* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and * and so it wouldn't have been advertised to userspace and
...@@ -171,14 +2338,66 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv) ...@@ -171,14 +2338,66 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv)
} }
dev_priv->perf.oa.b_counter_regs = dev_priv->perf.oa.b_counter_regs =
b_counter_config_render_basic; b_counter_config_tdl_1;
dev_priv->perf.oa.b_counter_regs_len = dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_render_basic); ARRAY_SIZE(b_counter_config_tdl_1);
dev_priv->perf.oa.flex_regs = dev_priv->perf.oa.flex_regs =
flex_eu_config_render_basic; flex_eu_config_tdl_1;
dev_priv->perf.oa.flex_regs_len = dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_render_basic); ARRAY_SIZE(flex_eu_config_tdl_1);
return 0;
case METRIC_SET_ID_TDL_2:
dev_priv->perf.oa.n_mux_configs =
get_tdl_2_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_tdl_2;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_tdl_2);
dev_priv->perf.oa.flex_regs =
flex_eu_config_tdl_2;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_tdl_2);
return 0;
case METRIC_SET_ID_TEST_OA:
dev_priv->perf.oa.n_mux_configs =
get_test_oa_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_test_oa;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_test_oa);
dev_priv->perf.oa.flex_regs =
flex_eu_config_test_oa;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_test_oa);
return 0; return 0;
default: default:
...@@ -208,6 +2427,292 @@ static struct attribute_group group_render_basic = { ...@@ -208,6 +2427,292 @@ static struct attribute_group group_render_basic = {
.attrs = attrs_render_basic, .attrs = attrs_render_basic,
}; };
static ssize_t
show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
}
static struct device_attribute dev_attr_compute_basic_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_basic_id,
.store = NULL,
};
static struct attribute *attrs_compute_basic[] = {
&dev_attr_compute_basic_id.attr,
NULL,
};
static struct attribute_group group_compute_basic = {
.name = "f522a89c-ecd1-4522-8331-3383c54af5f5",
.attrs = attrs_compute_basic,
};
static ssize_t
show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
}
static struct device_attribute dev_attr_render_pipe_profile_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_render_pipe_profile_id,
.store = NULL,
};
static struct attribute *attrs_render_pipe_profile[] = {
&dev_attr_render_pipe_profile_id.attr,
NULL,
};
static struct attribute_group group_render_pipe_profile = {
.name = "a9ccc03d-a943-4e6b-9cd6-13e063075927",
.attrs = attrs_render_pipe_profile,
};
static ssize_t
show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
}
static struct device_attribute dev_attr_hdc_and_sf_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_hdc_and_sf_id,
.store = NULL,
};
static struct attribute *attrs_hdc_and_sf[] = {
&dev_attr_hdc_and_sf_id.attr,
NULL,
};
static struct attribute_group group_hdc_and_sf = {
.name = "2cf0c064-68df-4fac-9b3f-57f51ca8a069",
.attrs = attrs_hdc_and_sf,
};
static ssize_t
show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
}
static struct device_attribute dev_attr_l3_1_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_l3_1_id,
.store = NULL,
};
static struct attribute *attrs_l3_1[] = {
&dev_attr_l3_1_id.attr,
NULL,
};
static struct attribute_group group_l3_1 = {
.name = "78a87ff9-543a-49ce-95ea-26d86071ea93",
.attrs = attrs_l3_1,
};
static ssize_t
show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
}
static struct device_attribute dev_attr_l3_2_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_l3_2_id,
.store = NULL,
};
static struct attribute *attrs_l3_2[] = {
&dev_attr_l3_2_id.attr,
NULL,
};
static struct attribute_group group_l3_2 = {
.name = "9f2cece5-7bfe-4320-ad66-8c7cc526bec5",
.attrs = attrs_l3_2,
};
static ssize_t
show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
}
static struct device_attribute dev_attr_l3_3_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_l3_3_id,
.store = NULL,
};
static struct attribute *attrs_l3_3[] = {
&dev_attr_l3_3_id.attr,
NULL,
};
static struct attribute_group group_l3_3 = {
.name = "d890ef38-d309-47e4-b8b5-aa779bb19ab0",
.attrs = attrs_l3_3,
};
static ssize_t
show_l3_4_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_L3_4);
}
static struct device_attribute dev_attr_l3_4_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_l3_4_id,
.store = NULL,
};
static struct attribute *attrs_l3_4[] = {
&dev_attr_l3_4_id.attr,
NULL,
};
static struct attribute_group group_l3_4 = {
.name = "5fdff4a6-9dc8-45e1-bfda-ef54869fbdd4",
.attrs = attrs_l3_4,
};
static ssize_t
show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
}
static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_rasterizer_and_pixel_backend_id,
.store = NULL,
};
static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
&dev_attr_rasterizer_and_pixel_backend_id.attr,
NULL,
};
static struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "2c0e45e1-7e2c-4a14-ae00-0b7ec868b8aa",
.attrs = attrs_rasterizer_and_pixel_backend,
};
static ssize_t
show_sampler_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_1);
}
static struct device_attribute dev_attr_sampler_1_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_sampler_1_id,
.store = NULL,
};
static struct attribute *attrs_sampler_1[] = {
&dev_attr_sampler_1_id.attr,
NULL,
};
static struct attribute_group group_sampler_1 = {
.name = "71148d78-baf5-474f-878a-e23158d0265d",
.attrs = attrs_sampler_1,
};
static ssize_t
show_sampler_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_2);
}
static struct device_attribute dev_attr_sampler_2_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_sampler_2_id,
.store = NULL,
};
static struct attribute *attrs_sampler_2[] = {
&dev_attr_sampler_2_id.attr,
NULL,
};
static struct attribute_group group_sampler_2 = {
.name = "b996a2b7-c59c-492d-877a-8cd54fd6df84",
.attrs = attrs_sampler_2,
};
static ssize_t
show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
}
static struct device_attribute dev_attr_tdl_1_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_tdl_1_id,
.store = NULL,
};
static struct attribute *attrs_tdl_1[] = {
&dev_attr_tdl_1_id.attr,
NULL,
};
static struct attribute_group group_tdl_1 = {
.name = "eb2fecba-b431-42e7-8261-fe9429a6e67a",
.attrs = attrs_tdl_1,
};
static ssize_t
show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
}
static struct device_attribute dev_attr_tdl_2_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_tdl_2_id,
.store = NULL,
};
static struct attribute *attrs_tdl_2[] = {
&dev_attr_tdl_2_id.attr,
NULL,
};
static struct attribute_group group_tdl_2 = {
.name = "60749470-a648-4a4b-9f10-dbfe1e36e44d",
.attrs = attrs_tdl_2,
};
static ssize_t
show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
}
static struct device_attribute dev_attr_test_oa_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_test_oa_id,
.store = NULL,
};
static struct attribute *attrs_test_oa[] = {
&dev_attr_test_oa_id.attr,
NULL,
};
static struct attribute_group group_test_oa = {
.name = "4a534b07-cba3-414d-8d60-874830e883aa",
.attrs = attrs_test_oa,
};
int int
i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv) i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv)
{ {
...@@ -220,9 +2725,113 @@ i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv) ...@@ -220,9 +2725,113 @@ i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv)
if (ret) if (ret)
goto error_render_basic; goto error_render_basic;
} }
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
if (ret)
goto error_compute_basic;
}
if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
if (ret)
goto error_render_pipe_profile;
}
if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
if (ret)
goto error_hdc_and_sf;
}
if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
if (ret)
goto error_l3_1;
}
if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
if (ret)
goto error_l3_2;
}
if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
if (ret)
goto error_l3_3;
}
if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_4);
if (ret)
goto error_l3_4;
}
if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
if (ret)
goto error_rasterizer_and_pixel_backend;
}
if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
if (ret)
goto error_sampler_1;
}
if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
if (ret)
goto error_sampler_2;
}
if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
if (ret)
goto error_tdl_1;
}
if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
if (ret)
goto error_tdl_2;
}
if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
if (ret)
goto error_test_oa;
}
return 0; return 0;
error_test_oa:
if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
error_tdl_2:
if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
error_tdl_1:
if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
error_sampler_2:
if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
error_sampler_1:
if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
error_rasterizer_and_pixel_backend:
if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4);
error_l3_4:
if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
error_l3_3:
if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
error_l3_2:
if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
error_l3_1:
if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
error_hdc_and_sf:
if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
error_render_pipe_profile:
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
error_compute_basic:
if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
error_render_basic: error_render_basic:
return ret; return ret;
} }
...@@ -235,4 +2844,30 @@ i915_perf_unregister_sysfs_chv(struct drm_i915_private *dev_priv) ...@@ -235,4 +2844,30 @@ i915_perf_unregister_sysfs_chv(struct drm_i915_private *dev_priv)
if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4);
if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1);
if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2);
if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
} }
drivers/gpu/drm/i915/i915_oa_hsw.c
View file @ fc599211
...@@ -49,6 +49,9 @@ static const struct i915_oa_reg b_counter_config_render_basic[] = { ...@@ -49,6 +49,9 @@ static const struct i915_oa_reg b_counter_config_render_basic[] = {
{ _MMIO(0x2710), 0x00000000 }, { _MMIO(0x2710), 0x00000000 },
}; };
static const struct i915_oa_reg flex_eu_config_render_basic[] = {
};
static const struct i915_oa_reg mux_config_render_basic[] = { static const struct i915_oa_reg mux_config_render_basic[] = {
{ _MMIO(0x253a4), 0x01600000 }, { _MMIO(0x253a4), 0x01600000 },
{ _MMIO(0x25440), 0x00100000 }, { _MMIO(0x25440), 0x00100000 },
...@@ -148,6 +151,9 @@ static const struct i915_oa_reg b_counter_config_compute_basic[] = { ...@@ -148,6 +151,9 @@ static const struct i915_oa_reg b_counter_config_compute_basic[] = {
{ _MMIO(0x236c), 0x00000000 }, { _MMIO(0x236c), 0x00000000 },
}; };
static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
};
static const struct i915_oa_reg mux_config_compute_basic[] = { static const struct i915_oa_reg mux_config_compute_basic[] = {
{ _MMIO(0x253a4), 0x00000000 }, { _MMIO(0x253a4), 0x00000000 },
{ _MMIO(0x2681c), 0x01f00800 }, { _MMIO(0x2681c), 0x01f00800 },
...@@ -223,6 +229,9 @@ static const struct i915_oa_reg b_counter_config_compute_extended[] = { ...@@ -223,6 +229,9 @@ static const struct i915_oa_reg b_counter_config_compute_extended[] = {
{ _MMIO(0x27ac), 0x0000fffe }, { _MMIO(0x27ac), 0x0000fffe },
}; };
static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
};
static const struct i915_oa_reg mux_config_compute_extended[] = { static const struct i915_oa_reg mux_config_compute_extended[] = {
{ _MMIO(0x2681c), 0x3eb00800 }, { _MMIO(0x2681c), 0x3eb00800 },
{ _MMIO(0x26820), 0x00900000 }, { _MMIO(0x26820), 0x00900000 },
...@@ -289,6 +298,9 @@ static const struct i915_oa_reg b_counter_config_memory_reads[] = { ...@@ -289,6 +298,9 @@ static const struct i915_oa_reg b_counter_config_memory_reads[] = {
{ _MMIO(0x27ac), 0x0000fc00 }, { _MMIO(0x27ac), 0x0000fc00 },
}; };
static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
};
static const struct i915_oa_reg mux_config_memory_reads[] = { static const struct i915_oa_reg mux_config_memory_reads[] = {
{ _MMIO(0x253a4), 0x34300000 }, { _MMIO(0x253a4), 0x34300000 },
{ _MMIO(0x25440), 0x2d800000 }, { _MMIO(0x25440), 0x2d800000 },
...@@ -358,6 +370,9 @@ static const struct i915_oa_reg b_counter_config_memory_writes[] = { ...@@ -358,6 +370,9 @@ static const struct i915_oa_reg b_counter_config_memory_writes[] = {
{ _MMIO(0x27ac), 0x0000fc00 }, { _MMIO(0x27ac), 0x0000fc00 },
}; };
static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
};
static const struct i915_oa_reg mux_config_memory_writes[] = { static const struct i915_oa_reg mux_config_memory_writes[] = {
{ _MMIO(0x253a4), 0x34300000 }, { _MMIO(0x253a4), 0x34300000 },
{ _MMIO(0x25440), 0x01500000 }, { _MMIO(0x25440), 0x01500000 },
...@@ -405,6 +420,9 @@ static const struct i915_oa_reg b_counter_config_sampler_balance[] = { ...@@ -405,6 +420,9 @@ static const struct i915_oa_reg b_counter_config_sampler_balance[] = {
{ _MMIO(0x2724), 0x00800000 }, { _MMIO(0x2724), 0x00800000 },
}; };
static const struct i915_oa_reg flex_eu_config_sampler_balance[] = {
};
static const struct i915_oa_reg mux_config_sampler_balance[] = { static const struct i915_oa_reg mux_config_sampler_balance[] = {
{ _MMIO(0x2eb9c), 0x01906400 }, { _MMIO(0x2eb9c), 0x01906400 },
{ _MMIO(0x2fb9c), 0x01906400 }, { _MMIO(0x2fb9c), 0x01906400 },
...@@ -492,6 +510,11 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv) ...@@ -492,6 +510,11 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.b_counter_regs_len = dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_render_basic); ARRAY_SIZE(b_counter_config_render_basic);
dev_priv->perf.oa.flex_regs =
flex_eu_config_render_basic;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_render_basic);
return 0; return 0;
case METRIC_SET_ID_COMPUTE_BASIC: case METRIC_SET_ID_COMPUTE_BASIC:
dev_priv->perf.oa.n_mux_configs = dev_priv->perf.oa.n_mux_configs =
...@@ -513,6 +536,11 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv) ...@@ -513,6 +536,11 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.b_counter_regs_len = dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_basic); ARRAY_SIZE(b_counter_config_compute_basic);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_basic;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_basic);
return 0; return 0;
case METRIC_SET_ID_COMPUTE_EXTENDED: case METRIC_SET_ID_COMPUTE_EXTENDED:
dev_priv->perf.oa.n_mux_configs = dev_priv->perf.oa.n_mux_configs =
...@@ -534,6 +562,11 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv) ...@@ -534,6 +562,11 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.b_counter_regs_len = dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_extended); ARRAY_SIZE(b_counter_config_compute_extended);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_extended;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_extended);
return 0; return 0;
case METRIC_SET_ID_MEMORY_READS: case METRIC_SET_ID_MEMORY_READS:
dev_priv->perf.oa.n_mux_configs = dev_priv->perf.oa.n_mux_configs =
...@@ -555,6 +588,11 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv) ...@@ -555,6 +588,11 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.b_counter_regs_len = dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_memory_reads); ARRAY_SIZE(b_counter_config_memory_reads);
dev_priv->perf.oa.flex_regs =
flex_eu_config_memory_reads;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_memory_reads);
return 0; return 0;
case METRIC_SET_ID_MEMORY_WRITES: case METRIC_SET_ID_MEMORY_WRITES:
dev_priv->perf.oa.n_mux_configs = dev_priv->perf.oa.n_mux_configs =
...@@ -576,6 +614,11 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv) ...@@ -576,6 +614,11 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.b_counter_regs_len = dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_memory_writes); ARRAY_SIZE(b_counter_config_memory_writes);
dev_priv->perf.oa.flex_regs =
flex_eu_config_memory_writes;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_memory_writes);
return 0; return 0;
case METRIC_SET_ID_SAMPLER_BALANCE: case METRIC_SET_ID_SAMPLER_BALANCE:
dev_priv->perf.oa.n_mux_configs = dev_priv->perf.oa.n_mux_configs =
...@@ -597,6 +640,11 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv) ...@@ -597,6 +640,11 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.b_counter_regs_len = dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_sampler_balance); ARRAY_SIZE(b_counter_config_sampler_balance);
dev_priv->perf.oa.flex_regs =
flex_eu_config_sampler_balance;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_sampler_balance);
return 0; return 0;
default: default:
return -ENODEV; return -ENODEV;
......
drivers/gpu/drm/i915/i915_oa_sklgt2.c
View file @ fc599211
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/gpu/drm/i915/i915_oa_sklgt3.c
View file @ fc599211
...@@ -33,9 +33,26 @@ ...@@ -33,9 +33,26 @@
enum metric_set_id { enum metric_set_id {
METRIC_SET_ID_RENDER_BASIC = 1, METRIC_SET_ID_RENDER_BASIC = 1,
METRIC_SET_ID_COMPUTE_BASIC,
METRIC_SET_ID_RENDER_PIPE_PROFILE,
METRIC_SET_ID_MEMORY_READS,
METRIC_SET_ID_MEMORY_WRITES,
METRIC_SET_ID_COMPUTE_EXTENDED,
METRIC_SET_ID_COMPUTE_L3_CACHE,
METRIC_SET_ID_HDC_AND_SF,
METRIC_SET_ID_L3_1,
METRIC_SET_ID_L3_2,
METRIC_SET_ID_L3_3,
METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
METRIC_SET_ID_SAMPLER,
METRIC_SET_ID_TDL_1,
METRIC_SET_ID_TDL_2,
METRIC_SET_ID_COMPUTE_EXTRA,
METRIC_SET_ID_VME_PIPE,
METRIC_SET_ID_TEST_OA,
}; };
int i915_oa_n_builtin_metric_sets_sklgt3 = 1; int i915_oa_n_builtin_metric_sets_sklgt3 = 18;
static const struct i915_oa_reg b_counter_config_render_basic[] = { static const struct i915_oa_reg b_counter_config_render_basic[] = {
{ _MMIO(0x2710), 0x00000000 }, { _MMIO(0x2710), 0x00000000 },
...@@ -157,66 +174,2669 @@ get_render_basic_mux_config(struct drm_i915_private *dev_priv, ...@@ -157,66 +174,2669 @@ get_render_basic_mux_config(struct drm_i915_private *dev_priv,
return n; return n;
} }
static const struct i915_oa_reg b_counter_config_compute_basic[] = {
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x00800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2740), 0x00000000 },
};
static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00000003 },
{ _MMIO(0xe658), 0x00002001 },
{ _MMIO(0xe758), 0x00778008 },
{ _MMIO(0xe45c), 0x00088078 },
{ _MMIO(0xe55c), 0x00808708 },
{ _MMIO(0xe65c), 0x00a08908 },
};
static const struct i915_oa_reg mux_config_compute_basic[] = {
{ _MMIO(0x9888), 0x104f00e0 },
{ _MMIO(0x9888), 0x124f1c00 },
{ _MMIO(0x9888), 0x106c00e0 },
{ _MMIO(0x9888), 0x37906800 },
{ _MMIO(0x9888), 0x3f900003 },
{ _MMIO(0x9888), 0x004e8000 },
{ _MMIO(0x9888), 0x1a4e0820 },
{ _MMIO(0x9888), 0x1c4e0002 },
{ _MMIO(0x9888), 0x064f0900 },
{ _MMIO(0x9888), 0x084f0032 },
{ _MMIO(0x9888), 0x0a4f1891 },
{ _MMIO(0x9888), 0x0c4f0e00 },
{ _MMIO(0x9888), 0x0e4f003c },
{ _MMIO(0x9888), 0x004f0d80 },
{ _MMIO(0x9888), 0x024f003b },
{ _MMIO(0x9888), 0x006c0002 },
{ _MMIO(0x9888), 0x086c0100 },
{ _MMIO(0x9888), 0x0c6c000c },
{ _MMIO(0x9888), 0x0e6c0b00 },
{ _MMIO(0x9888), 0x186c0000 },
{ _MMIO(0x9888), 0x1c6c0000 },
{ _MMIO(0x9888), 0x1e6c0000 },
{ _MMIO(0x9888), 0x001b4000 },
{ _MMIO(0x9888), 0x081b8000 },
{ _MMIO(0x9888), 0x0c1b4000 },
{ _MMIO(0x9888), 0x0e1b8000 },
{ _MMIO(0x9888), 0x101c8000 },
{ _MMIO(0x9888), 0x1a1c8000 },
{ _MMIO(0x9888), 0x1c1c0024 },
{ _MMIO(0x9888), 0x065b8000 },
{ _MMIO(0x9888), 0x085b4000 },
{ _MMIO(0x9888), 0x0a5bc000 },
{ _MMIO(0x9888), 0x0c5b8000 },
{ _MMIO(0x9888), 0x0e5b4000 },
{ _MMIO(0x9888), 0x005b8000 },
{ _MMIO(0x9888), 0x025b4000 },
{ _MMIO(0x9888), 0x1a5c6000 },
{ _MMIO(0x9888), 0x1c5c001b },
{ _MMIO(0x9888), 0x125c8000 },
{ _MMIO(0x9888), 0x145c8000 },
{ _MMIO(0x9888), 0x004c8000 },
{ _MMIO(0x9888), 0x0a4c2000 },
{ _MMIO(0x9888), 0x0c4c0208 },
{ _MMIO(0x9888), 0x000da000 },
{ _MMIO(0x9888), 0x060d8000 },
{ _MMIO(0x9888), 0x080da000 },
{ _MMIO(0x9888), 0x0a0da000 },
{ _MMIO(0x9888), 0x0c0da000 },
{ _MMIO(0x9888), 0x0e0da000 },
{ _MMIO(0x9888), 0x020d2000 },
{ _MMIO(0x9888), 0x0c0f5400 },
{ _MMIO(0x9888), 0x0e0f5500 },
{ _MMIO(0x9888), 0x100f0155 },
{ _MMIO(0x9888), 0x002c8000 },
{ _MMIO(0x9888), 0x0e2cc000 },
{ _MMIO(0x9888), 0x162cfb00 },
{ _MMIO(0x9888), 0x182c00be },
{ _MMIO(0x9888), 0x022cc000 },
{ _MMIO(0x9888), 0x042cc000 },
{ _MMIO(0x9888), 0x19900157 },
{ _MMIO(0x9888), 0x1b900158 },
{ _MMIO(0x9888), 0x1d900105 },
{ _MMIO(0x9888), 0x1f900103 },
{ _MMIO(0x9888), 0x35900000 },
{ _MMIO(0x9888), 0x11900fff },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900800 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x45900863 },
{ _MMIO(0x9888), 0x47900802 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900802 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900002 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x43900c62 },
{ _MMIO(0x9888), 0x53903333 },
};
static int
get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_basic;
lens[n] = ARRAY_SIZE(mux_config_compute_basic);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2770), 0x0007ffea },
{ _MMIO(0x2774), 0x00007ffc },
{ _MMIO(0x2778), 0x0007affa },
{ _MMIO(0x277c), 0x0000f5fd },
{ _MMIO(0x2780), 0x00079ffa },
{ _MMIO(0x2784), 0x0000f3fb },
{ _MMIO(0x2788), 0x0007bf7a },
{ _MMIO(0x278c), 0x0000f7e7 },
{ _MMIO(0x2790), 0x0007fefa },
{ _MMIO(0x2794), 0x0000f7cf },
{ _MMIO(0x2798), 0x00077ffa },
{ _MMIO(0x279c), 0x0000efdf },
{ _MMIO(0x27a0), 0x0006fffa },
{ _MMIO(0x27a4), 0x0000cfbf },
{ _MMIO(0x27a8), 0x0003fffa },
{ _MMIO(0x27ac), 0x00005f7f },
};
static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00015014 },
{ _MMIO(0xe658), 0x00025024 },
{ _MMIO(0xe758), 0x00035034 },
{ _MMIO(0xe45c), 0x00045044 },
{ _MMIO(0xe55c), 0x00055054 },
{ _MMIO(0xe65c), 0x00065064 },
};
static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
{ _MMIO(0x9888), 0x0c0e001f },
{ _MMIO(0x9888), 0x0a0f0000 },
{ _MMIO(0x9888), 0x10116800 },
{ _MMIO(0x9888), 0x178a03e0 },
{ _MMIO(0x9888), 0x11824c00 },
{ _MMIO(0x9888), 0x11830020 },
{ _MMIO(0x9888), 0x13840020 },
{ _MMIO(0x9888), 0x11850019 },
{ _MMIO(0x9888), 0x11860007 },
{ _MMIO(0x9888), 0x01870c40 },
{ _MMIO(0x9888), 0x17880000 },
{ _MMIO(0x9888), 0x022f4000 },
{ _MMIO(0x9888), 0x0a4c0040 },
{ _MMIO(0x9888), 0x0c0d8000 },
{ _MMIO(0x9888), 0x040d4000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x020e5400 },
{ _MMIO(0x9888), 0x000e0000 },
{ _MMIO(0x9888), 0x080f0040 },
{ _MMIO(0x9888), 0x000f0000 },
{ _MMIO(0x9888), 0x100f0000 },
{ _MMIO(0x9888), 0x0e0f0040 },
{ _MMIO(0x9888), 0x0c2c8000 },
{ _MMIO(0x9888), 0x06104000 },
{ _MMIO(0x9888), 0x06110012 },
{ _MMIO(0x9888), 0x06131000 },
{ _MMIO(0x9888), 0x01898000 },
{ _MMIO(0x9888), 0x0d890100 },
{ _MMIO(0x9888), 0x03898000 },
{ _MMIO(0x9888), 0x09808000 },
{ _MMIO(0x9888), 0x0b808000 },
{ _MMIO(0x9888), 0x0380c000 },
{ _MMIO(0x9888), 0x0f8a0075 },
{ _MMIO(0x9888), 0x1d8a0000 },
{ _MMIO(0x9888), 0x118a8000 },
{ _MMIO(0x9888), 0x1b8a4000 },
{ _MMIO(0x9888), 0x138a8000 },
{ _MMIO(0x9888), 0x1d81a000 },
{ _MMIO(0x9888), 0x15818000 },
{ _MMIO(0x9888), 0x17818000 },
{ _MMIO(0x9888), 0x0b820030 },
{ _MMIO(0x9888), 0x07828000 },
{ _MMIO(0x9888), 0x0d824000 },
{ _MMIO(0x9888), 0x0f828000 },
{ _MMIO(0x9888), 0x05824000 },
{ _MMIO(0x9888), 0x0d830003 },
{ _MMIO(0x9888), 0x0583000c },
{ _MMIO(0x9888), 0x09830000 },
{ _MMIO(0x9888), 0x03838000 },
{ _MMIO(0x9888), 0x07838000 },
{ _MMIO(0x9888), 0x0b840980 },
{ _MMIO(0x9888), 0x03844d80 },
{ _MMIO(0x9888), 0x11840000 },
{ _MMIO(0x9888), 0x09848000 },
{ _MMIO(0x9888), 0x09850080 },
{ _MMIO(0x9888), 0x03850003 },
{ _MMIO(0x9888), 0x01850000 },
{ _MMIO(0x9888), 0x07860000 },
{ _MMIO(0x9888), 0x0f860400 },
{ _MMIO(0x9888), 0x09870032 },
{ _MMIO(0x9888), 0x01888052 },
{ _MMIO(0x9888), 0x11880000 },
{ _MMIO(0x9888), 0x09884000 },
{ _MMIO(0x9888), 0x1b931001 },
{ _MMIO(0x9888), 0x1d930001 },
{ _MMIO(0x9888), 0x19934000 },
{ _MMIO(0x9888), 0x1b958000 },
{ _MMIO(0x9888), 0x1d950094 },
{ _MMIO(0x9888), 0x19958000 },
{ _MMIO(0x9888), 0x09e58000 },
{ _MMIO(0x9888), 0x0be58000 },
{ _MMIO(0x9888), 0x03e5c000 },
{ _MMIO(0x9888), 0x0592c000 },
{ _MMIO(0x9888), 0x0b928000 },
{ _MMIO(0x9888), 0x0d924000 },
{ _MMIO(0x9888), 0x0f924000 },
{ _MMIO(0x9888), 0x11928000 },
{ _MMIO(0x9888), 0x1392c000 },
{ _MMIO(0x9888), 0x09924000 },
{ _MMIO(0x9888), 0x01985000 },
{ _MMIO(0x9888), 0x07988000 },
{ _MMIO(0x9888), 0x09981000 },
{ _MMIO(0x9888), 0x0b982000 },
{ _MMIO(0x9888), 0x0d982000 },
{ _MMIO(0x9888), 0x0f989000 },
{ _MMIO(0x9888), 0x05982000 },
{ _MMIO(0x9888), 0x13904000 },
{ _MMIO(0x9888), 0x21904000 },
{ _MMIO(0x9888), 0x23904000 },
{ _MMIO(0x9888), 0x25908000 },
{ _MMIO(0x9888), 0x27904000 },
{ _MMIO(0x9888), 0x29908000 },
{ _MMIO(0x9888), 0x2b904000 },
{ _MMIO(0x9888), 0x2f904000 },
{ _MMIO(0x9888), 0x31904000 },
{ _MMIO(0x9888), 0x15904000 },
{ _MMIO(0x9888), 0x17908000 },
{ _MMIO(0x9888), 0x19908000 },
{ _MMIO(0x9888), 0x1b904000 },
{ _MMIO(0x9888), 0x1190c080 },
{ _MMIO(0x9888), 0x51901150 },
{ _MMIO(0x9888), 0x41901400 },
{ _MMIO(0x9888), 0x55905111 },
{ _MMIO(0x9888), 0x45901400 },
{ _MMIO(0x9888), 0x479004a5 },
{ _MMIO(0x9888), 0x57903455 },
{ _MMIO(0x9888), 0x49900000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b9000a0 },
{ _MMIO(0x9888), 0x59900001 },
{ _MMIO(0x9888), 0x43900005 },
{ _MMIO(0x9888), 0x53900455 },
};
static int
get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_render_pipe_profile;
lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_memory_reads[] = {
{ _MMIO(0x272c), 0xffffffff },
{ _MMIO(0x2728), 0xffffffff },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x271c), 0xffffffff },
{ _MMIO(0x2718), 0xffffffff },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x274c), 0x86543210 },
{ _MMIO(0x2748), 0x86543210 },
{ _MMIO(0x2744), 0x00006667 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x275c), 0x86543210 },
{ _MMIO(0x2758), 0x86543210 },
{ _MMIO(0x2754), 0x00006465 },
{ _MMIO(0x2750), 0x00000000 },
{ _MMIO(0x2770), 0x0007f81a },
{ _MMIO(0x2774), 0x0000fe00 },
{ _MMIO(0x2778), 0x0007f82a },
{ _MMIO(0x277c), 0x0000fe00 },
{ _MMIO(0x2780), 0x0007f872 },
{ _MMIO(0x2784), 0x0000fe00 },
{ _MMIO(0x2788), 0x0007f8ba },
{ _MMIO(0x278c), 0x0000fe00 },
{ _MMIO(0x2790), 0x0007f87a },
{ _MMIO(0x2794), 0x0000fe00 },
{ _MMIO(0x2798), 0x0007f8ea },
{ _MMIO(0x279c), 0x0000fe00 },
{ _MMIO(0x27a0), 0x0007f8e2 },
{ _MMIO(0x27a4), 0x0000fe00 },
{ _MMIO(0x27a8), 0x0007f8f2 },
{ _MMIO(0x27ac), 0x0000fe00 },
};
static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00015014 },
{ _MMIO(0xe658), 0x00025024 },
{ _MMIO(0xe758), 0x00035034 },
{ _MMIO(0xe45c), 0x00045044 },
{ _MMIO(0xe55c), 0x00055054 },
{ _MMIO(0xe65c), 0x00065064 },
};
static const struct i915_oa_reg mux_config_memory_reads[] = {
{ _MMIO(0x9888), 0x11810c00 },
{ _MMIO(0x9888), 0x1381001a },
{ _MMIO(0x9888), 0x37906800 },
{ _MMIO(0x9888), 0x3f900064 },
{ _MMIO(0x9888), 0x03811300 },
{ _MMIO(0x9888), 0x05811b12 },
{ _MMIO(0x9888), 0x0781001a },
{ _MMIO(0x9888), 0x1f810000 },
{ _MMIO(0x9888), 0x17810000 },
{ _MMIO(0x9888), 0x19810000 },
{ _MMIO(0x9888), 0x1b810000 },
{ _MMIO(0x9888), 0x1d810000 },
{ _MMIO(0x9888), 0x1b930055 },
{ _MMIO(0x9888), 0x03e58000 },
{ _MMIO(0x9888), 0x05e5c000 },
{ _MMIO(0x9888), 0x07e54000 },
{ _MMIO(0x9888), 0x13900150 },
{ _MMIO(0x9888), 0x21900151 },
{ _MMIO(0x9888), 0x23900152 },
{ _MMIO(0x9888), 0x25900153 },
{ _MMIO(0x9888), 0x27900154 },
{ _MMIO(0x9888), 0x29900155 },
{ _MMIO(0x9888), 0x2b900156 },
{ _MMIO(0x9888), 0x2d900157 },
{ _MMIO(0x9888), 0x2f90015f },
{ _MMIO(0x9888), 0x31900105 },
{ _MMIO(0x9888), 0x15900103 },
{ _MMIO(0x9888), 0x17900101 },
{ _MMIO(0x9888), 0x35900000 },
{ _MMIO(0x9888), 0x19908000 },
{ _MMIO(0x9888), 0x1b908000 },
{ _MMIO(0x9888), 0x1d908000 },
{ _MMIO(0x9888), 0x1f908000 },
{ _MMIO(0x9888), 0x11900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900c60 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x45900c00 },
{ _MMIO(0x9888), 0x47900c63 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900c63 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900063 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x43900003 },
{ _MMIO(0x9888), 0x53900000 },
};
static int
get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_memory_reads;
lens[n] = ARRAY_SIZE(mux_config_memory_reads);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_memory_writes[] = {
{ _MMIO(0x272c), 0xffffffff },
{ _MMIO(0x2728), 0xffffffff },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x271c), 0xffffffff },
{ _MMIO(0x2718), 0xffffffff },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x274c), 0x86543210 },
{ _MMIO(0x2748), 0x86543210 },
{ _MMIO(0x2744), 0x00006667 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x275c), 0x86543210 },
{ _MMIO(0x2758), 0x86543210 },
{ _MMIO(0x2754), 0x00006465 },
{ _MMIO(0x2750), 0x00000000 },
{ _MMIO(0x2770), 0x0007f81a },
{ _MMIO(0x2774), 0x0000fe00 },
{ _MMIO(0x2778), 0x0007f82a },
{ _MMIO(0x277c), 0x0000fe00 },
{ _MMIO(0x2780), 0x0007f822 },
{ _MMIO(0x2784), 0x0000fe00 },
{ _MMIO(0x2788), 0x0007f8ba },
{ _MMIO(0x278c), 0x0000fe00 },
{ _MMIO(0x2790), 0x0007f87a },
{ _MMIO(0x2794), 0x0000fe00 },
{ _MMIO(0x2798), 0x0007f8ea },
{ _MMIO(0x279c), 0x0000fe00 },
{ _MMIO(0x27a0), 0x0007f8e2 },
{ _MMIO(0x27a4), 0x0000fe00 },
{ _MMIO(0x27a8), 0x0007f8f2 },
{ _MMIO(0x27ac), 0x0000fe00 },
};
static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00015014 },
{ _MMIO(0xe658), 0x00025024 },
{ _MMIO(0xe758), 0x00035034 },
{ _MMIO(0xe45c), 0x00045044 },
{ _MMIO(0xe55c), 0x00055054 },
{ _MMIO(0xe65c), 0x00065064 },
};
static const struct i915_oa_reg mux_config_memory_writes[] = {
{ _MMIO(0x9888), 0x11810c00 },
{ _MMIO(0x9888), 0x1381001a },
{ _MMIO(0x9888), 0x37906800 },
{ _MMIO(0x9888), 0x3f901000 },
{ _MMIO(0x9888), 0x03811300 },
{ _MMIO(0x9888), 0x05811b12 },
{ _MMIO(0x9888), 0x0781001a },
{ _MMIO(0x9888), 0x1f810000 },
{ _MMIO(0x9888), 0x17810000 },
{ _MMIO(0x9888), 0x19810000 },
{ _MMIO(0x9888), 0x1b810000 },
{ _MMIO(0x9888), 0x1d810000 },
{ _MMIO(0x9888), 0x1b930055 },
{ _MMIO(0x9888), 0x03e58000 },
{ _MMIO(0x9888), 0x05e5c000 },
{ _MMIO(0x9888), 0x07e54000 },
{ _MMIO(0x9888), 0x13900160 },
{ _MMIO(0x9888), 0x21900161 },
{ _MMIO(0x9888), 0x23900162 },
{ _MMIO(0x9888), 0x25900163 },
{ _MMIO(0x9888), 0x27900164 },
{ _MMIO(0x9888), 0x29900165 },
{ _MMIO(0x9888), 0x2b900166 },
{ _MMIO(0x9888), 0x2d900167 },
{ _MMIO(0x9888), 0x2f900150 },
{ _MMIO(0x9888), 0x31900105 },
{ _MMIO(0x9888), 0x15900103 },
{ _MMIO(0x9888), 0x17900101 },
{ _MMIO(0x9888), 0x35900000 },
{ _MMIO(0x9888), 0x19908000 },
{ _MMIO(0x9888), 0x1b908000 },
{ _MMIO(0x9888), 0x1d908000 },
{ _MMIO(0x9888), 0x1f908000 },
{ _MMIO(0x9888), 0x11900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900c60 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x45900c00 },
{ _MMIO(0x9888), 0x47900c63 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900c63 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900063 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x43900003 },
{ _MMIO(0x9888), 0x53900000 },
};
static int
get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_memory_writes;
lens[n] = ARRAY_SIZE(mux_config_memory_writes);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_compute_extended[] = {
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2770), 0x0007fc2a },
{ _MMIO(0x2774), 0x0000bf00 },
{ _MMIO(0x2778), 0x0007fc6a },
{ _MMIO(0x277c), 0x0000bf00 },
{ _MMIO(0x2780), 0x0007fc92 },
{ _MMIO(0x2784), 0x0000bf00 },
{ _MMIO(0x2788), 0x0007fca2 },
{ _MMIO(0x278c), 0x0000bf00 },
{ _MMIO(0x2790), 0x0007fc32 },
{ _MMIO(0x2794), 0x0000bf00 },
{ _MMIO(0x2798), 0x0007fc9a },
{ _MMIO(0x279c), 0x0000bf00 },
{ _MMIO(0x27a0), 0x0007fe6a },
{ _MMIO(0x27a4), 0x0000bf00 },
{ _MMIO(0x27a8), 0x0007fe7a },
{ _MMIO(0x27ac), 0x0000bf00 },
};
static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00000003 },
{ _MMIO(0xe658), 0x00002001 },
{ _MMIO(0xe758), 0x00778008 },
{ _MMIO(0xe45c), 0x00088078 },
{ _MMIO(0xe55c), 0x00808708 },
{ _MMIO(0xe65c), 0x00a08908 },
};
static const struct i915_oa_reg mux_config_compute_extended[] = {
{ _MMIO(0x9888), 0x106c00e0 },
{ _MMIO(0x9888), 0x141c8160 },
{ _MMIO(0x9888), 0x161c8015 },
{ _MMIO(0x9888), 0x181c0120 },
{ _MMIO(0x9888), 0x004e8000 },
{ _MMIO(0x9888), 0x0e4e8000 },
{ _MMIO(0x9888), 0x184e8000 },
{ _MMIO(0x9888), 0x1a4eaaa0 },
{ _MMIO(0x9888), 0x1c4e0002 },
{ _MMIO(0x9888), 0x024e8000 },
{ _MMIO(0x9888), 0x044e8000 },
{ _MMIO(0x9888), 0x064e8000 },
{ _MMIO(0x9888), 0x084e8000 },
{ _MMIO(0x9888), 0x0a4e8000 },
{ _MMIO(0x9888), 0x0e6c0b01 },
{ _MMIO(0x9888), 0x006c0200 },
{ _MMIO(0x9888), 0x026c000c },
{ _MMIO(0x9888), 0x1c6c0000 },
{ _MMIO(0x9888), 0x1e6c0000 },
{ _MMIO(0x9888), 0x1a6c0000 },
{ _MMIO(0x9888), 0x0e1bc000 },
{ _MMIO(0x9888), 0x001b8000 },
{ _MMIO(0x9888), 0x021bc000 },
{ _MMIO(0x9888), 0x001c0041 },
{ _MMIO(0x9888), 0x061c4200 },
{ _MMIO(0x9888), 0x081c4443 },
{ _MMIO(0x9888), 0x0a1c4645 },
{ _MMIO(0x9888), 0x0c1c7647 },
{ _MMIO(0x9888), 0x041c7357 },
{ _MMIO(0x9888), 0x1c1c0030 },
{ _MMIO(0x9888), 0x101c0000 },
{ _MMIO(0x9888), 0x1a1c0000 },
{ _MMIO(0x9888), 0x121c8000 },
{ _MMIO(0x9888), 0x004c8000 },
{ _MMIO(0x9888), 0x0a4caa2a },
{ _MMIO(0x9888), 0x0c4c02aa },
{ _MMIO(0x9888), 0x084ca000 },
{ _MMIO(0x9888), 0x000da000 },
{ _MMIO(0x9888), 0x060d8000 },
{ _MMIO(0x9888), 0x080da000 },
{ _MMIO(0x9888), 0x0a0da000 },
{ _MMIO(0x9888), 0x0c0da000 },
{ _MMIO(0x9888), 0x0e0da000 },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x0c0f5400 },
{ _MMIO(0x9888), 0x0e0f5515 },
{ _MMIO(0x9888), 0x100f0155 },
{ _MMIO(0x9888), 0x002c8000 },
{ _MMIO(0x9888), 0x0e2c8000 },
{ _MMIO(0x9888), 0x162caa00 },
{ _MMIO(0x9888), 0x182c00aa },
{ _MMIO(0x9888), 0x022c8000 },
{ _MMIO(0x9888), 0x042c8000 },
{ _MMIO(0x9888), 0x062c8000 },
{ _MMIO(0x9888), 0x082c8000 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x11907fff },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900040 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x45900802 },
{ _MMIO(0x9888), 0x47900842 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900842 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900000 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x43900800 },
{ _MMIO(0x9888), 0x53900000 },
};
static int
get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_extended;
lens[n] = ARRAY_SIZE(mux_config_compute_extended);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x30800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x30800000 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2770), 0x0007fffa },
{ _MMIO(0x2774), 0x0000fefe },
{ _MMIO(0x2778), 0x0007fffa },
{ _MMIO(0x277c), 0x0000fefd },
{ _MMIO(0x2790), 0x0007fffa },
{ _MMIO(0x2794), 0x0000fbef },
{ _MMIO(0x2798), 0x0007fffa },
{ _MMIO(0x279c), 0x0000fbdf },
};
static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00000003 },
{ _MMIO(0xe658), 0x00002001 },
{ _MMIO(0xe758), 0x00101100 },
{ _MMIO(0xe45c), 0x00201200 },
{ _MMIO(0xe55c), 0x00301300 },
{ _MMIO(0xe65c), 0x00401400 },
};
static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
{ _MMIO(0x9888), 0x166c0760 },
{ _MMIO(0x9888), 0x1593001e },
{ _MMIO(0x9888), 0x3f900003 },
{ _MMIO(0x9888), 0x004e8000 },
{ _MMIO(0x9888), 0x0e4e8000 },
{ _MMIO(0x9888), 0x184e8000 },
{ _MMIO(0x9888), 0x1a4e8020 },
{ _MMIO(0x9888), 0x1c4e0002 },
{ _MMIO(0x9888), 0x006c0051 },
{ _MMIO(0x9888), 0x066c5000 },
{ _MMIO(0x9888), 0x086c5c5d },
{ _MMIO(0x9888), 0x0e6c5e5f },
{ _MMIO(0x9888), 0x106c0000 },
{ _MMIO(0x9888), 0x186c0000 },
{ _MMIO(0x9888), 0x1c6c0000 },
{ _MMIO(0x9888), 0x1e6c0000 },
{ _MMIO(0x9888), 0x001b4000 },
{ _MMIO(0x9888), 0x061b8000 },
{ _MMIO(0x9888), 0x081bc000 },
{ _MMIO(0x9888), 0x0e1bc000 },
{ _MMIO(0x9888), 0x101c8000 },
{ _MMIO(0x9888), 0x1a1ce000 },
{ _MMIO(0x9888), 0x1c1c0030 },
{ _MMIO(0x9888), 0x004c8000 },
{ _MMIO(0x9888), 0x0a4c2a00 },
{ _MMIO(0x9888), 0x0c4c0280 },
{ _MMIO(0x9888), 0x000d2000 },
{ _MMIO(0x9888), 0x060d8000 },
{ _MMIO(0x9888), 0x080da000 },
{ _MMIO(0x9888), 0x0e0da000 },
{ _MMIO(0x9888), 0x0c0f0400 },
{ _MMIO(0x9888), 0x0e0f1500 },
{ _MMIO(0x9888), 0x100f0140 },
{ _MMIO(0x9888), 0x002c8000 },
{ _MMIO(0x9888), 0x0e2c8000 },
{ _MMIO(0x9888), 0x162c0a00 },
{ _MMIO(0x9888), 0x182c00a0 },
{ _MMIO(0x9888), 0x03933300 },
{ _MMIO(0x9888), 0x05930032 },
{ _MMIO(0x9888), 0x11930000 },
{ _MMIO(0x9888), 0x1b930000 },
{ _MMIO(0x9888), 0x1d900157 },
{ _MMIO(0x9888), 0x1f900158 },
{ _MMIO(0x9888), 0x35900000 },
{ _MMIO(0x9888), 0x19908000 },
{ _MMIO(0x9888), 0x1b908000 },
{ _MMIO(0x9888), 0x1190030f },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900000 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x45900063 },
{ _MMIO(0x9888), 0x47900000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x4b900000 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x53903333 },
{ _MMIO(0x9888), 0x43900840 },
};
static int
get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_l3_cache;
lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x10800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x00000002 },
{ _MMIO(0x2774), 0x0000fdff },
};
static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
{ _MMIO(0x9888), 0x104f0232 },
{ _MMIO(0x9888), 0x124f4640 },
{ _MMIO(0x9888), 0x106c0232 },
{ _MMIO(0x9888), 0x11834400 },
{ _MMIO(0x9888), 0x0a4e8000 },
{ _MMIO(0x9888), 0x0c4e8000 },
{ _MMIO(0x9888), 0x004f1880 },
{ _MMIO(0x9888), 0x024f08bb },
{ _MMIO(0x9888), 0x044f001b },
{ _MMIO(0x9888), 0x046c0100 },
{ _MMIO(0x9888), 0x066c000b },
{ _MMIO(0x9888), 0x1a6c0000 },
{ _MMIO(0x9888), 0x041b8000 },
{ _MMIO(0x9888), 0x061b4000 },
{ _MMIO(0x9888), 0x1a1c1800 },
{ _MMIO(0x9888), 0x005b8000 },
{ _MMIO(0x9888), 0x025bc000 },
{ _MMIO(0x9888), 0x045b4000 },
{ _MMIO(0x9888), 0x125c8000 },
{ _MMIO(0x9888), 0x145c8000 },
{ _MMIO(0x9888), 0x165c8000 },
{ _MMIO(0x9888), 0x185c8000 },
{ _MMIO(0x9888), 0x0a4c00a0 },
{ _MMIO(0x9888), 0x000d8000 },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x0c0f5000 },
{ _MMIO(0x9888), 0x0e0f0055 },
{ _MMIO(0x9888), 0x022cc000 },
{ _MMIO(0x9888), 0x042cc000 },
{ _MMIO(0x9888), 0x062cc000 },
{ _MMIO(0x9888), 0x082cc000 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x0c2c8000 },
{ _MMIO(0x9888), 0x0f828000 },
{ _MMIO(0x9888), 0x0f8305c0 },
{ _MMIO(0x9888), 0x09830000 },
{ _MMIO(0x9888), 0x07830000 },
{ _MMIO(0x9888), 0x1d950080 },
{ _MMIO(0x9888), 0x13928000 },
{ _MMIO(0x9888), 0x0f988000 },
{ _MMIO(0x9888), 0x31904000 },
{ _MMIO(0x9888), 0x1190fc00 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x59900005 },
{ _MMIO(0x9888), 0x4b900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900800 },
{ _MMIO(0x9888), 0x43900842 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900000 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_hdc_and_sf;
lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_l3_1[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2770), 0x00100070 },
{ _MMIO(0x2774), 0x0000fff1 },
{ _MMIO(0x2778), 0x00014002 },
{ _MMIO(0x277c), 0x0000c3ff },
{ _MMIO(0x2780), 0x00010002 },
{ _MMIO(0x2784), 0x0000c7ff },
{ _MMIO(0x2788), 0x00004002 },
{ _MMIO(0x278c), 0x0000d3ff },
{ _MMIO(0x2790), 0x00100700 },
{ _MMIO(0x2794), 0x0000ff1f },
{ _MMIO(0x2798), 0x00001402 },
{ _MMIO(0x279c), 0x0000fc3f },
{ _MMIO(0x27a0), 0x00001002 },
{ _MMIO(0x27a4), 0x0000fc7f },
{ _MMIO(0x27a8), 0x00000402 },
{ _MMIO(0x27ac), 0x0000fd3f },
};
static const struct i915_oa_reg flex_eu_config_l3_1[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_l3_1[] = {
{ _MMIO(0x9888), 0x126c7b40 },
{ _MMIO(0x9888), 0x166c0020 },
{ _MMIO(0x9888), 0x0a603444 },
{ _MMIO(0x9888), 0x0a613400 },
{ _MMIO(0x9888), 0x1a4ea800 },
{ _MMIO(0x9888), 0x1c4e0002 },
{ _MMIO(0x9888), 0x024e8000 },
{ _MMIO(0x9888), 0x044e8000 },
{ _MMIO(0x9888), 0x064e8000 },
{ _MMIO(0x9888), 0x084e8000 },
{ _MMIO(0x9888), 0x0a4e8000 },
{ _MMIO(0x9888), 0x064f4000 },
{ _MMIO(0x9888), 0x0c6c5327 },
{ _MMIO(0x9888), 0x0e6c5425 },
{ _MMIO(0x9888), 0x006c2a00 },
{ _MMIO(0x9888), 0x026c285b },
{ _MMIO(0x9888), 0x046c005c },
{ _MMIO(0x9888), 0x106c0000 },
{ _MMIO(0x9888), 0x1c6c0000 },
{ _MMIO(0x9888), 0x1e6c0000 },
{ _MMIO(0x9888), 0x1a6c0800 },
{ _MMIO(0x9888), 0x0c1bc000 },
{ _MMIO(0x9888), 0x0e1bc000 },
{ _MMIO(0x9888), 0x001b8000 },
{ _MMIO(0x9888), 0x021bc000 },
{ _MMIO(0x9888), 0x041bc000 },
{ _MMIO(0x9888), 0x1c1c003c },
{ _MMIO(0x9888), 0x121c8000 },
{ _MMIO(0x9888), 0x141c8000 },
{ _MMIO(0x9888), 0x161c8000 },
{ _MMIO(0x9888), 0x181c8000 },
{ _MMIO(0x9888), 0x1a1c0800 },
{ _MMIO(0x9888), 0x065b4000 },
{ _MMIO(0x9888), 0x1a5c1000 },
{ _MMIO(0x9888), 0x10600000 },
{ _MMIO(0x9888), 0x04600000 },
{ _MMIO(0x9888), 0x0c610044 },
{ _MMIO(0x9888), 0x10610000 },
{ _MMIO(0x9888), 0x06610000 },
{ _MMIO(0x9888), 0x0c4c02a8 },
{ _MMIO(0x9888), 0x084ca000 },
{ _MMIO(0x9888), 0x0a4c002a },
{ _MMIO(0x9888), 0x0c0da000 },
{ _MMIO(0x9888), 0x0e0da000 },
{ _MMIO(0x9888), 0x000d8000 },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x100f0154 },
{ _MMIO(0x9888), 0x0c0f5000 },
{ _MMIO(0x9888), 0x0e0f0055 },
{ _MMIO(0x9888), 0x182c00aa },
{ _MMIO(0x9888), 0x022c8000 },
{ _MMIO(0x9888), 0x042c8000 },
{ _MMIO(0x9888), 0x062c8000 },
{ _MMIO(0x9888), 0x082c8000 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x0c2cc000 },
{ _MMIO(0x9888), 0x1190ffc0 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900420 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900021 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900400 },
{ _MMIO(0x9888), 0x43900421 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900040 },
};
static int
get_l3_1_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_l3_1;
lens[n] = ARRAY_SIZE(mux_config_l3_1);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_l3_2[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x00100070 },
{ _MMIO(0x2774), 0x0000fff1 },
{ _MMIO(0x2778), 0x00028002 },
{ _MMIO(0x277c), 0x000087ff },
{ _MMIO(0x2780), 0x00020002 },
{ _MMIO(0x2784), 0x00008fff },
{ _MMIO(0x2788), 0x00008002 },
{ _MMIO(0x278c), 0x0000a7ff },
};
static const struct i915_oa_reg flex_eu_config_l3_2[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_l3_2[] = {
{ _MMIO(0x9888), 0x126c02e0 },
{ _MMIO(0x9888), 0x146c0001 },
{ _MMIO(0x9888), 0x0a623400 },
{ _MMIO(0x9888), 0x044e8000 },
{ _MMIO(0x9888), 0x064e8000 },
{ _MMIO(0x9888), 0x084e8000 },
{ _MMIO(0x9888), 0x0a4e8000 },
{ _MMIO(0x9888), 0x064f4000 },
{ _MMIO(0x9888), 0x026c3324 },
{ _MMIO(0x9888), 0x046c3422 },
{ _MMIO(0x9888), 0x106c0000 },
{ _MMIO(0x9888), 0x1a6c0000 },
{ _MMIO(0x9888), 0x021bc000 },
{ _MMIO(0x9888), 0x041bc000 },
{ _MMIO(0x9888), 0x141c8000 },
{ _MMIO(0x9888), 0x161c8000 },
{ _MMIO(0x9888), 0x181c8000 },
{ _MMIO(0x9888), 0x1a1c0800 },
{ _MMIO(0x9888), 0x065b4000 },
{ _MMIO(0x9888), 0x1a5c1000 },
{ _MMIO(0x9888), 0x06614000 },
{ _MMIO(0x9888), 0x0c620044 },
{ _MMIO(0x9888), 0x10620000 },
{ _MMIO(0x9888), 0x06620000 },
{ _MMIO(0x9888), 0x084c8000 },
{ _MMIO(0x9888), 0x0a4c002a },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x0c0f4000 },
{ _MMIO(0x9888), 0x0e0f0055 },
{ _MMIO(0x9888), 0x042c8000 },
{ _MMIO(0x9888), 0x062c8000 },
{ _MMIO(0x9888), 0x082c8000 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x0c2cc000 },
{ _MMIO(0x9888), 0x1190f800 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x43900000 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900000 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_l3_2_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_l3_2;
lens[n] = ARRAY_SIZE(mux_config_l3_2);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_l3_3[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x00100070 },
{ _MMIO(0x2774), 0x0000fff1 },
{ _MMIO(0x2778), 0x00028002 },
{ _MMIO(0x277c), 0x000087ff },
{ _MMIO(0x2780), 0x00020002 },
{ _MMIO(0x2784), 0x00008fff },
{ _MMIO(0x2788), 0x00008002 },
{ _MMIO(0x278c), 0x0000a7ff },
};
static const struct i915_oa_reg flex_eu_config_l3_3[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_l3_3[] = {
{ _MMIO(0x9888), 0x126c4e80 },
{ _MMIO(0x9888), 0x146c0000 },
{ _MMIO(0x9888), 0x0a633400 },
{ _MMIO(0x9888), 0x044e8000 },
{ _MMIO(0x9888), 0x064e8000 },
{ _MMIO(0x9888), 0x084e8000 },
{ _MMIO(0x9888), 0x0a4e8000 },
{ _MMIO(0x9888), 0x0c4e8000 },
{ _MMIO(0x9888), 0x026c3321 },
{ _MMIO(0x9888), 0x046c342f },
{ _MMIO(0x9888), 0x106c0000 },
{ _MMIO(0x9888), 0x1a6c2000 },
{ _MMIO(0x9888), 0x021bc000 },
{ _MMIO(0x9888), 0x041bc000 },
{ _MMIO(0x9888), 0x061b4000 },
{ _MMIO(0x9888), 0x141c8000 },
{ _MMIO(0x9888), 0x161c8000 },
{ _MMIO(0x9888), 0x181c8000 },
{ _MMIO(0x9888), 0x1a1c1800 },
{ _MMIO(0x9888), 0x06604000 },
{ _MMIO(0x9888), 0x0c630044 },
{ _MMIO(0x9888), 0x10630000 },
{ _MMIO(0x9888), 0x06630000 },
{ _MMIO(0x9888), 0x084c8000 },
{ _MMIO(0x9888), 0x0a4c00aa },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x0c0f4000 },
{ _MMIO(0x9888), 0x0e0f0055 },
{ _MMIO(0x9888), 0x042c8000 },
{ _MMIO(0x9888), 0x062c8000 },
{ _MMIO(0x9888), 0x082c8000 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x0c2c8000 },
{ _MMIO(0x9888), 0x1190f800 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x43900842 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900002 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_l3_3_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_l3_3;
lens[n] = ARRAY_SIZE(mux_config_l3_3);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x30800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x00000002 },
{ _MMIO(0x2774), 0x0000efff },
{ _MMIO(0x2778), 0x00006000 },
{ _MMIO(0x277c), 0x0000f3ff },
};
static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
{ _MMIO(0x9888), 0x102f3800 },
{ _MMIO(0x9888), 0x144d0500 },
{ _MMIO(0x9888), 0x120d03c0 },
{ _MMIO(0x9888), 0x140d03cf },
{ _MMIO(0x9888), 0x0c0f0004 },
{ _MMIO(0x9888), 0x0c4e4000 },
{ _MMIO(0x9888), 0x042f0480 },
{ _MMIO(0x9888), 0x082f0000 },
{ _MMIO(0x9888), 0x022f0000 },
{ _MMIO(0x9888), 0x0a4c0090 },
{ _MMIO(0x9888), 0x064d0027 },
{ _MMIO(0x9888), 0x004d0000 },
{ _MMIO(0x9888), 0x000d0d40 },
{ _MMIO(0x9888), 0x020d803f },
{ _MMIO(0x9888), 0x040d8023 },
{ _MMIO(0x9888), 0x100d0000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x020f0010 },
{ _MMIO(0x9888), 0x000f0000 },
{ _MMIO(0x9888), 0x0e0f0050 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x0c2c8000 },
{ _MMIO(0x9888), 0x1190fc00 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41901400 },
{ _MMIO(0x9888), 0x43901485 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900001 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_rasterizer_and_pixel_backend;
lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_sampler[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x70800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x0000c000 },
{ _MMIO(0x2774), 0x0000e7ff },
{ _MMIO(0x2778), 0x00003000 },
{ _MMIO(0x277c), 0x0000f9ff },
{ _MMIO(0x2780), 0x00000c00 },
{ _MMIO(0x2784), 0x0000fe7f },
};
static const struct i915_oa_reg flex_eu_config_sampler[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_sampler[] = {
{ _MMIO(0x9888), 0x14152c00 },
{ _MMIO(0x9888), 0x16150005 },
{ _MMIO(0x9888), 0x121600a0 },
{ _MMIO(0x9888), 0x14352c00 },
{ _MMIO(0x9888), 0x16350005 },
{ _MMIO(0x9888), 0x123600a0 },
{ _MMIO(0x9888), 0x14552c00 },
{ _MMIO(0x9888), 0x16550005 },
{ _MMIO(0x9888), 0x125600a0 },
{ _MMIO(0x9888), 0x062f6000 },
{ _MMIO(0x9888), 0x022f2000 },
{ _MMIO(0x9888), 0x0c4c0050 },
{ _MMIO(0x9888), 0x0a4c0010 },
{ _MMIO(0x9888), 0x0c0d8000 },
{ _MMIO(0x9888), 0x0e0da000 },
{ _MMIO(0x9888), 0x000d8000 },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x100f0350 },
{ _MMIO(0x9888), 0x0c0fb000 },
{ _MMIO(0x9888), 0x0e0f00da },
{ _MMIO(0x9888), 0x182c0028 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x022dc000 },
{ _MMIO(0x9888), 0x042d4000 },
{ _MMIO(0x9888), 0x0c138000 },
{ _MMIO(0x9888), 0x0e132000 },
{ _MMIO(0x9888), 0x0413c000 },
{ _MMIO(0x9888), 0x1c140018 },
{ _MMIO(0x9888), 0x0c157000 },
{ _MMIO(0x9888), 0x0e150078 },
{ _MMIO(0x9888), 0x10150000 },
{ _MMIO(0x9888), 0x04162180 },
{ _MMIO(0x9888), 0x02160000 },
{ _MMIO(0x9888), 0x04174000 },
{ _MMIO(0x9888), 0x0233a000 },
{ _MMIO(0x9888), 0x04333000 },
{ _MMIO(0x9888), 0x14348000 },
{ _MMIO(0x9888), 0x16348000 },
{ _MMIO(0x9888), 0x02357870 },
{ _MMIO(0x9888), 0x10350000 },
{ _MMIO(0x9888), 0x04360043 },
{ _MMIO(0x9888), 0x02360000 },
{ _MMIO(0x9888), 0x04371000 },
{ _MMIO(0x9888), 0x0e538000 },
{ _MMIO(0x9888), 0x00538000 },
{ _MMIO(0x9888), 0x06533000 },
{ _MMIO(0x9888), 0x1c540020 },
{ _MMIO(0x9888), 0x12548000 },
{ _MMIO(0x9888), 0x0e557000 },
{ _MMIO(0x9888), 0x00557800 },
{ _MMIO(0x9888), 0x10550000 },
{ _MMIO(0x9888), 0x06560043 },
{ _MMIO(0x9888), 0x02560000 },
{ _MMIO(0x9888), 0x06571000 },
{ _MMIO(0x9888), 0x1190ff80 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900060 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900c00 },
{ _MMIO(0x9888), 0x43900842 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900060 },
};
static int
get_sampler_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_sampler;
lens[n] = ARRAY_SIZE(mux_config_sampler);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_tdl_1[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x30800000 },
{ _MMIO(0x2770), 0x00000002 },
{ _MMIO(0x2774), 0x00007fff },
{ _MMIO(0x2778), 0x00000000 },
{ _MMIO(0x277c), 0x00009fff },
{ _MMIO(0x2780), 0x00000002 },
{ _MMIO(0x2784), 0x0000efff },
{ _MMIO(0x2788), 0x00000000 },
{ _MMIO(0x278c), 0x0000f3ff },
{ _MMIO(0x2790), 0x00000002 },
{ _MMIO(0x2794), 0x0000fdff },
{ _MMIO(0x2798), 0x00000000 },
{ _MMIO(0x279c), 0x0000fe7f },
};
static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_tdl_1[] = {
{ _MMIO(0x9888), 0x12120000 },
{ _MMIO(0x9888), 0x12320000 },
{ _MMIO(0x9888), 0x12520000 },
{ _MMIO(0x9888), 0x002f8000 },
{ _MMIO(0x9888), 0x022f3000 },
{ _MMIO(0x9888), 0x0a4c0015 },
{ _MMIO(0x9888), 0x0c0d8000 },
{ _MMIO(0x9888), 0x0e0da000 },
{ _MMIO(0x9888), 0x000d8000 },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x100f03a0 },
{ _MMIO(0x9888), 0x0c0ff000 },
{ _MMIO(0x9888), 0x0e0f0095 },
{ _MMIO(0x9888), 0x062c8000 },
{ _MMIO(0x9888), 0x082c8000 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x0c2d8000 },
{ _MMIO(0x9888), 0x0e2d4000 },
{ _MMIO(0x9888), 0x062d4000 },
{ _MMIO(0x9888), 0x02108000 },
{ _MMIO(0x9888), 0x0410c000 },
{ _MMIO(0x9888), 0x02118000 },
{ _MMIO(0x9888), 0x0411c000 },
{ _MMIO(0x9888), 0x02121880 },
{ _MMIO(0x9888), 0x041219b5 },
{ _MMIO(0x9888), 0x00120000 },
{ _MMIO(0x9888), 0x02134000 },
{ _MMIO(0x9888), 0x04135000 },
{ _MMIO(0x9888), 0x0c308000 },
{ _MMIO(0x9888), 0x0e304000 },
{ _MMIO(0x9888), 0x06304000 },
{ _MMIO(0x9888), 0x0c318000 },
{ _MMIO(0x9888), 0x0e314000 },
{ _MMIO(0x9888), 0x06314000 },
{ _MMIO(0x9888), 0x0c321a80 },
{ _MMIO(0x9888), 0x0e320033 },
{ _MMIO(0x9888), 0x06320031 },
{ _MMIO(0x9888), 0x00320000 },
{ _MMIO(0x9888), 0x0c334000 },
{ _MMIO(0x9888), 0x0e331000 },
{ _MMIO(0x9888), 0x06331000 },
{ _MMIO(0x9888), 0x0e508000 },
{ _MMIO(0x9888), 0x00508000 },
{ _MMIO(0x9888), 0x02504000 },
{ _MMIO(0x9888), 0x0e518000 },
{ _MMIO(0x9888), 0x00518000 },
{ _MMIO(0x9888), 0x02514000 },
{ _MMIO(0x9888), 0x0e521880 },
{ _MMIO(0x9888), 0x00521a80 },
{ _MMIO(0x9888), 0x02520033 },
{ _MMIO(0x9888), 0x0e534000 },
{ _MMIO(0x9888), 0x00534000 },
{ _MMIO(0x9888), 0x02531000 },
{ _MMIO(0x9888), 0x1190ff80 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900800 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900062 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900c00 },
{ _MMIO(0x9888), 0x43900003 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900040 },
};
static int
get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_tdl_1;
lens[n] = ARRAY_SIZE(mux_config_tdl_1);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_tdl_2[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x00800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
};
static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_tdl_2[] = {
{ _MMIO(0x9888), 0x12124d60 },
{ _MMIO(0x9888), 0x12322e60 },
{ _MMIO(0x9888), 0x12524d60 },
{ _MMIO(0x9888), 0x022f3000 },
{ _MMIO(0x9888), 0x0a4c0014 },
{ _MMIO(0x9888), 0x000d8000 },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x0c0fe000 },
{ _MMIO(0x9888), 0x0e0f0097 },
{ _MMIO(0x9888), 0x082c8000 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x002d8000 },
{ _MMIO(0x9888), 0x062d4000 },
{ _MMIO(0x9888), 0x0410c000 },
{ _MMIO(0x9888), 0x0411c000 },
{ _MMIO(0x9888), 0x04121fb7 },
{ _MMIO(0x9888), 0x00120000 },
{ _MMIO(0x9888), 0x04135000 },
{ _MMIO(0x9888), 0x00308000 },
{ _MMIO(0x9888), 0x06304000 },
{ _MMIO(0x9888), 0x00318000 },
{ _MMIO(0x9888), 0x06314000 },
{ _MMIO(0x9888), 0x00321b80 },
{ _MMIO(0x9888), 0x0632003f },
{ _MMIO(0x9888), 0x00334000 },
{ _MMIO(0x9888), 0x06331000 },
{ _MMIO(0x9888), 0x0250c000 },
{ _MMIO(0x9888), 0x0251c000 },
{ _MMIO(0x9888), 0x02521fb7 },
{ _MMIO(0x9888), 0x00520000 },
{ _MMIO(0x9888), 0x02535000 },
{ _MMIO(0x9888), 0x1190fc00 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900800 },
{ _MMIO(0x9888), 0x43900063 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900040 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_tdl_2;
lens[n] = ARRAY_SIZE(mux_config_tdl_2);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_compute_extra[] = {
};
static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
};
static const struct i915_oa_reg mux_config_compute_extra[] = {
{ _MMIO(0x9888), 0x121203e0 },
{ _MMIO(0x9888), 0x123203e0 },
{ _MMIO(0x9888), 0x125203e0 },
{ _MMIO(0x9888), 0x129203e0 },
{ _MMIO(0x9888), 0x12b203e0 },
{ _MMIO(0x9888), 0x12d203e0 },
{ _MMIO(0x9888), 0x024ec000 },
{ _MMIO(0x9888), 0x044ec000 },
{ _MMIO(0x9888), 0x064ec000 },
{ _MMIO(0x9888), 0x022f4000 },
{ _MMIO(0x9888), 0x084ca000 },
{ _MMIO(0x9888), 0x0a4c0042 },
{ _MMIO(0x9888), 0x000d8000 },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x0c0f5000 },
{ _MMIO(0x9888), 0x0e0f006d },
{ _MMIO(0x9888), 0x022c8000 },
{ _MMIO(0x9888), 0x042c8000 },
{ _MMIO(0x9888), 0x062c8000 },
{ _MMIO(0x9888), 0x0c2c8000 },
{ _MMIO(0x9888), 0x042d8000 },
{ _MMIO(0x9888), 0x06104000 },
{ _MMIO(0x9888), 0x06114000 },
{ _MMIO(0x9888), 0x06120033 },
{ _MMIO(0x9888), 0x00120000 },
{ _MMIO(0x9888), 0x06131000 },
{ _MMIO(0x9888), 0x04308000 },
{ _MMIO(0x9888), 0x04318000 },
{ _MMIO(0x9888), 0x04321980 },
{ _MMIO(0x9888), 0x00320000 },
{ _MMIO(0x9888), 0x04334000 },
{ _MMIO(0x9888), 0x04504000 },
{ _MMIO(0x9888), 0x04514000 },
{ _MMIO(0x9888), 0x04520033 },
{ _MMIO(0x9888), 0x00520000 },
{ _MMIO(0x9888), 0x04531000 },
{ _MMIO(0x9888), 0x00af8000 },
{ _MMIO(0x9888), 0x0acc0001 },
{ _MMIO(0x9888), 0x008d8000 },
{ _MMIO(0x9888), 0x028da000 },
{ _MMIO(0x9888), 0x0c8fb000 },
{ _MMIO(0x9888), 0x0e8f0001 },
{ _MMIO(0x9888), 0x06ac8000 },
{ _MMIO(0x9888), 0x02ad4000 },
{ _MMIO(0x9888), 0x02908000 },
{ _MMIO(0x9888), 0x02918000 },
{ _MMIO(0x9888), 0x02921980 },
{ _MMIO(0x9888), 0x00920000 },
{ _MMIO(0x9888), 0x02934000 },
{ _MMIO(0x9888), 0x02b04000 },
{ _MMIO(0x9888), 0x02b14000 },
{ _MMIO(0x9888), 0x02b20033 },
{ _MMIO(0x9888), 0x00b20000 },
{ _MMIO(0x9888), 0x02b31000 },
{ _MMIO(0x9888), 0x00d08000 },
{ _MMIO(0x9888), 0x00d18000 },
{ _MMIO(0x9888), 0x00d21980 },
{ _MMIO(0x9888), 0x00d34000 },
{ _MMIO(0x9888), 0x1190fc00 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900c00 },
{ _MMIO(0x9888), 0x43900402 },
{ _MMIO(0x9888), 0x53901550 },
{ _MMIO(0x9888), 0x45900080 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_extra;
lens[n] = ARRAY_SIZE(mux_config_compute_extra);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_vme_pipe[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x30800000 },
{ _MMIO(0x2770), 0x00100030 },
{ _MMIO(0x2774), 0x0000fff9 },
{ _MMIO(0x2778), 0x00000002 },
{ _MMIO(0x277c), 0x0000fffc },
{ _MMIO(0x2780), 0x00000002 },
{ _MMIO(0x2784), 0x0000fff3 },
{ _MMIO(0x2788), 0x00100180 },
{ _MMIO(0x278c), 0x0000ffcf },
{ _MMIO(0x2790), 0x00000002 },
{ _MMIO(0x2794), 0x0000ffcf },
{ _MMIO(0x2798), 0x00000002 },
{ _MMIO(0x279c), 0x0000ff3f },
};
static const struct i915_oa_reg flex_eu_config_vme_pipe[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00008003 },
};
static const struct i915_oa_reg mux_config_vme_pipe[] = {
{ _MMIO(0x9888), 0x141a5800 },
{ _MMIO(0x9888), 0x161a00c0 },
{ _MMIO(0x9888), 0x12180240 },
{ _MMIO(0x9888), 0x14180002 },
{ _MMIO(0x9888), 0x149a5800 },
{ _MMIO(0x9888), 0x169a00c0 },
{ _MMIO(0x9888), 0x12980240 },
{ _MMIO(0x9888), 0x14980002 },
{ _MMIO(0x9888), 0x1a4e3fc0 },
{ _MMIO(0x9888), 0x002f1000 },
{ _MMIO(0x9888), 0x022f8000 },
{ _MMIO(0x9888), 0x042f3000 },
{ _MMIO(0x9888), 0x004c4000 },
{ _MMIO(0x9888), 0x0a4c9500 },
{ _MMIO(0x9888), 0x0c4c002a },
{ _MMIO(0x9888), 0x000d2000 },
{ _MMIO(0x9888), 0x060d8000 },
{ _MMIO(0x9888), 0x080da000 },
{ _MMIO(0x9888), 0x0a0da000 },
{ _MMIO(0x9888), 0x0c0da000 },
{ _MMIO(0x9888), 0x0c0f0400 },
{ _MMIO(0x9888), 0x0e0f5500 },
{ _MMIO(0x9888), 0x100f0015 },
{ _MMIO(0x9888), 0x002c8000 },
{ _MMIO(0x9888), 0x0e2c8000 },
{ _MMIO(0x9888), 0x162caa00 },
{ _MMIO(0x9888), 0x182c000a },
{ _MMIO(0x9888), 0x04193000 },
{ _MMIO(0x9888), 0x081a28c1 },
{ _MMIO(0x9888), 0x001a0000 },
{ _MMIO(0x9888), 0x00133000 },
{ _MMIO(0x9888), 0x0613c000 },
{ _MMIO(0x9888), 0x0813f000 },
{ _MMIO(0x9888), 0x00172000 },
{ _MMIO(0x9888), 0x06178000 },
{ _MMIO(0x9888), 0x0817a000 },
{ _MMIO(0x9888), 0x00180037 },
{ _MMIO(0x9888), 0x06180940 },
{ _MMIO(0x9888), 0x08180000 },
{ _MMIO(0x9888), 0x02180000 },
{ _MMIO(0x9888), 0x04183000 },
{ _MMIO(0x9888), 0x04afc000 },
{ _MMIO(0x9888), 0x06af3000 },
{ _MMIO(0x9888), 0x0acc4000 },
{ _MMIO(0x9888), 0x0ccc0015 },
{ _MMIO(0x9888), 0x0a8da000 },
{ _MMIO(0x9888), 0x0c8da000 },
{ _MMIO(0x9888), 0x0e8f4000 },
{ _MMIO(0x9888), 0x108f0015 },
{ _MMIO(0x9888), 0x16aca000 },
{ _MMIO(0x9888), 0x18ac000a },
{ _MMIO(0x9888), 0x06993000 },
{ _MMIO(0x9888), 0x0c9a28c1 },
{ _MMIO(0x9888), 0x009a0000 },
{ _MMIO(0x9888), 0x0a93f000 },
{ _MMIO(0x9888), 0x0c93f000 },
{ _MMIO(0x9888), 0x0a97a000 },
{ _MMIO(0x9888), 0x0c97a000 },
{ _MMIO(0x9888), 0x0a980977 },
{ _MMIO(0x9888), 0x08980000 },
{ _MMIO(0x9888), 0x04980000 },
{ _MMIO(0x9888), 0x06983000 },
{ _MMIO(0x9888), 0x119000ff },
{ _MMIO(0x9888), 0x51900050 },
{ _MMIO(0x9888), 0x41900000 },
{ _MMIO(0x9888), 0x55900115 },
{ _MMIO(0x9888), 0x45900000 },
{ _MMIO(0x9888), 0x47900884 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900002 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_vme_pipe_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_vme_pipe;
lens[n] = ARRAY_SIZE(mux_config_vme_pipe);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_test_oa[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2770), 0x00000004 },
{ _MMIO(0x2774), 0x00000000 },
{ _MMIO(0x2778), 0x00000003 },
{ _MMIO(0x277c), 0x00000000 },
{ _MMIO(0x2780), 0x00000007 },
{ _MMIO(0x2784), 0x00000000 },
{ _MMIO(0x2788), 0x00100002 },
{ _MMIO(0x278c), 0x0000fff7 },
{ _MMIO(0x2790), 0x00100002 },
{ _MMIO(0x2794), 0x0000ffcf },
{ _MMIO(0x2798), 0x00100082 },
{ _MMIO(0x279c), 0x0000ffef },
{ _MMIO(0x27a0), 0x001000c2 },
{ _MMIO(0x27a4), 0x0000ffe7 },
{ _MMIO(0x27a8), 0x00100001 },
{ _MMIO(0x27ac), 0x0000ffe7 },
};
static const struct i915_oa_reg flex_eu_config_test_oa[] = {
};
static const struct i915_oa_reg mux_config_test_oa[] = {
{ _MMIO(0x9888), 0x11810000 },
{ _MMIO(0x9888), 0x07810013 },
{ _MMIO(0x9888), 0x1f810000 },
{ _MMIO(0x9888), 0x1d810000 },
{ _MMIO(0x9888), 0x1b930040 },
{ _MMIO(0x9888), 0x07e54000 },
{ _MMIO(0x9888), 0x1f908000 },
{ _MMIO(0x9888), 0x11900000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900000 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_test_oa_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_test_oa;
lens[n] = ARRAY_SIZE(mux_config_test_oa);
n++;
return n;
}
int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv) int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv)
{ {
dev_priv->perf.oa.n_mux_configs = 0; dev_priv->perf.oa.n_mux_configs = 0;
dev_priv->perf.oa.b_counter_regs = NULL; dev_priv->perf.oa.b_counter_regs = NULL;
dev_priv->perf.oa.b_counter_regs_len = 0; dev_priv->perf.oa.b_counter_regs_len = 0;
dev_priv->perf.oa.flex_regs = NULL; dev_priv->perf.oa.flex_regs = NULL;
dev_priv->perf.oa.flex_regs_len = 0; dev_priv->perf.oa.flex_regs_len = 0;
switch (dev_priv->perf.oa.metrics_set) {
case METRIC_SET_ID_RENDER_BASIC:
dev_priv->perf.oa.n_mux_configs =
get_render_basic_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_render_basic;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_render_basic);
dev_priv->perf.oa.flex_regs =
flex_eu_config_render_basic;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_render_basic);
return 0;
case METRIC_SET_ID_COMPUTE_BASIC:
dev_priv->perf.oa.n_mux_configs =
get_compute_basic_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_compute_basic;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_basic);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_basic;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_basic);
return 0;
case METRIC_SET_ID_RENDER_PIPE_PROFILE:
dev_priv->perf.oa.n_mux_configs =
get_render_pipe_profile_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_render_pipe_profile;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_render_pipe_profile);
dev_priv->perf.oa.flex_regs =
flex_eu_config_render_pipe_profile;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_render_pipe_profile);
return 0;
case METRIC_SET_ID_MEMORY_READS:
dev_priv->perf.oa.n_mux_configs =
get_memory_reads_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_memory_reads;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_memory_reads);
dev_priv->perf.oa.flex_regs =
flex_eu_config_memory_reads;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_memory_reads);
return 0;
case METRIC_SET_ID_MEMORY_WRITES:
dev_priv->perf.oa.n_mux_configs =
get_memory_writes_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_memory_writes;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_memory_writes);
dev_priv->perf.oa.flex_regs =
flex_eu_config_memory_writes;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_memory_writes);
return 0;
case METRIC_SET_ID_COMPUTE_EXTENDED:
dev_priv->perf.oa.n_mux_configs =
get_compute_extended_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_compute_extended;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_extended);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_extended;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_extended);
return 0;
case METRIC_SET_ID_COMPUTE_L3_CACHE:
dev_priv->perf.oa.n_mux_configs =
get_compute_l3_cache_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_compute_l3_cache;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_l3_cache);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_l3_cache;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_l3_cache);
return 0;
case METRIC_SET_ID_HDC_AND_SF:
dev_priv->perf.oa.n_mux_configs =
get_hdc_and_sf_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_hdc_and_sf;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_hdc_and_sf);
dev_priv->perf.oa.flex_regs =
flex_eu_config_hdc_and_sf;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_hdc_and_sf);
return 0;
case METRIC_SET_ID_L3_1:
dev_priv->perf.oa.n_mux_configs =
get_l3_1_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_l3_1;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_l3_1);
dev_priv->perf.oa.flex_regs =
flex_eu_config_l3_1;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_l3_1);
return 0;
case METRIC_SET_ID_L3_2:
dev_priv->perf.oa.n_mux_configs =
get_l3_2_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_l3_2;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_l3_2);
dev_priv->perf.oa.flex_regs =
flex_eu_config_l3_2;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_l3_2);
return 0;
case METRIC_SET_ID_L3_3:
dev_priv->perf.oa.n_mux_configs =
get_l3_3_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_l3_3;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_l3_3);
dev_priv->perf.oa.flex_regs =
flex_eu_config_l3_3;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_l3_3);
return 0;
case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
dev_priv->perf.oa.n_mux_configs =
get_rasterizer_and_pixel_backend_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_rasterizer_and_pixel_backend;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
dev_priv->perf.oa.flex_regs =
flex_eu_config_rasterizer_and_pixel_backend;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
return 0;
case METRIC_SET_ID_SAMPLER:
dev_priv->perf.oa.n_mux_configs =
get_sampler_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_sampler;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_sampler);
dev_priv->perf.oa.flex_regs =
flex_eu_config_sampler;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_sampler);
return 0;
case METRIC_SET_ID_TDL_1:
dev_priv->perf.oa.n_mux_configs =
get_tdl_1_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_tdl_1;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_tdl_1);
dev_priv->perf.oa.flex_regs =
flex_eu_config_tdl_1;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_tdl_1);
return 0;
case METRIC_SET_ID_TDL_2:
dev_priv->perf.oa.n_mux_configs =
get_tdl_2_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_tdl_2;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_tdl_2);
dev_priv->perf.oa.flex_regs =
flex_eu_config_tdl_2;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_tdl_2);
return 0;
case METRIC_SET_ID_COMPUTE_EXTRA:
dev_priv->perf.oa.n_mux_configs =
get_compute_extra_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_compute_extra;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_extra);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_extra;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_extra);
return 0;
case METRIC_SET_ID_VME_PIPE:
dev_priv->perf.oa.n_mux_configs =
get_vme_pipe_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_vme_pipe;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_vme_pipe);
dev_priv->perf.oa.flex_regs =
flex_eu_config_vme_pipe;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_vme_pipe);
return 0;
case METRIC_SET_ID_TEST_OA:
dev_priv->perf.oa.n_mux_configs =
get_test_oa_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_test_oa;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_test_oa);
dev_priv->perf.oa.flex_regs =
flex_eu_config_test_oa;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_test_oa);
return 0;
default:
return -ENODEV;
}
}
static ssize_t
show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
}
static struct device_attribute dev_attr_render_basic_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_render_basic_id,
.store = NULL,
};
static struct attribute *attrs_render_basic[] = {
&dev_attr_render_basic_id.attr,
NULL,
};
static struct attribute_group group_render_basic = {
.name = "4616d450-2393-4836-8146-53c5ed84d359",
.attrs = attrs_render_basic,
};
static ssize_t
show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
}
static struct device_attribute dev_attr_compute_basic_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_basic_id,
.store = NULL,
};
static struct attribute *attrs_compute_basic[] = {
&dev_attr_compute_basic_id.attr,
NULL,
};
static struct attribute_group group_compute_basic = {
.name = "4320492b-fd03-42ac-922f-dbe1ef3b7b58",
.attrs = attrs_compute_basic,
};
static ssize_t
show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
}
static struct device_attribute dev_attr_render_pipe_profile_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_render_pipe_profile_id,
.store = NULL,
};
static struct attribute *attrs_render_pipe_profile[] = {
&dev_attr_render_pipe_profile_id.attr,
NULL,
};
static struct attribute_group group_render_pipe_profile = {
.name = "bd2d9cae-b9ec-4f5b-9d2f-934bed398a2d",
.attrs = attrs_render_pipe_profile,
};
static ssize_t
show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
}
switch (dev_priv->perf.oa.metrics_set) { static struct device_attribute dev_attr_memory_reads_id = {
case METRIC_SET_ID_RENDER_BASIC: .attr = { .name = "id", .mode = 0444 },
dev_priv->perf.oa.n_mux_configs = .show = show_memory_reads_id,
get_render_basic_mux_config(dev_priv, .store = NULL,
dev_priv->perf.oa.mux_regs, };
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
/* EINVAL because *_register_sysfs already checked this static struct attribute *attrs_memory_reads[] = {
* and so it wouldn't have been advertised to userspace and &dev_attr_memory_reads_id.attr,
* so shouldn't have been requested NULL,
*/ };
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs = static struct attribute_group group_memory_reads = {
b_counter_config_render_basic; .name = "4ca0f3fe-7fd3-4924-98cb-1807d9879767",
dev_priv->perf.oa.b_counter_regs_len = .attrs = attrs_memory_reads,
ARRAY_SIZE(b_counter_config_render_basic); };
dev_priv->perf.oa.flex_regs = static ssize_t
flex_eu_config_render_basic; show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
dev_priv->perf.oa.flex_regs_len = {
ARRAY_SIZE(flex_eu_config_render_basic); return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
}
return 0; static struct device_attribute dev_attr_memory_writes_id = {
default: .attr = { .name = "id", .mode = 0444 },
return -ENODEV; .show = show_memory_writes_id,
} .store = NULL,
};
static struct attribute *attrs_memory_writes[] = {
&dev_attr_memory_writes_id.attr,
NULL,
};
static struct attribute_group group_memory_writes = {
.name = "a0c0172c-ee13-403d-99ff-2bdf6936cf14",
.attrs = attrs_memory_writes,
};
static ssize_t
show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
}
static struct device_attribute dev_attr_compute_extended_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_extended_id,
.store = NULL,
};
static struct attribute *attrs_compute_extended[] = {
&dev_attr_compute_extended_id.attr,
NULL,
};
static struct attribute_group group_compute_extended = {
.name = "52435e0b-f188-42ea-8680-21a56ee20dee",
.attrs = attrs_compute_extended,
};
static ssize_t
show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
} }
static struct device_attribute dev_attr_compute_l3_cache_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_l3_cache_id,
.store = NULL,
};
static struct attribute *attrs_compute_l3_cache[] = {
&dev_attr_compute_l3_cache_id.attr,
NULL,
};
static struct attribute_group group_compute_l3_cache = {
.name = "27076eeb-49f3-4fed-8423-c66506005c63",
.attrs = attrs_compute_l3_cache,
};
static ssize_t static ssize_t
show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
{ {
return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
} }
static struct device_attribute dev_attr_render_basic_id = { static struct device_attribute dev_attr_hdc_and_sf_id = {
.attr = { .name = "id", .mode = 0444 }, .attr = { .name = "id", .mode = 0444 },
.show = show_render_basic_id, .show = show_hdc_and_sf_id,
.store = NULL, .store = NULL,
}; };
static struct attribute *attrs_render_basic[] = { static struct attribute *attrs_hdc_and_sf[] = {
&dev_attr_render_basic_id.attr, &dev_attr_hdc_and_sf_id.attr,
NULL, NULL,
}; };
static struct attribute_group group_render_basic = { static struct attribute_group group_hdc_and_sf = {
.name = "4616d450-2393-4836-8146-53c5ed84d359", .name = "8071b409-c39a-4674-94d7-32962ecfb512",
.attrs = attrs_render_basic, .attrs = attrs_hdc_and_sf,
};
static ssize_t
show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
}
static struct device_attribute dev_attr_l3_1_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_l3_1_id,
.store = NULL,
};
static struct attribute *attrs_l3_1[] = {
&dev_attr_l3_1_id.attr,
NULL,
};
static struct attribute_group group_l3_1 = {
.name = "5e0b391e-9ea8-4901-b2ff-b64ff616c7ed",
.attrs = attrs_l3_1,
};
static ssize_t
show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
}
static struct device_attribute dev_attr_l3_2_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_l3_2_id,
.store = NULL,
};
static struct attribute *attrs_l3_2[] = {
&dev_attr_l3_2_id.attr,
NULL,
};
static struct attribute_group group_l3_2 = {
.name = "25dc828e-1d2d-426e-9546-a1d4233cdf16",
.attrs = attrs_l3_2,
};
static ssize_t
show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
}
static struct device_attribute dev_attr_l3_3_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_l3_3_id,
.store = NULL,
};
static struct attribute *attrs_l3_3[] = {
&dev_attr_l3_3_id.attr,
NULL,
};
static struct attribute_group group_l3_3 = {
.name = "3dba9405-2d7e-4d70-8199-e734e82fd6bf",
.attrs = attrs_l3_3,
};
static ssize_t
show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
}
static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_rasterizer_and_pixel_backend_id,
.store = NULL,
};
static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
&dev_attr_rasterizer_and_pixel_backend_id.attr,
NULL,
};
static struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "76935d7b-09c9-46bf-87f1-c18b4a86ebe5",
.attrs = attrs_rasterizer_and_pixel_backend,
};
static ssize_t
show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
}
static struct device_attribute dev_attr_sampler_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_sampler_id,
.store = NULL,
};
static struct attribute *attrs_sampler[] = {
&dev_attr_sampler_id.attr,
NULL,
};
static struct attribute_group group_sampler = {
.name = "1b34c0d6-4f4c-4d7b-833f-4aaf236d87a6",
.attrs = attrs_sampler,
};
static ssize_t
show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
}
static struct device_attribute dev_attr_tdl_1_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_tdl_1_id,
.store = NULL,
};
static struct attribute *attrs_tdl_1[] = {
&dev_attr_tdl_1_id.attr,
NULL,
};
static struct attribute_group group_tdl_1 = {
.name = "b375c985-9953-455b-bda2-b03f7594e9db",
.attrs = attrs_tdl_1,
};
static ssize_t
show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
}
static struct device_attribute dev_attr_tdl_2_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_tdl_2_id,
.store = NULL,
};
static struct attribute *attrs_tdl_2[] = {
&dev_attr_tdl_2_id.attr,
NULL,
};
static struct attribute_group group_tdl_2 = {
.name = "3e2be2bb-884a-49bb-82c5-2358e6bd5f2d",
.attrs = attrs_tdl_2,
};
static ssize_t
show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
}
static struct device_attribute dev_attr_compute_extra_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_extra_id,
.store = NULL,
};
static struct attribute *attrs_compute_extra[] = {
&dev_attr_compute_extra_id.attr,
NULL,
};
static struct attribute_group group_compute_extra = {
.name = "2d80a648-7b5a-4e92-bbe7-3b5c76f2e221",
.attrs = attrs_compute_extra,
};
static ssize_t
show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE);
}
static struct device_attribute dev_attr_vme_pipe_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_vme_pipe_id,
.store = NULL,
};
static struct attribute *attrs_vme_pipe[] = {
&dev_attr_vme_pipe_id.attr,
NULL,
};
static struct attribute_group group_vme_pipe = {
.name = "cfae9232-6ffc-42cc-a703-9790016925f0",
.attrs = attrs_vme_pipe,
};
static ssize_t
show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
}
static struct device_attribute dev_attr_test_oa_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_test_oa_id,
.store = NULL,
};
static struct attribute *attrs_test_oa[] = {
&dev_attr_test_oa_id.attr,
NULL,
};
static struct attribute_group group_test_oa = {
.name = "2b985803-d3c9-4629-8a4f-634bfecba0e8",
.attrs = attrs_test_oa,
}; };
int int
...@@ -231,9 +2851,145 @@ i915_perf_register_sysfs_sklgt3(struct drm_i915_private *dev_priv) ...@@ -231,9 +2851,145 @@ i915_perf_register_sysfs_sklgt3(struct drm_i915_private *dev_priv)
if (ret) if (ret)
goto error_render_basic; goto error_render_basic;
} }
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
if (ret)
goto error_compute_basic;
}
if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
if (ret)
goto error_render_pipe_profile;
}
if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
if (ret)
goto error_memory_reads;
}
if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
if (ret)
goto error_memory_writes;
}
if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
if (ret)
goto error_compute_extended;
}
if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
if (ret)
goto error_compute_l3_cache;
}
if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
if (ret)
goto error_hdc_and_sf;
}
if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
if (ret)
goto error_l3_1;
}
if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
if (ret)
goto error_l3_2;
}
if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
if (ret)
goto error_l3_3;
}
if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
if (ret)
goto error_rasterizer_and_pixel_backend;
}
if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
if (ret)
goto error_sampler;
}
if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
if (ret)
goto error_tdl_1;
}
if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
if (ret)
goto error_tdl_2;
}
if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
if (ret)
goto error_compute_extra;
}
if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
if (ret)
goto error_vme_pipe;
}
if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
if (ret)
goto error_test_oa;
}
return 0; return 0;
error_test_oa:
if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
error_vme_pipe:
if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
error_compute_extra:
if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
error_tdl_2:
if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
error_tdl_1:
if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
error_sampler:
if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
error_rasterizer_and_pixel_backend:
if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
error_l3_3:
if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
error_l3_2:
if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
error_l3_1:
if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
error_hdc_and_sf:
if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
error_compute_l3_cache:
if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
error_compute_extended:
if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
error_memory_writes:
if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
error_memory_reads:
if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
error_render_pipe_profile:
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
error_compute_basic:
if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
error_render_basic: error_render_basic:
return ret; return ret;
} }
...@@ -246,4 +3002,38 @@ i915_perf_unregister_sysfs_sklgt3(struct drm_i915_private *dev_priv) ...@@ -246,4 +3002,38 @@ i915_perf_unregister_sysfs_sklgt3(struct drm_i915_private *dev_priv)
if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
} }
drivers/gpu/drm/i915/i915_oa_sklgt4.c
View file @ fc599211
...@@ -33,9 +33,26 @@ ...@@ -33,9 +33,26 @@
enum metric_set_id { enum metric_set_id {
METRIC_SET_ID_RENDER_BASIC = 1, METRIC_SET_ID_RENDER_BASIC = 1,
METRIC_SET_ID_COMPUTE_BASIC,
METRIC_SET_ID_RENDER_PIPE_PROFILE,
METRIC_SET_ID_MEMORY_READS,
METRIC_SET_ID_MEMORY_WRITES,
METRIC_SET_ID_COMPUTE_EXTENDED,
METRIC_SET_ID_COMPUTE_L3_CACHE,
METRIC_SET_ID_HDC_AND_SF,
METRIC_SET_ID_L3_1,
METRIC_SET_ID_L3_2,
METRIC_SET_ID_L3_3,
METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
METRIC_SET_ID_SAMPLER,
METRIC_SET_ID_TDL_1,
METRIC_SET_ID_TDL_2,
METRIC_SET_ID_COMPUTE_EXTRA,
METRIC_SET_ID_VME_PIPE,
METRIC_SET_ID_TEST_OA,
}; };
int i915_oa_n_builtin_metric_sets_sklgt4 = 1; int i915_oa_n_builtin_metric_sets_sklgt4 = 18;
static const struct i915_oa_reg b_counter_config_render_basic[] = { static const struct i915_oa_reg b_counter_config_render_basic[] = {
{ _MMIO(0x2710), 0x00000000 }, { _MMIO(0x2710), 0x00000000 },
...@@ -168,66 +185,2712 @@ get_render_basic_mux_config(struct drm_i915_private *dev_priv, ...@@ -168,66 +185,2712 @@ get_render_basic_mux_config(struct drm_i915_private *dev_priv,
return n; return n;
} }
static const struct i915_oa_reg b_counter_config_compute_basic[] = {
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x00800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2740), 0x00000000 },
};
static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00000003 },
{ _MMIO(0xe658), 0x00002001 },
{ _MMIO(0xe758), 0x00778008 },
{ _MMIO(0xe45c), 0x00088078 },
{ _MMIO(0xe55c), 0x00808708 },
{ _MMIO(0xe65c), 0x00a08908 },
};
static const struct i915_oa_reg mux_config_compute_basic[] = {
{ _MMIO(0x9888), 0x104f00e0 },
{ _MMIO(0x9888), 0x124f1c00 },
{ _MMIO(0x9888), 0x106c00e0 },
{ _MMIO(0x9888), 0x37906800 },
{ _MMIO(0x9888), 0x3f900003 },
{ _MMIO(0x9888), 0x004e8000 },
{ _MMIO(0x9888), 0x1a4e0820 },
{ _MMIO(0x9888), 0x1c4e0002 },
{ _MMIO(0x9888), 0x064f0900 },
{ _MMIO(0x9888), 0x084f0032 },
{ _MMIO(0x9888), 0x0a4f1891 },
{ _MMIO(0x9888), 0x0c4f0e00 },
{ _MMIO(0x9888), 0x0e4f003c },
{ _MMIO(0x9888), 0x004f0d80 },
{ _MMIO(0x9888), 0x024f003b },
{ _MMIO(0x9888), 0x006c0002 },
{ _MMIO(0x9888), 0x086c0100 },
{ _MMIO(0x9888), 0x0c6c000c },
{ _MMIO(0x9888), 0x0e6c0b00 },
{ _MMIO(0x9888), 0x186c0000 },
{ _MMIO(0x9888), 0x1c6c0000 },
{ _MMIO(0x9888), 0x1e6c0000 },
{ _MMIO(0x9888), 0x001b4000 },
{ _MMIO(0x9888), 0x081b8000 },
{ _MMIO(0x9888), 0x0c1b4000 },
{ _MMIO(0x9888), 0x0e1b8000 },
{ _MMIO(0x9888), 0x101c8000 },
{ _MMIO(0x9888), 0x1a1c8000 },
{ _MMIO(0x9888), 0x1c1c0024 },
{ _MMIO(0x9888), 0x065b8000 },
{ _MMIO(0x9888), 0x085b4000 },
{ _MMIO(0x9888), 0x0a5bc000 },
{ _MMIO(0x9888), 0x0c5b8000 },
{ _MMIO(0x9888), 0x0e5b4000 },
{ _MMIO(0x9888), 0x005b8000 },
{ _MMIO(0x9888), 0x025b4000 },
{ _MMIO(0x9888), 0x1a5c6000 },
{ _MMIO(0x9888), 0x1c5c001b },
{ _MMIO(0x9888), 0x125c8000 },
{ _MMIO(0x9888), 0x145c8000 },
{ _MMIO(0x9888), 0x004c8000 },
{ _MMIO(0x9888), 0x0a4c2000 },
{ _MMIO(0x9888), 0x0c4c0208 },
{ _MMIO(0x9888), 0x000da000 },
{ _MMIO(0x9888), 0x060d8000 },
{ _MMIO(0x9888), 0x080da000 },
{ _MMIO(0x9888), 0x0a0da000 },
{ _MMIO(0x9888), 0x0c0da000 },
{ _MMIO(0x9888), 0x0e0da000 },
{ _MMIO(0x9888), 0x020d2000 },
{ _MMIO(0x9888), 0x0c0f5400 },
{ _MMIO(0x9888), 0x0e0f5500 },
{ _MMIO(0x9888), 0x100f0155 },
{ _MMIO(0x9888), 0x002c8000 },
{ _MMIO(0x9888), 0x0e2cc000 },
{ _MMIO(0x9888), 0x162cfb00 },
{ _MMIO(0x9888), 0x182c00be },
{ _MMIO(0x9888), 0x022cc000 },
{ _MMIO(0x9888), 0x042cc000 },
{ _MMIO(0x9888), 0x19900157 },
{ _MMIO(0x9888), 0x1b900158 },
{ _MMIO(0x9888), 0x1d900105 },
{ _MMIO(0x9888), 0x1f900103 },
{ _MMIO(0x9888), 0x35900000 },
{ _MMIO(0x9888), 0x11900fff },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900800 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x45900821 },
{ _MMIO(0x9888), 0x47900802 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900802 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900002 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x43900422 },
{ _MMIO(0x9888), 0x53905555 },
};
static int
get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_basic;
lens[n] = ARRAY_SIZE(mux_config_compute_basic);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2770), 0x0007ffea },
{ _MMIO(0x2774), 0x00007ffc },
{ _MMIO(0x2778), 0x0007affa },
{ _MMIO(0x277c), 0x0000f5fd },
{ _MMIO(0x2780), 0x00079ffa },
{ _MMIO(0x2784), 0x0000f3fb },
{ _MMIO(0x2788), 0x0007bf7a },
{ _MMIO(0x278c), 0x0000f7e7 },
{ _MMIO(0x2790), 0x0007fefa },
{ _MMIO(0x2794), 0x0000f7cf },
{ _MMIO(0x2798), 0x00077ffa },
{ _MMIO(0x279c), 0x0000efdf },
{ _MMIO(0x27a0), 0x0006fffa },
{ _MMIO(0x27a4), 0x0000cfbf },
{ _MMIO(0x27a8), 0x0003fffa },
{ _MMIO(0x27ac), 0x00005f7f },
};
static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00015014 },
{ _MMIO(0xe658), 0x00025024 },
{ _MMIO(0xe758), 0x00035034 },
{ _MMIO(0xe45c), 0x00045044 },
{ _MMIO(0xe55c), 0x00055054 },
{ _MMIO(0xe65c), 0x00065064 },
};
static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
{ _MMIO(0x9888), 0x0c0e001f },
{ _MMIO(0x9888), 0x0a0f0000 },
{ _MMIO(0x9888), 0x10116800 },
{ _MMIO(0x9888), 0x178a03e0 },
{ _MMIO(0x9888), 0x11824c00 },
{ _MMIO(0x9888), 0x11830020 },
{ _MMIO(0x9888), 0x13840020 },
{ _MMIO(0x9888), 0x11850019 },
{ _MMIO(0x9888), 0x11860007 },
{ _MMIO(0x9888), 0x01870c40 },
{ _MMIO(0x9888), 0x17880000 },
{ _MMIO(0x9888), 0x022f4000 },
{ _MMIO(0x9888), 0x0a4c0040 },
{ _MMIO(0x9888), 0x0c0d8000 },
{ _MMIO(0x9888), 0x040d4000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x020e5400 },
{ _MMIO(0x9888), 0x000e0000 },
{ _MMIO(0x9888), 0x080f0040 },
{ _MMIO(0x9888), 0x000f0000 },
{ _MMIO(0x9888), 0x100f0000 },
{ _MMIO(0x9888), 0x0e0f0040 },
{ _MMIO(0x9888), 0x0c2c8000 },
{ _MMIO(0x9888), 0x06104000 },
{ _MMIO(0x9888), 0x06110012 },
{ _MMIO(0x9888), 0x06131000 },
{ _MMIO(0x9888), 0x01898000 },
{ _MMIO(0x9888), 0x0d890100 },
{ _MMIO(0x9888), 0x03898000 },
{ _MMIO(0x9888), 0x09808000 },
{ _MMIO(0x9888), 0x0b808000 },
{ _MMIO(0x9888), 0x0380c000 },
{ _MMIO(0x9888), 0x0f8a0075 },
{ _MMIO(0x9888), 0x1d8a0000 },
{ _MMIO(0x9888), 0x118a8000 },
{ _MMIO(0x9888), 0x1b8a4000 },
{ _MMIO(0x9888), 0x138a8000 },
{ _MMIO(0x9888), 0x1d81a000 },
{ _MMIO(0x9888), 0x15818000 },
{ _MMIO(0x9888), 0x17818000 },
{ _MMIO(0x9888), 0x0b820030 },
{ _MMIO(0x9888), 0x07828000 },
{ _MMIO(0x9888), 0x0d824000 },
{ _MMIO(0x9888), 0x0f828000 },
{ _MMIO(0x9888), 0x05824000 },
{ _MMIO(0x9888), 0x0d830003 },
{ _MMIO(0x9888), 0x0583000c },
{ _MMIO(0x9888), 0x09830000 },
{ _MMIO(0x9888), 0x03838000 },
{ _MMIO(0x9888), 0x07838000 },
{ _MMIO(0x9888), 0x0b840980 },
{ _MMIO(0x9888), 0x03844d80 },
{ _MMIO(0x9888), 0x11840000 },
{ _MMIO(0x9888), 0x09848000 },
{ _MMIO(0x9888), 0x09850080 },
{ _MMIO(0x9888), 0x03850003 },
{ _MMIO(0x9888), 0x01850000 },
{ _MMIO(0x9888), 0x07860000 },
{ _MMIO(0x9888), 0x0f860400 },
{ _MMIO(0x9888), 0x09870032 },
{ _MMIO(0x9888), 0x01888052 },
{ _MMIO(0x9888), 0x11880000 },
{ _MMIO(0x9888), 0x09884000 },
{ _MMIO(0x9888), 0x1b931001 },
{ _MMIO(0x9888), 0x1d930001 },
{ _MMIO(0x9888), 0x19934000 },
{ _MMIO(0x9888), 0x1b958000 },
{ _MMIO(0x9888), 0x1d950094 },
{ _MMIO(0x9888), 0x19958000 },
{ _MMIO(0x9888), 0x09e58000 },
{ _MMIO(0x9888), 0x0be58000 },
{ _MMIO(0x9888), 0x03e5c000 },
{ _MMIO(0x9888), 0x0592c000 },
{ _MMIO(0x9888), 0x0b928000 },
{ _MMIO(0x9888), 0x0d924000 },
{ _MMIO(0x9888), 0x0f924000 },
{ _MMIO(0x9888), 0x11928000 },
{ _MMIO(0x9888), 0x1392c000 },
{ _MMIO(0x9888), 0x09924000 },
{ _MMIO(0x9888), 0x01985000 },
{ _MMIO(0x9888), 0x07988000 },
{ _MMIO(0x9888), 0x09981000 },
{ _MMIO(0x9888), 0x0b982000 },
{ _MMIO(0x9888), 0x0d982000 },
{ _MMIO(0x9888), 0x0f989000 },
{ _MMIO(0x9888), 0x05982000 },
{ _MMIO(0x9888), 0x13904000 },
{ _MMIO(0x9888), 0x21904000 },
{ _MMIO(0x9888), 0x23904000 },
{ _MMIO(0x9888), 0x25908000 },
{ _MMIO(0x9888), 0x27904000 },
{ _MMIO(0x9888), 0x29908000 },
{ _MMIO(0x9888), 0x2b904000 },
{ _MMIO(0x9888), 0x2f904000 },
{ _MMIO(0x9888), 0x31904000 },
{ _MMIO(0x9888), 0x15904000 },
{ _MMIO(0x9888), 0x17908000 },
{ _MMIO(0x9888), 0x19908000 },
{ _MMIO(0x9888), 0x1b904000 },
{ _MMIO(0x9888), 0x1190c080 },
{ _MMIO(0x9888), 0x51901110 },
{ _MMIO(0x9888), 0x41900440 },
{ _MMIO(0x9888), 0x55901111 },
{ _MMIO(0x9888), 0x45900400 },
{ _MMIO(0x9888), 0x47900c21 },
{ _MMIO(0x9888), 0x57901411 },
{ _MMIO(0x9888), 0x49900042 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900024 },
{ _MMIO(0x9888), 0x59900001 },
{ _MMIO(0x9888), 0x43900841 },
{ _MMIO(0x9888), 0x53900411 },
};
static int
get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_render_pipe_profile;
lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_memory_reads[] = {
{ _MMIO(0x272c), 0xffffffff },
{ _MMIO(0x2728), 0xffffffff },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x271c), 0xffffffff },
{ _MMIO(0x2718), 0xffffffff },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x274c), 0x86543210 },
{ _MMIO(0x2748), 0x86543210 },
{ _MMIO(0x2744), 0x00006667 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x275c), 0x86543210 },
{ _MMIO(0x2758), 0x86543210 },
{ _MMIO(0x2754), 0x00006465 },
{ _MMIO(0x2750), 0x00000000 },
{ _MMIO(0x2770), 0x0007f81a },
{ _MMIO(0x2774), 0x0000fe00 },
{ _MMIO(0x2778), 0x0007f82a },
{ _MMIO(0x277c), 0x0000fe00 },
{ _MMIO(0x2780), 0x0007f872 },
{ _MMIO(0x2784), 0x0000fe00 },
{ _MMIO(0x2788), 0x0007f8ba },
{ _MMIO(0x278c), 0x0000fe00 },
{ _MMIO(0x2790), 0x0007f87a },
{ _MMIO(0x2794), 0x0000fe00 },
{ _MMIO(0x2798), 0x0007f8ea },
{ _MMIO(0x279c), 0x0000fe00 },
{ _MMIO(0x27a0), 0x0007f8e2 },
{ _MMIO(0x27a4), 0x0000fe00 },
{ _MMIO(0x27a8), 0x0007f8f2 },
{ _MMIO(0x27ac), 0x0000fe00 },
};
static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00015014 },
{ _MMIO(0xe658), 0x00025024 },
{ _MMIO(0xe758), 0x00035034 },
{ _MMIO(0xe45c), 0x00045044 },
{ _MMIO(0xe55c), 0x00055054 },
{ _MMIO(0xe65c), 0x00065064 },
};
static const struct i915_oa_reg mux_config_memory_reads[] = {
{ _MMIO(0x9888), 0x11810c00 },
{ _MMIO(0x9888), 0x1381001a },
{ _MMIO(0x9888), 0x37906800 },
{ _MMIO(0x9888), 0x3f900064 },
{ _MMIO(0x9888), 0x03811300 },
{ _MMIO(0x9888), 0x05811b12 },
{ _MMIO(0x9888), 0x0781001a },
{ _MMIO(0x9888), 0x1f810000 },
{ _MMIO(0x9888), 0x17810000 },
{ _MMIO(0x9888), 0x19810000 },
{ _MMIO(0x9888), 0x1b810000 },
{ _MMIO(0x9888), 0x1d810000 },
{ _MMIO(0x9888), 0x1b930055 },
{ _MMIO(0x9888), 0x03e58000 },
{ _MMIO(0x9888), 0x05e5c000 },
{ _MMIO(0x9888), 0x07e54000 },
{ _MMIO(0x9888), 0x13900150 },
{ _MMIO(0x9888), 0x21900151 },
{ _MMIO(0x9888), 0x23900152 },
{ _MMIO(0x9888), 0x25900153 },
{ _MMIO(0x9888), 0x27900154 },
{ _MMIO(0x9888), 0x29900155 },
{ _MMIO(0x9888), 0x2b900156 },
{ _MMIO(0x9888), 0x2d900157 },
{ _MMIO(0x9888), 0x2f90015f },
{ _MMIO(0x9888), 0x31900105 },
{ _MMIO(0x9888), 0x15900103 },
{ _MMIO(0x9888), 0x17900101 },
{ _MMIO(0x9888), 0x35900000 },
{ _MMIO(0x9888), 0x19908000 },
{ _MMIO(0x9888), 0x1b908000 },
{ _MMIO(0x9888), 0x1d908000 },
{ _MMIO(0x9888), 0x1f908000 },
{ _MMIO(0x9888), 0x11900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900c60 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x45900c00 },
{ _MMIO(0x9888), 0x47900c63 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900c63 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900063 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x43900003 },
{ _MMIO(0x9888), 0x53900000 },
};
static int
get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_memory_reads;
lens[n] = ARRAY_SIZE(mux_config_memory_reads);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_memory_writes[] = {
{ _MMIO(0x272c), 0xffffffff },
{ _MMIO(0x2728), 0xffffffff },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x271c), 0xffffffff },
{ _MMIO(0x2718), 0xffffffff },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x274c), 0x86543210 },
{ _MMIO(0x2748), 0x86543210 },
{ _MMIO(0x2744), 0x00006667 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x275c), 0x86543210 },
{ _MMIO(0x2758), 0x86543210 },
{ _MMIO(0x2754), 0x00006465 },
{ _MMIO(0x2750), 0x00000000 },
{ _MMIO(0x2770), 0x0007f81a },
{ _MMIO(0x2774), 0x0000fe00 },
{ _MMIO(0x2778), 0x0007f82a },
{ _MMIO(0x277c), 0x0000fe00 },
{ _MMIO(0x2780), 0x0007f822 },
{ _MMIO(0x2784), 0x0000fe00 },
{ _MMIO(0x2788), 0x0007f8ba },
{ _MMIO(0x278c), 0x0000fe00 },
{ _MMIO(0x2790), 0x0007f87a },
{ _MMIO(0x2794), 0x0000fe00 },
{ _MMIO(0x2798), 0x0007f8ea },
{ _MMIO(0x279c), 0x0000fe00 },
{ _MMIO(0x27a0), 0x0007f8e2 },
{ _MMIO(0x27a4), 0x0000fe00 },
{ _MMIO(0x27a8), 0x0007f8f2 },
{ _MMIO(0x27ac), 0x0000fe00 },
};
static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00015014 },
{ _MMIO(0xe658), 0x00025024 },
{ _MMIO(0xe758), 0x00035034 },
{ _MMIO(0xe45c), 0x00045044 },
{ _MMIO(0xe55c), 0x00055054 },
{ _MMIO(0xe65c), 0x00065064 },
};
static const struct i915_oa_reg mux_config_memory_writes[] = {
{ _MMIO(0x9888), 0x11810c00 },
{ _MMIO(0x9888), 0x1381001a },
{ _MMIO(0x9888), 0x37906800 },
{ _MMIO(0x9888), 0x3f901000 },
{ _MMIO(0x9888), 0x03811300 },
{ _MMIO(0x9888), 0x05811b12 },
{ _MMIO(0x9888), 0x0781001a },
{ _MMIO(0x9888), 0x1f810000 },
{ _MMIO(0x9888), 0x17810000 },
{ _MMIO(0x9888), 0x19810000 },
{ _MMIO(0x9888), 0x1b810000 },
{ _MMIO(0x9888), 0x1d810000 },
{ _MMIO(0x9888), 0x1b930055 },
{ _MMIO(0x9888), 0x03e58000 },
{ _MMIO(0x9888), 0x05e5c000 },
{ _MMIO(0x9888), 0x07e54000 },
{ _MMIO(0x9888), 0x13900160 },
{ _MMIO(0x9888), 0x21900161 },
{ _MMIO(0x9888), 0x23900162 },
{ _MMIO(0x9888), 0x25900163 },
{ _MMIO(0x9888), 0x27900164 },
{ _MMIO(0x9888), 0x29900165 },
{ _MMIO(0x9888), 0x2b900166 },
{ _MMIO(0x9888), 0x2d900167 },
{ _MMIO(0x9888), 0x2f900150 },
{ _MMIO(0x9888), 0x31900105 },
{ _MMIO(0x9888), 0x15900103 },
{ _MMIO(0x9888), 0x17900101 },
{ _MMIO(0x9888), 0x35900000 },
{ _MMIO(0x9888), 0x19908000 },
{ _MMIO(0x9888), 0x1b908000 },
{ _MMIO(0x9888), 0x1d908000 },
{ _MMIO(0x9888), 0x1f908000 },
{ _MMIO(0x9888), 0x11900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900c60 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x45900c00 },
{ _MMIO(0x9888), 0x47900c63 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900c63 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900063 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x43900003 },
{ _MMIO(0x9888), 0x53900000 },
};
static int
get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_memory_writes;
lens[n] = ARRAY_SIZE(mux_config_memory_writes);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_compute_extended[] = {
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2770), 0x0007fc2a },
{ _MMIO(0x2774), 0x0000bf00 },
{ _MMIO(0x2778), 0x0007fc6a },
{ _MMIO(0x277c), 0x0000bf00 },
{ _MMIO(0x2780), 0x0007fc92 },
{ _MMIO(0x2784), 0x0000bf00 },
{ _MMIO(0x2788), 0x0007fca2 },
{ _MMIO(0x278c), 0x0000bf00 },
{ _MMIO(0x2790), 0x0007fc32 },
{ _MMIO(0x2794), 0x0000bf00 },
{ _MMIO(0x2798), 0x0007fc9a },
{ _MMIO(0x279c), 0x0000bf00 },
{ _MMIO(0x27a0), 0x0007fe6a },
{ _MMIO(0x27a4), 0x0000bf00 },
{ _MMIO(0x27a8), 0x0007fe7a },
{ _MMIO(0x27ac), 0x0000bf00 },
};
static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00000003 },
{ _MMIO(0xe658), 0x00002001 },
{ _MMIO(0xe758), 0x00778008 },
{ _MMIO(0xe45c), 0x00088078 },
{ _MMIO(0xe55c), 0x00808708 },
{ _MMIO(0xe65c), 0x00a08908 },
};
static const struct i915_oa_reg mux_config_compute_extended[] = {
{ _MMIO(0x9888), 0x106c00e0 },
{ _MMIO(0x9888), 0x141c8160 },
{ _MMIO(0x9888), 0x161c8015 },
{ _MMIO(0x9888), 0x181c0120 },
{ _MMIO(0x9888), 0x004e8000 },
{ _MMIO(0x9888), 0x0e4e8000 },
{ _MMIO(0x9888), 0x184e8000 },
{ _MMIO(0x9888), 0x1a4eaaa0 },
{ _MMIO(0x9888), 0x1c4e0002 },
{ _MMIO(0x9888), 0x024e8000 },
{ _MMIO(0x9888), 0x044e8000 },
{ _MMIO(0x9888), 0x064e8000 },
{ _MMIO(0x9888), 0x084e8000 },
{ _MMIO(0x9888), 0x0a4e8000 },
{ _MMIO(0x9888), 0x0e6c0b01 },
{ _MMIO(0x9888), 0x006c0200 },
{ _MMIO(0x9888), 0x026c000c },
{ _MMIO(0x9888), 0x1c6c0000 },
{ _MMIO(0x9888), 0x1e6c0000 },
{ _MMIO(0x9888), 0x1a6c0000 },
{ _MMIO(0x9888), 0x0e1bc000 },
{ _MMIO(0x9888), 0x001b8000 },
{ _MMIO(0x9888), 0x021bc000 },
{ _MMIO(0x9888), 0x001c0041 },
{ _MMIO(0x9888), 0x061c4200 },
{ _MMIO(0x9888), 0x081c4443 },
{ _MMIO(0x9888), 0x0a1c4645 },
{ _MMIO(0x9888), 0x0c1c7647 },
{ _MMIO(0x9888), 0x041c7357 },
{ _MMIO(0x9888), 0x1c1c0030 },
{ _MMIO(0x9888), 0x101c0000 },
{ _MMIO(0x9888), 0x1a1c0000 },
{ _MMIO(0x9888), 0x121c8000 },
{ _MMIO(0x9888), 0x004c8000 },
{ _MMIO(0x9888), 0x0a4caa2a },
{ _MMIO(0x9888), 0x0c4c02aa },
{ _MMIO(0x9888), 0x084ca000 },
{ _MMIO(0x9888), 0x000da000 },
{ _MMIO(0x9888), 0x060d8000 },
{ _MMIO(0x9888), 0x080da000 },
{ _MMIO(0x9888), 0x0a0da000 },
{ _MMIO(0x9888), 0x0c0da000 },
{ _MMIO(0x9888), 0x0e0da000 },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x0c0f5400 },
{ _MMIO(0x9888), 0x0e0f5515 },
{ _MMIO(0x9888), 0x100f0155 },
{ _MMIO(0x9888), 0x002c8000 },
{ _MMIO(0x9888), 0x0e2c8000 },
{ _MMIO(0x9888), 0x162caa00 },
{ _MMIO(0x9888), 0x182c00aa },
{ _MMIO(0x9888), 0x022c8000 },
{ _MMIO(0x9888), 0x042c8000 },
{ _MMIO(0x9888), 0x062c8000 },
{ _MMIO(0x9888), 0x082c8000 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x11907fff },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900040 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x45900802 },
{ _MMIO(0x9888), 0x47900842 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900842 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900000 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x43900800 },
{ _MMIO(0x9888), 0x53900000 },
};
static int
get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_extended;
lens[n] = ARRAY_SIZE(mux_config_compute_extended);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x30800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x30800000 },
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2770), 0x0007fffa },
{ _MMIO(0x2774), 0x0000fefe },
{ _MMIO(0x2778), 0x0007fffa },
{ _MMIO(0x277c), 0x0000fefd },
{ _MMIO(0x2790), 0x0007fffa },
{ _MMIO(0x2794), 0x0000fbef },
{ _MMIO(0x2798), 0x0007fffa },
{ _MMIO(0x279c), 0x0000fbdf },
};
static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00000003 },
{ _MMIO(0xe658), 0x00002001 },
{ _MMIO(0xe758), 0x00101100 },
{ _MMIO(0xe45c), 0x00201200 },
{ _MMIO(0xe55c), 0x00301300 },
{ _MMIO(0xe65c), 0x00401400 },
};
static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
{ _MMIO(0x9888), 0x166c0760 },
{ _MMIO(0x9888), 0x1593001e },
{ _MMIO(0x9888), 0x3f900003 },
{ _MMIO(0x9888), 0x004e8000 },
{ _MMIO(0x9888), 0x0e4e8000 },
{ _MMIO(0x9888), 0x184e8000 },
{ _MMIO(0x9888), 0x1a4e8020 },
{ _MMIO(0x9888), 0x1c4e0002 },
{ _MMIO(0x9888), 0x006c0051 },
{ _MMIO(0x9888), 0x066c5000 },
{ _MMIO(0x9888), 0x086c5c5d },
{ _MMIO(0x9888), 0x0e6c5e5f },
{ _MMIO(0x9888), 0x106c0000 },
{ _MMIO(0x9888), 0x186c0000 },
{ _MMIO(0x9888), 0x1c6c0000 },
{ _MMIO(0x9888), 0x1e6c0000 },
{ _MMIO(0x9888), 0x001b4000 },
{ _MMIO(0x9888), 0x061b8000 },
{ _MMIO(0x9888), 0x081bc000 },
{ _MMIO(0x9888), 0x0e1bc000 },
{ _MMIO(0x9888), 0x101c8000 },
{ _MMIO(0x9888), 0x1a1ce000 },
{ _MMIO(0x9888), 0x1c1c0030 },
{ _MMIO(0x9888), 0x004c8000 },
{ _MMIO(0x9888), 0x0a4c2a00 },
{ _MMIO(0x9888), 0x0c4c0280 },
{ _MMIO(0x9888), 0x000d2000 },
{ _MMIO(0x9888), 0x060d8000 },
{ _MMIO(0x9888), 0x080da000 },
{ _MMIO(0x9888), 0x0e0da000 },
{ _MMIO(0x9888), 0x0c0f0400 },
{ _MMIO(0x9888), 0x0e0f1500 },
{ _MMIO(0x9888), 0x100f0140 },
{ _MMIO(0x9888), 0x002c8000 },
{ _MMIO(0x9888), 0x0e2c8000 },
{ _MMIO(0x9888), 0x162c0a00 },
{ _MMIO(0x9888), 0x182c00a0 },
{ _MMIO(0x9888), 0x03933300 },
{ _MMIO(0x9888), 0x05930032 },
{ _MMIO(0x9888), 0x11930000 },
{ _MMIO(0x9888), 0x1b930000 },
{ _MMIO(0x9888), 0x1d900157 },
{ _MMIO(0x9888), 0x1f900158 },
{ _MMIO(0x9888), 0x35900000 },
{ _MMIO(0x9888), 0x19908000 },
{ _MMIO(0x9888), 0x1b908000 },
{ _MMIO(0x9888), 0x1190030f },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900000 },
{ _MMIO(0x9888), 0x55900000 },
{ _MMIO(0x9888), 0x45900021 },
{ _MMIO(0x9888), 0x47900000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x4b900000 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x53905555 },
{ _MMIO(0x9888), 0x43900000 },
};
static int
get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_l3_cache;
lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x10800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x00000002 },
{ _MMIO(0x2774), 0x0000fdff },
};
static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
{ _MMIO(0x9888), 0x104f0232 },
{ _MMIO(0x9888), 0x124f4640 },
{ _MMIO(0x9888), 0x106c0232 },
{ _MMIO(0x9888), 0x11834400 },
{ _MMIO(0x9888), 0x0a4e8000 },
{ _MMIO(0x9888), 0x0c4e8000 },
{ _MMIO(0x9888), 0x004f1880 },
{ _MMIO(0x9888), 0x024f08bb },
{ _MMIO(0x9888), 0x044f001b },
{ _MMIO(0x9888), 0x046c0100 },
{ _MMIO(0x9888), 0x066c000b },
{ _MMIO(0x9888), 0x1a6c0000 },
{ _MMIO(0x9888), 0x041b8000 },
{ _MMIO(0x9888), 0x061b4000 },
{ _MMIO(0x9888), 0x1a1c1800 },
{ _MMIO(0x9888), 0x005b8000 },
{ _MMIO(0x9888), 0x025bc000 },
{ _MMIO(0x9888), 0x045b4000 },
{ _MMIO(0x9888), 0x125c8000 },
{ _MMIO(0x9888), 0x145c8000 },
{ _MMIO(0x9888), 0x165c8000 },
{ _MMIO(0x9888), 0x185c8000 },
{ _MMIO(0x9888), 0x0a4c00a0 },
{ _MMIO(0x9888), 0x000d8000 },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x0c0f5000 },
{ _MMIO(0x9888), 0x0e0f0055 },
{ _MMIO(0x9888), 0x022cc000 },
{ _MMIO(0x9888), 0x042cc000 },
{ _MMIO(0x9888), 0x062cc000 },
{ _MMIO(0x9888), 0x082cc000 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x0c2c8000 },
{ _MMIO(0x9888), 0x0f828000 },
{ _MMIO(0x9888), 0x0f8305c0 },
{ _MMIO(0x9888), 0x09830000 },
{ _MMIO(0x9888), 0x07830000 },
{ _MMIO(0x9888), 0x1d950080 },
{ _MMIO(0x9888), 0x13928000 },
{ _MMIO(0x9888), 0x0f988000 },
{ _MMIO(0x9888), 0x31904000 },
{ _MMIO(0x9888), 0x1190fc00 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x59900001 },
{ _MMIO(0x9888), 0x4b900040 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900800 },
{ _MMIO(0x9888), 0x43900842 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900000 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_hdc_and_sf;
lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_l3_1[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2770), 0x00100070 },
{ _MMIO(0x2774), 0x0000fff1 },
{ _MMIO(0x2778), 0x00014002 },
{ _MMIO(0x277c), 0x0000c3ff },
{ _MMIO(0x2780), 0x00010002 },
{ _MMIO(0x2784), 0x0000c7ff },
{ _MMIO(0x2788), 0x00004002 },
{ _MMIO(0x278c), 0x0000d3ff },
{ _MMIO(0x2790), 0x00100700 },
{ _MMIO(0x2794), 0x0000ff1f },
{ _MMIO(0x2798), 0x00001402 },
{ _MMIO(0x279c), 0x0000fc3f },
{ _MMIO(0x27a0), 0x00001002 },
{ _MMIO(0x27a4), 0x0000fc7f },
{ _MMIO(0x27a8), 0x00000402 },
{ _MMIO(0x27ac), 0x0000fd3f },
};
static const struct i915_oa_reg flex_eu_config_l3_1[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_l3_1[] = {
{ _MMIO(0x9888), 0x126c7b40 },
{ _MMIO(0x9888), 0x166c0020 },
{ _MMIO(0x9888), 0x0a603444 },
{ _MMIO(0x9888), 0x0a613400 },
{ _MMIO(0x9888), 0x1a4ea800 },
{ _MMIO(0x9888), 0x1c4e0002 },
{ _MMIO(0x9888), 0x024e8000 },
{ _MMIO(0x9888), 0x044e8000 },
{ _MMIO(0x9888), 0x064e8000 },
{ _MMIO(0x9888), 0x084e8000 },
{ _MMIO(0x9888), 0x0a4e8000 },
{ _MMIO(0x9888), 0x064f4000 },
{ _MMIO(0x9888), 0x0c6c5327 },
{ _MMIO(0x9888), 0x0e6c5425 },
{ _MMIO(0x9888), 0x006c2a00 },
{ _MMIO(0x9888), 0x026c285b },
{ _MMIO(0x9888), 0x046c005c },
{ _MMIO(0x9888), 0x106c0000 },
{ _MMIO(0x9888), 0x1c6c0000 },
{ _MMIO(0x9888), 0x1e6c0000 },
{ _MMIO(0x9888), 0x1a6c0800 },
{ _MMIO(0x9888), 0x0c1bc000 },
{ _MMIO(0x9888), 0x0e1bc000 },
{ _MMIO(0x9888), 0x001b8000 },
{ _MMIO(0x9888), 0x021bc000 },
{ _MMIO(0x9888), 0x041bc000 },
{ _MMIO(0x9888), 0x1c1c003c },
{ _MMIO(0x9888), 0x121c8000 },
{ _MMIO(0x9888), 0x141c8000 },
{ _MMIO(0x9888), 0x161c8000 },
{ _MMIO(0x9888), 0x181c8000 },
{ _MMIO(0x9888), 0x1a1c0800 },
{ _MMIO(0x9888), 0x065b4000 },
{ _MMIO(0x9888), 0x1a5c1000 },
{ _MMIO(0x9888), 0x10600000 },
{ _MMIO(0x9888), 0x04600000 },
{ _MMIO(0x9888), 0x0c610044 },
{ _MMIO(0x9888), 0x10610000 },
{ _MMIO(0x9888), 0x06610000 },
{ _MMIO(0x9888), 0x0c4c02a8 },
{ _MMIO(0x9888), 0x084ca000 },
{ _MMIO(0x9888), 0x0a4c002a },
{ _MMIO(0x9888), 0x0c0da000 },
{ _MMIO(0x9888), 0x0e0da000 },
{ _MMIO(0x9888), 0x000d8000 },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x100f0154 },
{ _MMIO(0x9888), 0x0c0f5000 },
{ _MMIO(0x9888), 0x0e0f0055 },
{ _MMIO(0x9888), 0x182c00aa },
{ _MMIO(0x9888), 0x022c8000 },
{ _MMIO(0x9888), 0x042c8000 },
{ _MMIO(0x9888), 0x062c8000 },
{ _MMIO(0x9888), 0x082c8000 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x0c2cc000 },
{ _MMIO(0x9888), 0x1190ffc0 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900420 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900021 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900400 },
{ _MMIO(0x9888), 0x43900421 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900040 },
};
static int
get_l3_1_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_l3_1;
lens[n] = ARRAY_SIZE(mux_config_l3_1);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_l3_2[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x00100070 },
{ _MMIO(0x2774), 0x0000fff1 },
{ _MMIO(0x2778), 0x00028002 },
{ _MMIO(0x277c), 0x000087ff },
{ _MMIO(0x2780), 0x00020002 },
{ _MMIO(0x2784), 0x00008fff },
{ _MMIO(0x2788), 0x00008002 },
{ _MMIO(0x278c), 0x0000a7ff },
};
static const struct i915_oa_reg flex_eu_config_l3_2[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_l3_2[] = {
{ _MMIO(0x9888), 0x126c02e0 },
{ _MMIO(0x9888), 0x146c0001 },
{ _MMIO(0x9888), 0x0a623400 },
{ _MMIO(0x9888), 0x044e8000 },
{ _MMIO(0x9888), 0x064e8000 },
{ _MMIO(0x9888), 0x084e8000 },
{ _MMIO(0x9888), 0x0a4e8000 },
{ _MMIO(0x9888), 0x064f4000 },
{ _MMIO(0x9888), 0x026c3324 },
{ _MMIO(0x9888), 0x046c3422 },
{ _MMIO(0x9888), 0x106c0000 },
{ _MMIO(0x9888), 0x1a6c0000 },
{ _MMIO(0x9888), 0x021bc000 },
{ _MMIO(0x9888), 0x041bc000 },
{ _MMIO(0x9888), 0x141c8000 },
{ _MMIO(0x9888), 0x161c8000 },
{ _MMIO(0x9888), 0x181c8000 },
{ _MMIO(0x9888), 0x1a1c0800 },
{ _MMIO(0x9888), 0x065b4000 },
{ _MMIO(0x9888), 0x1a5c1000 },
{ _MMIO(0x9888), 0x06614000 },
{ _MMIO(0x9888), 0x0c620044 },
{ _MMIO(0x9888), 0x10620000 },
{ _MMIO(0x9888), 0x06620000 },
{ _MMIO(0x9888), 0x084c8000 },
{ _MMIO(0x9888), 0x0a4c002a },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x0c0f4000 },
{ _MMIO(0x9888), 0x0e0f0055 },
{ _MMIO(0x9888), 0x042c8000 },
{ _MMIO(0x9888), 0x062c8000 },
{ _MMIO(0x9888), 0x082c8000 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x0c2cc000 },
{ _MMIO(0x9888), 0x1190f800 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x43900000 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900000 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_l3_2_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_l3_2;
lens[n] = ARRAY_SIZE(mux_config_l3_2);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_l3_3[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x00100070 },
{ _MMIO(0x2774), 0x0000fff1 },
{ _MMIO(0x2778), 0x00028002 },
{ _MMIO(0x277c), 0x000087ff },
{ _MMIO(0x2780), 0x00020002 },
{ _MMIO(0x2784), 0x00008fff },
{ _MMIO(0x2788), 0x00008002 },
{ _MMIO(0x278c), 0x0000a7ff },
};
static const struct i915_oa_reg flex_eu_config_l3_3[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_l3_3[] = {
{ _MMIO(0x9888), 0x126c4e80 },
{ _MMIO(0x9888), 0x146c0000 },
{ _MMIO(0x9888), 0x0a633400 },
{ _MMIO(0x9888), 0x044e8000 },
{ _MMIO(0x9888), 0x064e8000 },
{ _MMIO(0x9888), 0x084e8000 },
{ _MMIO(0x9888), 0x0a4e8000 },
{ _MMIO(0x9888), 0x0c4e8000 },
{ _MMIO(0x9888), 0x026c3321 },
{ _MMIO(0x9888), 0x046c342f },
{ _MMIO(0x9888), 0x106c0000 },
{ _MMIO(0x9888), 0x1a6c2000 },
{ _MMIO(0x9888), 0x021bc000 },
{ _MMIO(0x9888), 0x041bc000 },
{ _MMIO(0x9888), 0x061b4000 },
{ _MMIO(0x9888), 0x141c8000 },
{ _MMIO(0x9888), 0x161c8000 },
{ _MMIO(0x9888), 0x181c8000 },
{ _MMIO(0x9888), 0x1a1c1800 },
{ _MMIO(0x9888), 0x06604000 },
{ _MMIO(0x9888), 0x0c630044 },
{ _MMIO(0x9888), 0x10630000 },
{ _MMIO(0x9888), 0x06630000 },
{ _MMIO(0x9888), 0x084c8000 },
{ _MMIO(0x9888), 0x0a4c00aa },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x0c0f4000 },
{ _MMIO(0x9888), 0x0e0f0055 },
{ _MMIO(0x9888), 0x042c8000 },
{ _MMIO(0x9888), 0x062c8000 },
{ _MMIO(0x9888), 0x082c8000 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x0c2c8000 },
{ _MMIO(0x9888), 0x1190f800 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x43900842 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900002 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_l3_3_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_l3_3;
lens[n] = ARRAY_SIZE(mux_config_l3_3);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x30800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x00000002 },
{ _MMIO(0x2774), 0x0000efff },
{ _MMIO(0x2778), 0x00006000 },
{ _MMIO(0x277c), 0x0000f3ff },
};
static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
{ _MMIO(0x9888), 0x102f3800 },
{ _MMIO(0x9888), 0x144d0500 },
{ _MMIO(0x9888), 0x120d03c0 },
{ _MMIO(0x9888), 0x140d03cf },
{ _MMIO(0x9888), 0x0c0f0004 },
{ _MMIO(0x9888), 0x0c4e4000 },
{ _MMIO(0x9888), 0x042f0480 },
{ _MMIO(0x9888), 0x082f0000 },
{ _MMIO(0x9888), 0x022f0000 },
{ _MMIO(0x9888), 0x0a4c0090 },
{ _MMIO(0x9888), 0x064d0027 },
{ _MMIO(0x9888), 0x004d0000 },
{ _MMIO(0x9888), 0x000d0d40 },
{ _MMIO(0x9888), 0x020d803f },
{ _MMIO(0x9888), 0x040d8023 },
{ _MMIO(0x9888), 0x100d0000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x020f0010 },
{ _MMIO(0x9888), 0x000f0000 },
{ _MMIO(0x9888), 0x0e0f0050 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x0c2c8000 },
{ _MMIO(0x9888), 0x1190fc00 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41901400 },
{ _MMIO(0x9888), 0x43901485 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900001 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_rasterizer_and_pixel_backend;
lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_sampler[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x70800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
{ _MMIO(0x2770), 0x0000c000 },
{ _MMIO(0x2774), 0x0000e7ff },
{ _MMIO(0x2778), 0x00003000 },
{ _MMIO(0x277c), 0x0000f9ff },
{ _MMIO(0x2780), 0x00000c00 },
{ _MMIO(0x2784), 0x0000fe7f },
};
static const struct i915_oa_reg flex_eu_config_sampler[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_sampler[] = {
{ _MMIO(0x9888), 0x14152c00 },
{ _MMIO(0x9888), 0x16150005 },
{ _MMIO(0x9888), 0x121600a0 },
{ _MMIO(0x9888), 0x14352c00 },
{ _MMIO(0x9888), 0x16350005 },
{ _MMIO(0x9888), 0x123600a0 },
{ _MMIO(0x9888), 0x14552c00 },
{ _MMIO(0x9888), 0x16550005 },
{ _MMIO(0x9888), 0x125600a0 },
{ _MMIO(0x9888), 0x062f6000 },
{ _MMIO(0x9888), 0x022f2000 },
{ _MMIO(0x9888), 0x0c4c0050 },
{ _MMIO(0x9888), 0x0a4c0010 },
{ _MMIO(0x9888), 0x0c0d8000 },
{ _MMIO(0x9888), 0x0e0da000 },
{ _MMIO(0x9888), 0x000d8000 },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x100f0350 },
{ _MMIO(0x9888), 0x0c0fb000 },
{ _MMIO(0x9888), 0x0e0f00da },
{ _MMIO(0x9888), 0x182c0028 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x022dc000 },
{ _MMIO(0x9888), 0x042d4000 },
{ _MMIO(0x9888), 0x0c138000 },
{ _MMIO(0x9888), 0x0e132000 },
{ _MMIO(0x9888), 0x0413c000 },
{ _MMIO(0x9888), 0x1c140018 },
{ _MMIO(0x9888), 0x0c157000 },
{ _MMIO(0x9888), 0x0e150078 },
{ _MMIO(0x9888), 0x10150000 },
{ _MMIO(0x9888), 0x04162180 },
{ _MMIO(0x9888), 0x02160000 },
{ _MMIO(0x9888), 0x04174000 },
{ _MMIO(0x9888), 0x0233a000 },
{ _MMIO(0x9888), 0x04333000 },
{ _MMIO(0x9888), 0x14348000 },
{ _MMIO(0x9888), 0x16348000 },
{ _MMIO(0x9888), 0x02357870 },
{ _MMIO(0x9888), 0x10350000 },
{ _MMIO(0x9888), 0x04360043 },
{ _MMIO(0x9888), 0x02360000 },
{ _MMIO(0x9888), 0x04371000 },
{ _MMIO(0x9888), 0x0e538000 },
{ _MMIO(0x9888), 0x00538000 },
{ _MMIO(0x9888), 0x06533000 },
{ _MMIO(0x9888), 0x1c540020 },
{ _MMIO(0x9888), 0x12548000 },
{ _MMIO(0x9888), 0x0e557000 },
{ _MMIO(0x9888), 0x00557800 },
{ _MMIO(0x9888), 0x10550000 },
{ _MMIO(0x9888), 0x06560043 },
{ _MMIO(0x9888), 0x02560000 },
{ _MMIO(0x9888), 0x06571000 },
{ _MMIO(0x9888), 0x1190ff80 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900060 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900c00 },
{ _MMIO(0x9888), 0x43900842 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900060 },
};
static int
get_sampler_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_sampler;
lens[n] = ARRAY_SIZE(mux_config_sampler);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_tdl_1[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x30800000 },
{ _MMIO(0x2770), 0x00000002 },
{ _MMIO(0x2774), 0x00007fff },
{ _MMIO(0x2778), 0x00000000 },
{ _MMIO(0x277c), 0x00009fff },
{ _MMIO(0x2780), 0x00000002 },
{ _MMIO(0x2784), 0x0000efff },
{ _MMIO(0x2788), 0x00000000 },
{ _MMIO(0x278c), 0x0000f3ff },
{ _MMIO(0x2790), 0x00000002 },
{ _MMIO(0x2794), 0x0000fdff },
{ _MMIO(0x2798), 0x00000000 },
{ _MMIO(0x279c), 0x0000fe7f },
};
static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_tdl_1[] = {
{ _MMIO(0x9888), 0x12120000 },
{ _MMIO(0x9888), 0x12320000 },
{ _MMIO(0x9888), 0x12520000 },
{ _MMIO(0x9888), 0x002f8000 },
{ _MMIO(0x9888), 0x022f3000 },
{ _MMIO(0x9888), 0x0a4c0015 },
{ _MMIO(0x9888), 0x0c0d8000 },
{ _MMIO(0x9888), 0x0e0da000 },
{ _MMIO(0x9888), 0x000d8000 },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x100f03a0 },
{ _MMIO(0x9888), 0x0c0ff000 },
{ _MMIO(0x9888), 0x0e0f0095 },
{ _MMIO(0x9888), 0x062c8000 },
{ _MMIO(0x9888), 0x082c8000 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x0c2d8000 },
{ _MMIO(0x9888), 0x0e2d4000 },
{ _MMIO(0x9888), 0x062d4000 },
{ _MMIO(0x9888), 0x02108000 },
{ _MMIO(0x9888), 0x0410c000 },
{ _MMIO(0x9888), 0x02118000 },
{ _MMIO(0x9888), 0x0411c000 },
{ _MMIO(0x9888), 0x02121880 },
{ _MMIO(0x9888), 0x041219b5 },
{ _MMIO(0x9888), 0x00120000 },
{ _MMIO(0x9888), 0x02134000 },
{ _MMIO(0x9888), 0x04135000 },
{ _MMIO(0x9888), 0x0c308000 },
{ _MMIO(0x9888), 0x0e304000 },
{ _MMIO(0x9888), 0x06304000 },
{ _MMIO(0x9888), 0x0c318000 },
{ _MMIO(0x9888), 0x0e314000 },
{ _MMIO(0x9888), 0x06314000 },
{ _MMIO(0x9888), 0x0c321a80 },
{ _MMIO(0x9888), 0x0e320033 },
{ _MMIO(0x9888), 0x06320031 },
{ _MMIO(0x9888), 0x00320000 },
{ _MMIO(0x9888), 0x0c334000 },
{ _MMIO(0x9888), 0x0e331000 },
{ _MMIO(0x9888), 0x06331000 },
{ _MMIO(0x9888), 0x0e508000 },
{ _MMIO(0x9888), 0x00508000 },
{ _MMIO(0x9888), 0x02504000 },
{ _MMIO(0x9888), 0x0e518000 },
{ _MMIO(0x9888), 0x00518000 },
{ _MMIO(0x9888), 0x02514000 },
{ _MMIO(0x9888), 0x0e521880 },
{ _MMIO(0x9888), 0x00521a80 },
{ _MMIO(0x9888), 0x02520033 },
{ _MMIO(0x9888), 0x0e534000 },
{ _MMIO(0x9888), 0x00534000 },
{ _MMIO(0x9888), 0x02531000 },
{ _MMIO(0x9888), 0x1190ff80 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900800 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900062 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900c00 },
{ _MMIO(0x9888), 0x43900003 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900040 },
};
static int
get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_tdl_1;
lens[n] = ARRAY_SIZE(mux_config_tdl_1);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_tdl_2[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x00800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
};
static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_tdl_2[] = {
{ _MMIO(0x9888), 0x12124d60 },
{ _MMIO(0x9888), 0x12322e60 },
{ _MMIO(0x9888), 0x12524d60 },
{ _MMIO(0x9888), 0x022f3000 },
{ _MMIO(0x9888), 0x0a4c0014 },
{ _MMIO(0x9888), 0x000d8000 },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x0c0fe000 },
{ _MMIO(0x9888), 0x0e0f0097 },
{ _MMIO(0x9888), 0x082c8000 },
{ _MMIO(0x9888), 0x0a2c8000 },
{ _MMIO(0x9888), 0x002d8000 },
{ _MMIO(0x9888), 0x062d4000 },
{ _MMIO(0x9888), 0x0410c000 },
{ _MMIO(0x9888), 0x0411c000 },
{ _MMIO(0x9888), 0x04121fb7 },
{ _MMIO(0x9888), 0x00120000 },
{ _MMIO(0x9888), 0x04135000 },
{ _MMIO(0x9888), 0x00308000 },
{ _MMIO(0x9888), 0x06304000 },
{ _MMIO(0x9888), 0x00318000 },
{ _MMIO(0x9888), 0x06314000 },
{ _MMIO(0x9888), 0x00321b80 },
{ _MMIO(0x9888), 0x0632003f },
{ _MMIO(0x9888), 0x00334000 },
{ _MMIO(0x9888), 0x06331000 },
{ _MMIO(0x9888), 0x0250c000 },
{ _MMIO(0x9888), 0x0251c000 },
{ _MMIO(0x9888), 0x02521fb7 },
{ _MMIO(0x9888), 0x00520000 },
{ _MMIO(0x9888), 0x02535000 },
{ _MMIO(0x9888), 0x1190fc00 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x51900000 },
{ _MMIO(0x9888), 0x41900800 },
{ _MMIO(0x9888), 0x43900063 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900040 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_tdl_2;
lens[n] = ARRAY_SIZE(mux_config_tdl_2);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_compute_extra[] = {
};
static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
};
static const struct i915_oa_reg mux_config_compute_extra[] = {
{ _MMIO(0x9888), 0x121203e0 },
{ _MMIO(0x9888), 0x123203e0 },
{ _MMIO(0x9888), 0x125203e0 },
{ _MMIO(0x9888), 0x129203e0 },
{ _MMIO(0x9888), 0x12b203e0 },
{ _MMIO(0x9888), 0x12d203e0 },
{ _MMIO(0x9888), 0x131203e0 },
{ _MMIO(0x9888), 0x133203e0 },
{ _MMIO(0x9888), 0x135203e0 },
{ _MMIO(0x9888), 0x1a4ef000 },
{ _MMIO(0x9888), 0x1c4e0003 },
{ _MMIO(0x9888), 0x024ec000 },
{ _MMIO(0x9888), 0x044ec000 },
{ _MMIO(0x9888), 0x064ec000 },
{ _MMIO(0x9888), 0x022f4000 },
{ _MMIO(0x9888), 0x0c4c02a0 },
{ _MMIO(0x9888), 0x084ca000 },
{ _MMIO(0x9888), 0x0a4c0042 },
{ _MMIO(0x9888), 0x0c0d8000 },
{ _MMIO(0x9888), 0x0e0da000 },
{ _MMIO(0x9888), 0x000d8000 },
{ _MMIO(0x9888), 0x020da000 },
{ _MMIO(0x9888), 0x040da000 },
{ _MMIO(0x9888), 0x060d2000 },
{ _MMIO(0x9888), 0x100f0150 },
{ _MMIO(0x9888), 0x0c0f5000 },
{ _MMIO(0x9888), 0x0e0f006d },
{ _MMIO(0x9888), 0x182c00a8 },
{ _MMIO(0x9888), 0x022c8000 },
{ _MMIO(0x9888), 0x042c8000 },
{ _MMIO(0x9888), 0x062c8000 },
{ _MMIO(0x9888), 0x0c2c8000 },
{ _MMIO(0x9888), 0x042d8000 },
{ _MMIO(0x9888), 0x06104000 },
{ _MMIO(0x9888), 0x06114000 },
{ _MMIO(0x9888), 0x06120033 },
{ _MMIO(0x9888), 0x00120000 },
{ _MMIO(0x9888), 0x06131000 },
{ _MMIO(0x9888), 0x04308000 },
{ _MMIO(0x9888), 0x04318000 },
{ _MMIO(0x9888), 0x04321980 },
{ _MMIO(0x9888), 0x00320000 },
{ _MMIO(0x9888), 0x04334000 },
{ _MMIO(0x9888), 0x04504000 },
{ _MMIO(0x9888), 0x04514000 },
{ _MMIO(0x9888), 0x04520033 },
{ _MMIO(0x9888), 0x00520000 },
{ _MMIO(0x9888), 0x04531000 },
{ _MMIO(0x9888), 0x1acef000 },
{ _MMIO(0x9888), 0x1cce0003 },
{ _MMIO(0x9888), 0x00af8000 },
{ _MMIO(0x9888), 0x0ccc02a0 },
{ _MMIO(0x9888), 0x0acc0001 },
{ _MMIO(0x9888), 0x0c8d8000 },
{ _MMIO(0x9888), 0x0e8da000 },
{ _MMIO(0x9888), 0x008d8000 },
{ _MMIO(0x9888), 0x028da000 },
{ _MMIO(0x9888), 0x108f0150 },
{ _MMIO(0x9888), 0x0c8fb000 },
{ _MMIO(0x9888), 0x0e8f0001 },
{ _MMIO(0x9888), 0x18ac00a8 },
{ _MMIO(0x9888), 0x06ac8000 },
{ _MMIO(0x9888), 0x02ad4000 },
{ _MMIO(0x9888), 0x02908000 },
{ _MMIO(0x9888), 0x02918000 },
{ _MMIO(0x9888), 0x02921980 },
{ _MMIO(0x9888), 0x00920000 },
{ _MMIO(0x9888), 0x02934000 },
{ _MMIO(0x9888), 0x02b04000 },
{ _MMIO(0x9888), 0x02b14000 },
{ _MMIO(0x9888), 0x02b20033 },
{ _MMIO(0x9888), 0x00b20000 },
{ _MMIO(0x9888), 0x02b31000 },
{ _MMIO(0x9888), 0x00d08000 },
{ _MMIO(0x9888), 0x00d18000 },
{ _MMIO(0x9888), 0x00d21980 },
{ _MMIO(0x9888), 0x00d34000 },
{ _MMIO(0x9888), 0x072f8000 },
{ _MMIO(0x9888), 0x0d4c0100 },
{ _MMIO(0x9888), 0x0d0d8000 },
{ _MMIO(0x9888), 0x0f0da000 },
{ _MMIO(0x9888), 0x110f01b0 },
{ _MMIO(0x9888), 0x192c0080 },
{ _MMIO(0x9888), 0x0f2d4000 },
{ _MMIO(0x9888), 0x0f108000 },
{ _MMIO(0x9888), 0x0f118000 },
{ _MMIO(0x9888), 0x0f121980 },
{ _MMIO(0x9888), 0x01120000 },
{ _MMIO(0x9888), 0x0f134000 },
{ _MMIO(0x9888), 0x0f304000 },
{ _MMIO(0x9888), 0x0f314000 },
{ _MMIO(0x9888), 0x0f320033 },
{ _MMIO(0x9888), 0x01320000 },
{ _MMIO(0x9888), 0x0f331000 },
{ _MMIO(0x9888), 0x0d508000 },
{ _MMIO(0x9888), 0x0d518000 },
{ _MMIO(0x9888), 0x0d521980 },
{ _MMIO(0x9888), 0x01520000 },
{ _MMIO(0x9888), 0x0d534000 },
{ _MMIO(0x9888), 0x1190ff80 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900c00 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
{ _MMIO(0x9888), 0x4b900002 },
{ _MMIO(0x9888), 0x59900000 },
{ _MMIO(0x9888), 0x51901100 },
{ _MMIO(0x9888), 0x41901000 },
{ _MMIO(0x9888), 0x43901423 },
{ _MMIO(0x9888), 0x53903331 },
{ _MMIO(0x9888), 0x45900044 },
};
static int
get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_compute_extra;
lens[n] = ARRAY_SIZE(mux_config_compute_extra);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_vme_pipe[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x30800000 },
{ _MMIO(0x2770), 0x00100030 },
{ _MMIO(0x2774), 0x0000fff9 },
{ _MMIO(0x2778), 0x00000002 },
{ _MMIO(0x277c), 0x0000fffc },
{ _MMIO(0x2780), 0x00000002 },
{ _MMIO(0x2784), 0x0000fff3 },
{ _MMIO(0x2788), 0x00100180 },
{ _MMIO(0x278c), 0x0000ffcf },
{ _MMIO(0x2790), 0x00000002 },
{ _MMIO(0x2794), 0x0000ffcf },
{ _MMIO(0x2798), 0x00000002 },
{ _MMIO(0x279c), 0x0000ff3f },
};
static const struct i915_oa_reg flex_eu_config_vme_pipe[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00008003 },
};
static const struct i915_oa_reg mux_config_vme_pipe[] = {
{ _MMIO(0x9888), 0x141a5800 },
{ _MMIO(0x9888), 0x161a00c0 },
{ _MMIO(0x9888), 0x12180240 },
{ _MMIO(0x9888), 0x14180002 },
{ _MMIO(0x9888), 0x149a5800 },
{ _MMIO(0x9888), 0x169a00c0 },
{ _MMIO(0x9888), 0x12980240 },
{ _MMIO(0x9888), 0x14980002 },
{ _MMIO(0x9888), 0x1a4e3fc0 },
{ _MMIO(0x9888), 0x002f1000 },
{ _MMIO(0x9888), 0x022f8000 },
{ _MMIO(0x9888), 0x042f3000 },
{ _MMIO(0x9888), 0x004c4000 },
{ _MMIO(0x9888), 0x0a4c9500 },
{ _MMIO(0x9888), 0x0c4c002a },
{ _MMIO(0x9888), 0x000d2000 },
{ _MMIO(0x9888), 0x060d8000 },
{ _MMIO(0x9888), 0x080da000 },
{ _MMIO(0x9888), 0x0a0da000 },
{ _MMIO(0x9888), 0x0c0da000 },
{ _MMIO(0x9888), 0x0c0f0400 },
{ _MMIO(0x9888), 0x0e0f5500 },
{ _MMIO(0x9888), 0x100f0015 },
{ _MMIO(0x9888), 0x002c8000 },
{ _MMIO(0x9888), 0x0e2c8000 },
{ _MMIO(0x9888), 0x162caa00 },
{ _MMIO(0x9888), 0x182c000a },
{ _MMIO(0x9888), 0x04193000 },
{ _MMIO(0x9888), 0x081a28c1 },
{ _MMIO(0x9888), 0x001a0000 },
{ _MMIO(0x9888), 0x00133000 },
{ _MMIO(0x9888), 0x0613c000 },
{ _MMIO(0x9888), 0x0813f000 },
{ _MMIO(0x9888), 0x00172000 },
{ _MMIO(0x9888), 0x06178000 },
{ _MMIO(0x9888), 0x0817a000 },
{ _MMIO(0x9888), 0x00180037 },
{ _MMIO(0x9888), 0x06180940 },
{ _MMIO(0x9888), 0x08180000 },
{ _MMIO(0x9888), 0x02180000 },
{ _MMIO(0x9888), 0x04183000 },
{ _MMIO(0x9888), 0x04afc000 },
{ _MMIO(0x9888), 0x06af3000 },
{ _MMIO(0x9888), 0x0acc4000 },
{ _MMIO(0x9888), 0x0ccc0015 },
{ _MMIO(0x9888), 0x0a8da000 },
{ _MMIO(0x9888), 0x0c8da000 },
{ _MMIO(0x9888), 0x0e8f4000 },
{ _MMIO(0x9888), 0x108f0015 },
{ _MMIO(0x9888), 0x16aca000 },
{ _MMIO(0x9888), 0x18ac000a },
{ _MMIO(0x9888), 0x06993000 },
{ _MMIO(0x9888), 0x0c9a28c1 },
{ _MMIO(0x9888), 0x009a0000 },
{ _MMIO(0x9888), 0x0a93f000 },
{ _MMIO(0x9888), 0x0c93f000 },
{ _MMIO(0x9888), 0x0a97a000 },
{ _MMIO(0x9888), 0x0c97a000 },
{ _MMIO(0x9888), 0x0a980977 },
{ _MMIO(0x9888), 0x08980000 },
{ _MMIO(0x9888), 0x04980000 },
{ _MMIO(0x9888), 0x06983000 },
{ _MMIO(0x9888), 0x119000ff },
{ _MMIO(0x9888), 0x51900010 },
{ _MMIO(0x9888), 0x41900060 },
{ _MMIO(0x9888), 0x55900111 },
{ _MMIO(0x9888), 0x45900c00 },
{ _MMIO(0x9888), 0x47900821 },
{ _MMIO(0x9888), 0x57900000 },
{ _MMIO(0x9888), 0x49900002 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_vme_pipe_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_vme_pipe;
lens[n] = ARRAY_SIZE(mux_config_vme_pipe);
n++;
return n;
}
static const struct i915_oa_reg b_counter_config_test_oa[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2744), 0x00800000 },
{ _MMIO(0x2714), 0xf0800000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2724), 0xf0800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2770), 0x00000004 },
{ _MMIO(0x2774), 0x00000000 },
{ _MMIO(0x2778), 0x00000003 },
{ _MMIO(0x277c), 0x00000000 },
{ _MMIO(0x2780), 0x00000007 },
{ _MMIO(0x2784), 0x00000000 },
{ _MMIO(0x2788), 0x00100002 },
{ _MMIO(0x278c), 0x0000fff7 },
{ _MMIO(0x2790), 0x00100002 },
{ _MMIO(0x2794), 0x0000ffcf },
{ _MMIO(0x2798), 0x00100082 },
{ _MMIO(0x279c), 0x0000ffef },
{ _MMIO(0x27a0), 0x001000c2 },
{ _MMIO(0x27a4), 0x0000ffe7 },
{ _MMIO(0x27a8), 0x00100001 },
{ _MMIO(0x27ac), 0x0000ffe7 },
};
static const struct i915_oa_reg flex_eu_config_test_oa[] = {
};
static const struct i915_oa_reg mux_config_test_oa[] = {
{ _MMIO(0x9888), 0x11810000 },
{ _MMIO(0x9888), 0x07810013 },
{ _MMIO(0x9888), 0x1f810000 },
{ _MMIO(0x9888), 0x1d810000 },
{ _MMIO(0x9888), 0x1b930040 },
{ _MMIO(0x9888), 0x07e54000 },
{ _MMIO(0x9888), 0x1f908000 },
{ _MMIO(0x9888), 0x11900000 },
{ _MMIO(0x9888), 0x37900000 },
{ _MMIO(0x9888), 0x53900000 },
{ _MMIO(0x9888), 0x45900000 },
{ _MMIO(0x9888), 0x33900000 },
};
static int
get_test_oa_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_test_oa;
lens[n] = ARRAY_SIZE(mux_config_test_oa);
n++;
return n;
}
int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv) int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv)
{ {
dev_priv->perf.oa.n_mux_configs = 0; dev_priv->perf.oa.n_mux_configs = 0;
dev_priv->perf.oa.b_counter_regs = NULL; dev_priv->perf.oa.b_counter_regs = NULL;
dev_priv->perf.oa.b_counter_regs_len = 0; dev_priv->perf.oa.b_counter_regs_len = 0;
dev_priv->perf.oa.flex_regs = NULL; dev_priv->perf.oa.flex_regs = NULL;
dev_priv->perf.oa.flex_regs_len = 0; dev_priv->perf.oa.flex_regs_len = 0;
switch (dev_priv->perf.oa.metrics_set) {
case METRIC_SET_ID_RENDER_BASIC:
dev_priv->perf.oa.n_mux_configs =
get_render_basic_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_render_basic;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_render_basic);
dev_priv->perf.oa.flex_regs =
flex_eu_config_render_basic;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_render_basic);
return 0;
case METRIC_SET_ID_COMPUTE_BASIC:
dev_priv->perf.oa.n_mux_configs =
get_compute_basic_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_compute_basic;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_basic);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_basic;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_basic);
return 0;
case METRIC_SET_ID_RENDER_PIPE_PROFILE:
dev_priv->perf.oa.n_mux_configs =
get_render_pipe_profile_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_render_pipe_profile;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_render_pipe_profile);
dev_priv->perf.oa.flex_regs =
flex_eu_config_render_pipe_profile;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_render_pipe_profile);
return 0;
case METRIC_SET_ID_MEMORY_READS:
dev_priv->perf.oa.n_mux_configs =
get_memory_reads_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_memory_reads;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_memory_reads);
dev_priv->perf.oa.flex_regs =
flex_eu_config_memory_reads;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_memory_reads);
return 0;
case METRIC_SET_ID_MEMORY_WRITES:
dev_priv->perf.oa.n_mux_configs =
get_memory_writes_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_memory_writes;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_memory_writes);
dev_priv->perf.oa.flex_regs =
flex_eu_config_memory_writes;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_memory_writes);
return 0;
case METRIC_SET_ID_COMPUTE_EXTENDED:
dev_priv->perf.oa.n_mux_configs =
get_compute_extended_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_compute_extended;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_extended);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_extended;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_extended);
return 0;
case METRIC_SET_ID_COMPUTE_L3_CACHE:
dev_priv->perf.oa.n_mux_configs =
get_compute_l3_cache_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_compute_l3_cache;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_l3_cache);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_l3_cache;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_l3_cache);
return 0;
case METRIC_SET_ID_HDC_AND_SF:
dev_priv->perf.oa.n_mux_configs =
get_hdc_and_sf_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_hdc_and_sf;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_hdc_and_sf);
dev_priv->perf.oa.flex_regs =
flex_eu_config_hdc_and_sf;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_hdc_and_sf);
return 0;
case METRIC_SET_ID_L3_1:
dev_priv->perf.oa.n_mux_configs =
get_l3_1_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_l3_1;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_l3_1);
dev_priv->perf.oa.flex_regs =
flex_eu_config_l3_1;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_l3_1);
return 0;
case METRIC_SET_ID_L3_2:
dev_priv->perf.oa.n_mux_configs =
get_l3_2_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_l3_2;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_l3_2);
dev_priv->perf.oa.flex_regs =
flex_eu_config_l3_2;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_l3_2);
return 0;
case METRIC_SET_ID_L3_3:
dev_priv->perf.oa.n_mux_configs =
get_l3_3_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_l3_3;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_l3_3);
dev_priv->perf.oa.flex_regs =
flex_eu_config_l3_3;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_l3_3);
return 0;
case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
dev_priv->perf.oa.n_mux_configs =
get_rasterizer_and_pixel_backend_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_rasterizer_and_pixel_backend;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
dev_priv->perf.oa.flex_regs =
flex_eu_config_rasterizer_and_pixel_backend;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
return 0;
case METRIC_SET_ID_SAMPLER:
dev_priv->perf.oa.n_mux_configs =
get_sampler_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_sampler;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_sampler);
dev_priv->perf.oa.flex_regs =
flex_eu_config_sampler;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_sampler);
return 0;
case METRIC_SET_ID_TDL_1:
dev_priv->perf.oa.n_mux_configs =
get_tdl_1_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_tdl_1;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_tdl_1);
dev_priv->perf.oa.flex_regs =
flex_eu_config_tdl_1;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_tdl_1);
return 0;
case METRIC_SET_ID_TDL_2:
dev_priv->perf.oa.n_mux_configs =
get_tdl_2_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_tdl_2;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_tdl_2);
dev_priv->perf.oa.flex_regs =
flex_eu_config_tdl_2;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_tdl_2);
return 0;
case METRIC_SET_ID_COMPUTE_EXTRA:
dev_priv->perf.oa.n_mux_configs =
get_compute_extra_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_compute_extra;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_compute_extra);
dev_priv->perf.oa.flex_regs =
flex_eu_config_compute_extra;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_compute_extra);
return 0;
case METRIC_SET_ID_VME_PIPE:
dev_priv->perf.oa.n_mux_configs =
get_vme_pipe_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_vme_pipe;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_vme_pipe);
dev_priv->perf.oa.flex_regs =
flex_eu_config_vme_pipe;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_vme_pipe);
return 0;
case METRIC_SET_ID_TEST_OA:
dev_priv->perf.oa.n_mux_configs =
get_test_oa_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_test_oa;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_test_oa);
dev_priv->perf.oa.flex_regs =
flex_eu_config_test_oa;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_test_oa);
return 0;
default:
return -ENODEV;
}
}
static ssize_t
show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
}
static struct device_attribute dev_attr_render_basic_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_render_basic_id,
.store = NULL,
};
static struct attribute *attrs_render_basic[] = {
&dev_attr_render_basic_id.attr,
NULL,
};
static struct attribute_group group_render_basic = {
.name = "bad77c24-cc64-480d-99bf-e7b740713800",
.attrs = attrs_render_basic,
};
static ssize_t
show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
}
static struct device_attribute dev_attr_compute_basic_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_basic_id,
.store = NULL,
};
static struct attribute *attrs_compute_basic[] = {
&dev_attr_compute_basic_id.attr,
NULL,
};
static struct attribute_group group_compute_basic = {
.name = "7277228f-e7f3-4743-945a-6a2049d11377",
.attrs = attrs_compute_basic,
};
static ssize_t
show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
}
static struct device_attribute dev_attr_render_pipe_profile_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_render_pipe_profile_id,
.store = NULL,
};
static struct attribute *attrs_render_pipe_profile[] = {
&dev_attr_render_pipe_profile_id.attr,
NULL,
};
static struct attribute_group group_render_pipe_profile = {
.name = "463c668c-3f60-49b6-8f85-d995b635b3b2",
.attrs = attrs_render_pipe_profile,
};
static ssize_t
show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
}
switch (dev_priv->perf.oa.metrics_set) { static struct device_attribute dev_attr_memory_reads_id = {
case METRIC_SET_ID_RENDER_BASIC: .attr = { .name = "id", .mode = 0444 },
dev_priv->perf.oa.n_mux_configs = .show = show_memory_reads_id,
get_render_basic_mux_config(dev_priv, .store = NULL,
dev_priv->perf.oa.mux_regs, };
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
/* EINVAL because *_register_sysfs already checked this static struct attribute *attrs_memory_reads[] = {
* and so it wouldn't have been advertised to userspace and &dev_attr_memory_reads_id.attr,
* so shouldn't have been requested NULL,
*/ };
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs = static struct attribute_group group_memory_reads = {
b_counter_config_render_basic; .name = "3ae6e74c-72c3-4040-9bd0-7961430b8cc8",
dev_priv->perf.oa.b_counter_regs_len = .attrs = attrs_memory_reads,
ARRAY_SIZE(b_counter_config_render_basic); };
dev_priv->perf.oa.flex_regs = static ssize_t
flex_eu_config_render_basic; show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
dev_priv->perf.oa.flex_regs_len = {
ARRAY_SIZE(flex_eu_config_render_basic); return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
}
return 0; static struct device_attribute dev_attr_memory_writes_id = {
default: .attr = { .name = "id", .mode = 0444 },
return -ENODEV; .show = show_memory_writes_id,
} .store = NULL,
};
static struct attribute *attrs_memory_writes[] = {
&dev_attr_memory_writes_id.attr,
NULL,
};
static struct attribute_group group_memory_writes = {
.name = "055f256d-4052-467c-8dec-6064a4806433",
.attrs = attrs_memory_writes,
};
static ssize_t
show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
}
static struct device_attribute dev_attr_compute_extended_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_extended_id,
.store = NULL,
};
static struct attribute *attrs_compute_extended[] = {
&dev_attr_compute_extended_id.attr,
NULL,
};
static struct attribute_group group_compute_extended = {
.name = "753972d4-87cd-4460-824d-754463ac5054",
.attrs = attrs_compute_extended,
};
static ssize_t
show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
} }
static struct device_attribute dev_attr_compute_l3_cache_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_l3_cache_id,
.store = NULL,
};
static struct attribute *attrs_compute_l3_cache[] = {
&dev_attr_compute_l3_cache_id.attr,
NULL,
};
static struct attribute_group group_compute_l3_cache = {
.name = "4e4392e9-8f73-457b-ab44-b49f7a0c733b",
.attrs = attrs_compute_l3_cache,
};
static ssize_t static ssize_t
show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
{ {
return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
} }
static struct device_attribute dev_attr_render_basic_id = { static struct device_attribute dev_attr_hdc_and_sf_id = {
.attr = { .name = "id", .mode = 0444 }, .attr = { .name = "id", .mode = 0444 },
.show = show_render_basic_id, .show = show_hdc_and_sf_id,
.store = NULL, .store = NULL,
}; };
static struct attribute *attrs_render_basic[] = { static struct attribute *attrs_hdc_and_sf[] = {
&dev_attr_render_basic_id.attr, &dev_attr_hdc_and_sf_id.attr,
NULL, NULL,
}; };
static struct attribute_group group_render_basic = { static struct attribute_group group_hdc_and_sf = {
.name = "bad77c24-cc64-480d-99bf-e7b740713800", .name = "730d95dd-7da8-4e1c-ab8d-c0eb1e4c1805",
.attrs = attrs_render_basic, .attrs = attrs_hdc_and_sf,
};
static ssize_t
show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
}
static struct device_attribute dev_attr_l3_1_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_l3_1_id,
.store = NULL,
};
static struct attribute *attrs_l3_1[] = {
&dev_attr_l3_1_id.attr,
NULL,
};
static struct attribute_group group_l3_1 = {
.name = "d9e86d70-462b-462a-851e-fd63e8c13d63",
.attrs = attrs_l3_1,
};
static ssize_t
show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
}
static struct device_attribute dev_attr_l3_2_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_l3_2_id,
.store = NULL,
};
static struct attribute *attrs_l3_2[] = {
&dev_attr_l3_2_id.attr,
NULL,
};
static struct attribute_group group_l3_2 = {
.name = "52200424-6ee9-48b3-b7fa-0afcf1975e4d",
.attrs = attrs_l3_2,
};
static ssize_t
show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
}
static struct device_attribute dev_attr_l3_3_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_l3_3_id,
.store = NULL,
};
static struct attribute *attrs_l3_3[] = {
&dev_attr_l3_3_id.attr,
NULL,
};
static struct attribute_group group_l3_3 = {
.name = "1988315f-0a26-44df-acb0-df7ec86b1456",
.attrs = attrs_l3_3,
};
static ssize_t
show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
}
static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_rasterizer_and_pixel_backend_id,
.store = NULL,
};
static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
&dev_attr_rasterizer_and_pixel_backend_id.attr,
NULL,
};
static struct attribute_group group_rasterizer_and_pixel_backend = {
.name = "f1f17ca7-286e-4ae5-9d15-9fccad6c665d",
.attrs = attrs_rasterizer_and_pixel_backend,
};
static ssize_t
show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
}
static struct device_attribute dev_attr_sampler_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_sampler_id,
.store = NULL,
};
static struct attribute *attrs_sampler[] = {
&dev_attr_sampler_id.attr,
NULL,
};
static struct attribute_group group_sampler = {
.name = "00a9e0fb-3d2e-4405-852c-dce6334ffb3b",
.attrs = attrs_sampler,
};
static ssize_t
show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
}
static struct device_attribute dev_attr_tdl_1_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_tdl_1_id,
.store = NULL,
};
static struct attribute *attrs_tdl_1[] = {
&dev_attr_tdl_1_id.attr,
NULL,
};
static struct attribute_group group_tdl_1 = {
.name = "13dcc50a-7ec0-409b-99d6-a3f932cedcb3",
.attrs = attrs_tdl_1,
};
static ssize_t
show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
}
static struct device_attribute dev_attr_tdl_2_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_tdl_2_id,
.store = NULL,
};
static struct attribute *attrs_tdl_2[] = {
&dev_attr_tdl_2_id.attr,
NULL,
};
static struct attribute_group group_tdl_2 = {
.name = "97875e21-6624-4aee-9191-682feb3eae21",
.attrs = attrs_tdl_2,
};
static ssize_t
show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
}
static struct device_attribute dev_attr_compute_extra_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_compute_extra_id,
.store = NULL,
};
static struct attribute *attrs_compute_extra[] = {
&dev_attr_compute_extra_id.attr,
NULL,
};
static struct attribute_group group_compute_extra = {
.name = "a5aa857d-e8f0-4dfa-8981-ce340fa748fd",
.attrs = attrs_compute_extra,
};
static ssize_t
show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE);
}
static struct device_attribute dev_attr_vme_pipe_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_vme_pipe_id,
.store = NULL,
};
static struct attribute *attrs_vme_pipe[] = {
&dev_attr_vme_pipe_id.attr,
NULL,
};
static struct attribute_group group_vme_pipe = {
.name = "0e8d8b86-4ee7-4cdd-aaaa-58adc92cb29e",
.attrs = attrs_vme_pipe,
};
static ssize_t
show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
}
static struct device_attribute dev_attr_test_oa_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_test_oa_id,
.store = NULL,
};
static struct attribute *attrs_test_oa[] = {
&dev_attr_test_oa_id.attr,
NULL,
};
static struct attribute_group group_test_oa = {
.name = "882fa433-1f4a-4a67-a962-c741888fe5f5",
.attrs = attrs_test_oa,
}; };
int int
...@@ -242,9 +2905,145 @@ i915_perf_register_sysfs_sklgt4(struct drm_i915_private *dev_priv) ...@@ -242,9 +2905,145 @@ i915_perf_register_sysfs_sklgt4(struct drm_i915_private *dev_priv)
if (ret) if (ret)
goto error_render_basic; goto error_render_basic;
} }
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
if (ret)
goto error_compute_basic;
}
if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
if (ret)
goto error_render_pipe_profile;
}
if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
if (ret)
goto error_memory_reads;
}
if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
if (ret)
goto error_memory_writes;
}
if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
if (ret)
goto error_compute_extended;
}
if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
if (ret)
goto error_compute_l3_cache;
}
if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
if (ret)
goto error_hdc_and_sf;
}
if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
if (ret)
goto error_l3_1;
}
if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
if (ret)
goto error_l3_2;
}
if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
if (ret)
goto error_l3_3;
}
if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
if (ret)
goto error_rasterizer_and_pixel_backend;
}
if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
if (ret)
goto error_sampler;
}
if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
if (ret)
goto error_tdl_1;
}
if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
if (ret)
goto error_tdl_2;
}
if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
if (ret)
goto error_compute_extra;
}
if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
if (ret)
goto error_vme_pipe;
}
if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
if (ret)
goto error_test_oa;
}
return 0; return 0;
error_test_oa:
if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
error_vme_pipe:
if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
error_compute_extra:
if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
error_tdl_2:
if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
error_tdl_1:
if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
error_sampler:
if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
error_rasterizer_and_pixel_backend:
if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
error_l3_3:
if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
error_l3_2:
if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
error_l3_1:
if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
error_hdc_and_sf:
if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
error_compute_l3_cache:
if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
error_compute_extended:
if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
error_memory_writes:
if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
error_memory_reads:
if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
error_render_pipe_profile:
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
error_compute_basic:
if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
error_render_basic: error_render_basic:
return ret; return ret;
} }
...@@ -257,4 +3056,38 @@ i915_perf_unregister_sysfs_sklgt4(struct drm_i915_private *dev_priv) ...@@ -257,4 +3056,38 @@ i915_perf_unregister_sysfs_sklgt4(struct drm_i915_private *dev_priv)
if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
} }
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