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Commit fcf3790b authored by Vadim Pasternak's avatar Vadim Pasternak Committed by Hans de Goede
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platform: mellanox: Introduce support for next-generation 800GB/s switch 

Introduce support for Nvidia next-generation 800GB/s ethernet switch
SN5600.

SN5600 is 51.2 Tbps Ethernet switch based on Nvidia Spectrum-4 ASIC.
It can provide up to 64x800Gb/s (ETH) full bidirectional bandwidth per
port using PAM-4 modulations. The system supports 64 Belly to Belly 2x4
OSFP cages.
The switch was designed to fit standard 2U racks.

Features:
- 64 OSFP ports support 800GbE - 10GbE speed.
- Additional 25GbE - 1GbE service port on the front panel.
- Air-cooled with 3 + 1 redundant fan units.
- 1 + 1 redundant 3000W or 3600W PSUs.
- System management board is based on Intel Coffee-lake CPU E-2276
  with secure-boot support.
Signed-off-by: default avatarVadim Pasternak <vadimp@nvidia.com>
Reviewed-by: default avatarMichael Shych <michaelsh@nvidia.com>
Link: https://lore.kernel.org/r/20230208063331.15560-5-vadimp@nvidia.comSigned-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent acc6ea30
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drivers/platform/x86/mlx-platform.c
View file @ fcf3790b
...@@ -253,6 +253,7 @@ ...@@ -253,6 +253,7 @@
#define MLXPLAT_CPLD_CH3_ETH_MODULAR 43 #define MLXPLAT_CPLD_CH3_ETH_MODULAR 43
#define MLXPLAT_CPLD_CH4_ETH_MODULAR 51 #define MLXPLAT_CPLD_CH4_ETH_MODULAR 51
#define MLXPLAT_CPLD_CH2_RACK_SWITCH 18 #define MLXPLAT_CPLD_CH2_RACK_SWITCH 18
#define MLXPLAT_CPLD_CH2_NG800 34
/* Number of LPC attached MUX platform devices */ /* Number of LPC attached MUX platform devices */
#define MLXPLAT_CPLD_LPC_MUX_DEVS 4 #define MLXPLAT_CPLD_LPC_MUX_DEVS 4
...@@ -503,6 +504,37 @@ static struct i2c_mux_reg_platform_data mlxplat_rack_switch_mux_data[] = { ...@@ -503,6 +504,37 @@ static struct i2c_mux_reg_platform_data mlxplat_rack_switch_mux_data[] = {
}; };
/* Platform channels for ng800 system family */
static const int mlxplat_ng800_channels[] = {
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32
};
/* Platform ng800 mux data */
static struct i2c_mux_reg_platform_data mlxplat_ng800_mux_data[] = {
{
.parent = 1,
.base_nr = MLXPLAT_CPLD_CH1,
.write_only = 1,
.reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
.reg_size = 1,
.idle_in_use = 1,
.values = mlxplat_ng800_channels,
.n_values = ARRAY_SIZE(mlxplat_ng800_channels),
},
{
.parent = 1,
.base_nr = MLXPLAT_CPLD_CH2_NG800,
.write_only = 1,
.reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
.reg_size = 1,
.idle_in_use = 1,
.values = mlxplat_msn21xx_channels,
.n_values = ARRAY_SIZE(mlxplat_msn21xx_channels),
},
};
/* Platform hotplug devices */ /* Platform hotplug devices */
static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { static struct i2c_board_info mlxplat_mlxcpld_pwr[] = {
{ {
...@@ -522,6 +554,15 @@ static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = { ...@@ -522,6 +554,15 @@ static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = {
}, },
}; };
static struct i2c_board_info mlxplat_mlxcpld_pwr_ng800[] = {
{
I2C_BOARD_INFO("dps460", 0x59),
},
{
I2C_BOARD_INFO("dps460", 0x5a),
},
};
static struct i2c_board_info mlxplat_mlxcpld_fan[] = { static struct i2c_board_info mlxplat_mlxcpld_fan[] = {
{ {
I2C_BOARD_INFO("24c32", 0x50), I2C_BOARD_INFO("24c32", 0x50),
...@@ -601,6 +642,23 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = { ...@@ -601,6 +642,23 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = {
}, },
}; };
static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_ng800_items_data[] = {
{
.label = "pwr1",
.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
.mask = BIT(0),
.hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[0],
.hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
},
{
.label = "pwr2",
.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
.mask = BIT(1),
.hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[1],
.hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
},
};
static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = { static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = {
{ {
.label = "fan1", .label = "fan1",
...@@ -1224,6 +1282,47 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { ...@@ -1224,6 +1282,47 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = {
} }
}; };
static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = {
{
.data = mlxplat_mlxcpld_default_ng_psu_items_data,
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
.mask = MLXPLAT_CPLD_PSU_EXT_MASK,
.capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
.count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data),
.inversed = 1,
.health = false,
},
{
.data = mlxplat_mlxcpld_default_pwr_ng800_items_data,
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
.mask = MLXPLAT_CPLD_PWR_EXT_MASK,
.capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
.count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_ng800_items_data),
.inversed = 0,
.health = false,
},
{
.data = mlxplat_mlxcpld_default_ng_fan_items_data,
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
.mask = MLXPLAT_CPLD_FAN_NG_MASK,
.count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
.inversed = 1,
.health = false,
},
{
.data = mlxplat_mlxcpld_default_asic_items_data,
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
.reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
.mask = MLXPLAT_CPLD_ASIC_MASK,
.count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
.inversed = 0,
.health = true,
},
};
static static
struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {
.items = mlxplat_mlxcpld_ext_items, .items = mlxplat_mlxcpld_ext_items,
...@@ -1234,6 +1333,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { ...@@ -1234,6 +1333,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {
.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2,
}; };
static
struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = {
.items = mlxplat_mlxcpld_ng800_items,
.counter = ARRAY_SIZE(mlxplat_mlxcpld_ng800_items),
.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
.mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2,
};
static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = {
{ {
.label = "pwr1", .label = "pwr1",
...@@ -3093,6 +3202,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { ...@@ -3093,6 +3202,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
.mask = GENMASK(7, 0) & ~BIT(7), .mask = GENMASK(7, 0) & ~BIT(7),
.mode = 0644, .mode = 0644,
}, },
{
.label = "clk_brd_prog_en",
.reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
.mask = GENMASK(7, 0) & ~BIT(1),
.mode = 0644,
.secured = 1,
},
{ {
.label = "erot1_recovery", .label = "erot1_recovery",
.reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
...@@ -3221,6 +3337,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { ...@@ -3221,6 +3337,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
.mask = GENMASK(7, 0) & ~BIT(6), .mask = GENMASK(7, 0) & ~BIT(6),
.mode = 0444, .mode = 0444,
}, },
{
.label = "reset_ac_ok_fail",
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
.mask = GENMASK(7, 0) & ~BIT(7),
.mode = 0444,
},
{ {
.label = "psu1_on", .label = "psu1_on",
.reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
...@@ -3302,6 +3424,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { ...@@ -3302,6 +3424,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
.bit = 5, .bit = 5,
.mode = 0444, .mode = 0444,
}, },
{
.label = "pwr_converter_prog_en",
.reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
.mask = GENMASK(7, 0) & ~BIT(0),
.mode = 0644,
.secured = 1,
},
{ {
.label = "vpd_wp", .label = "vpd_wp",
.reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
...@@ -3326,6 +3455,30 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { ...@@ -3326,6 +3455,30 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
.mask = GENMASK(7, 0) & ~BIT(1), .mask = GENMASK(7, 0) & ~BIT(1),
.mode = 0444, .mode = 0444,
}, },
{
.label = "clk_brd1_boot_fail",
.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
.mask = GENMASK(7, 0) & ~BIT(4),
.mode = 0444,
},
{
.label = "clk_brd2_boot_fail",
.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
.mask = GENMASK(7, 0) & ~BIT(5),
.mode = 0444,
},
{
.label = "clk_brd_fail",
.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
.mask = GENMASK(7, 0) & ~BIT(6),
.mode = 0444,
},
{
.label = "asic_pg_fail",
.reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
.mask = GENMASK(7, 0) & ~BIT(7),
.mode = 0444,
},
{ {
.label = "spi_chnl_select", .label = "spi_chnl_select",
.reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT, .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT,
...@@ -5211,6 +5364,27 @@ static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dm ...@@ -5211,6 +5364,27 @@ static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dm
return 1; return 1;
} }
static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi)
{
int i;
mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data);
mlxplat_mux_data = mlxplat_ng800_mux_data;
mlxplat_hotplug = &mlxplat_mlxcpld_ng800_data;
mlxplat_hotplug->deferred_nr =
mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
mlxplat_led = &mlxplat_default_ng_led_data;
mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
mlxplat_fan = &mlxplat_default_fan_data;
for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400;
return 1;
}
static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
{ {
.callback = mlxplat_dmi_default_wc_matched, .callback = mlxplat_dmi_default_wc_matched,
...@@ -5287,6 +5461,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { ...@@ -5287,6 +5461,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"), DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"),
}, },
}, },
{
.callback = mlxplat_dmi_ng800_matched,
.matches = {
DMI_MATCH(DMI_BOARD_NAME, "VMOD0013"),
},
},
{ {
.callback = mlxplat_dmi_chassis_blade_matched, .callback = mlxplat_dmi_chassis_blade_matched,
.matches = { .matches = {
......
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