Commit fe63a066 authored by Marc Kleine-Budde's avatar Marc Kleine-Budde

can: flexcan: struct flexcan_regs: document registers not affected by soft reset

This patch documents which registers are not affected by a soft reset of the
flexcan IP core.
Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20200922144429.2613631-5-mkl@pengutronix.de
parent 4b702878
...@@ -203,12 +203,12 @@ struct flexcan_mb { ...@@ -203,12 +203,12 @@ struct flexcan_mb {
/* Structure of the hardware registers */ /* Structure of the hardware registers */
struct flexcan_regs { struct flexcan_regs {
u32 mcr; /* 0x00 */ u32 mcr; /* 0x00 */
u32 ctrl; /* 0x04 */ u32 ctrl; /* 0x04 - Not affected by Soft Reset */
u32 timer; /* 0x08 */ u32 timer; /* 0x08 */
u32 tcr; /* 0x0c */ u32 tcr; /* 0x0c */
u32 rxgmask; /* 0x10 */ u32 rxgmask; /* 0x10 - Not affected by Soft Reset */
u32 rx14mask; /* 0x14 */ u32 rx14mask; /* 0x14 - Not affected by Soft Reset */
u32 rx15mask; /* 0x18 */ u32 rx15mask; /* 0x18 - Not affected by Soft Reset */
u32 ecr; /* 0x1c */ u32 ecr; /* 0x1c */
u32 esr; /* 0x20 */ u32 esr; /* 0x20 */
u32 imask2; /* 0x24 */ u32 imask2; /* 0x24 */
...@@ -217,20 +217,20 @@ struct flexcan_regs { ...@@ -217,20 +217,20 @@ struct flexcan_regs {
u32 iflag1; /* 0x30 */ u32 iflag1; /* 0x30 */
union { /* 0x34 */ union { /* 0x34 */
u32 gfwr_mx28; /* MX28, MX53 */ u32 gfwr_mx28; /* MX28, MX53 */
u32 ctrl2; /* MX6, VF610 */ u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */
}; };
u32 esr2; /* 0x38 */ u32 esr2; /* 0x38 */
u32 imeur; /* 0x3c */ u32 imeur; /* 0x3c */
u32 lrfr; /* 0x40 */ u32 lrfr; /* 0x40 */
u32 crcr; /* 0x44 */ u32 crcr; /* 0x44 */
u32 rxfgmask; /* 0x48 */ u32 rxfgmask; /* 0x48 */
u32 rxfir; /* 0x4c */ u32 rxfir; /* 0x4c - Not affected by Soft Reset */
u32 cbt; /* 0x50 */ u32 cbt; /* 0x50 - Not affected by Soft Reset */
u32 _reserved2; /* 0x54 */ u32 _reserved2; /* 0x54 */
u32 dbg1; /* 0x58 */ u32 dbg1; /* 0x58 */
u32 dbg2; /* 0x5c */ u32 dbg2; /* 0x5c */
u32 _reserved3[8]; /* 0x60 */ u32 _reserved3[8]; /* 0x60 */
u8 mb[2][512]; /* 0x80 */ u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */
/* FIFO-mode: /* FIFO-mode:
* MB * MB
* 0x080...0x08f 0 RX message buffer * 0x080...0x08f 0 RX message buffer
...@@ -242,7 +242,7 @@ struct flexcan_regs { ...@@ -242,7 +242,7 @@ struct flexcan_regs {
* (mx6, vf610) * (mx6, vf610)
*/ */
u32 _reserved4[256]; /* 0x480 */ u32 _reserved4[256]; /* 0x480 */
u32 rximr[64]; /* 0x880 */ u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */
u32 _reserved5[24]; /* 0x980 */ u32 _reserved5[24]; /* 0x980 */
u32 gfwr_mx6; /* 0x9e0 - MX6 */ u32 gfwr_mx6; /* 0x9e0 - MX6 */
u32 _reserved6[63]; /* 0x9e4 */ u32 _reserved6[63]; /* 0x9e4 */
...@@ -255,8 +255,8 @@ struct flexcan_regs { ...@@ -255,8 +255,8 @@ struct flexcan_regs {
u32 rerrsynr; /* 0xaf8 */ u32 rerrsynr; /* 0xaf8 */
u32 errsr; /* 0xafc */ u32 errsr; /* 0xafc */
u32 _reserved7[64]; /* 0xb00 */ u32 _reserved7[64]; /* 0xb00 */
u32 fdctrl; /* 0xc00 */ u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */
u32 fdcbt; /* 0xc04 */ u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */
u32 fdcrc; /* 0xc08 */ u32 fdcrc; /* 0xc08 */
}; };
......
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