Commit fff35d45 authored by Sakari Ailus's avatar Sakari Ailus Committed by Mauro Carvalho Chehab

media: v4l2-fwnode: The first default data lane is 0 on C-PHY

C-PHY has no clock lanes. Therefore the first data lane is 0 by default.

Fixes: edc6d56c ("media: v4l: fwnode: Support parsing of CSI-2 C-PHY endpoints")
Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent 9d386373
...@@ -229,6 +229,10 @@ static int v4l2_fwnode_endpoint_parse_csi2_bus(struct fwnode_handle *fwnode, ...@@ -229,6 +229,10 @@ static int v4l2_fwnode_endpoint_parse_csi2_bus(struct fwnode_handle *fwnode,
if (bus_type == V4L2_MBUS_CSI2_DPHY || if (bus_type == V4L2_MBUS_CSI2_DPHY ||
bus_type == V4L2_MBUS_CSI2_CPHY || lanes_used || bus_type == V4L2_MBUS_CSI2_CPHY || lanes_used ||
have_clk_lane || (flags & ~V4L2_MBUS_CSI2_CONTINUOUS_CLOCK)) { have_clk_lane || (flags & ~V4L2_MBUS_CSI2_CONTINUOUS_CLOCK)) {
/* Only D-PHY has a clock lane. */
unsigned int dfl_data_lane_index =
bus_type == V4L2_MBUS_CSI2_DPHY;
bus->flags = flags; bus->flags = flags;
if (bus_type == V4L2_MBUS_UNKNOWN) if (bus_type == V4L2_MBUS_UNKNOWN)
vep->bus_type = V4L2_MBUS_CSI2_DPHY; vep->bus_type = V4L2_MBUS_CSI2_DPHY;
...@@ -237,7 +241,7 @@ static int v4l2_fwnode_endpoint_parse_csi2_bus(struct fwnode_handle *fwnode, ...@@ -237,7 +241,7 @@ static int v4l2_fwnode_endpoint_parse_csi2_bus(struct fwnode_handle *fwnode,
if (use_default_lane_mapping) { if (use_default_lane_mapping) {
bus->clock_lane = 0; bus->clock_lane = 0;
for (i = 0; i < num_data_lanes; i++) for (i = 0; i < num_data_lanes; i++)
bus->data_lanes[i] = 1 + i; bus->data_lanes[i] = dfl_data_lane_index + i;
} else { } else {
bus->clock_lane = clock_lane; bus->clock_lane = clock_lane;
for (i = 0; i < num_data_lanes; i++) for (i = 0; i < num_data_lanes; i++)
......
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