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nexedi
linux
Commits
02917aa3
Commit
02917aa3
authored
May 08, 2018
by
Ben Skeggs
Browse files
Options
Browse Files
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Email Patches
Plain Diff
drm/nouveau/gr/gf100-: virtualise init_zcull
Signed-off-by:
Ben Skeggs
<
bskeggs@redhat.com
>
parent
2fe5ff63
Changes
19
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Showing
19 changed files
with
85 additions
and
178 deletions
+85
-178
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
+30
-32
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
+4
-0
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
+1
-0
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c
+1
-0
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c
+1
-0
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c
+29
-0
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c
+1
-0
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
+2
-29
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
+1
-0
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
+1
-0
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
+1
-0
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
+3
-30
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
+2
-29
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
+2
-29
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c
+1
-0
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c
+2
-29
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c
+1
-0
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c
+1
-0
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c
+1
-0
No files found.
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View file @
02917aa3
...
...
@@ -1930,6 +1930,34 @@ gf100_gr_init_gpc_mmu(struct gf100_gr *gr)
nvkm_wr32
(
device
,
0x4188b8
,
nvkm_memory_addr
(
fb
->
mmu_rd
)
>>
8
);
}
void
gf100_gr_init_zcull
(
struct
gf100_gr
*
gr
)
{
struct
nvkm_device
*
device
=
gr
->
base
.
engine
.
subdev
.
device
;
const
u32
magicgpc918
=
DIV_ROUND_UP
(
0x00800000
,
gr
->
tpc_total
);
u32
data
[
TPC_MAX
/
8
]
=
{};
u8
tpcnr
[
GPC_MAX
];
int
gpc
,
tpc
;
int
i
;
memcpy
(
tpcnr
,
gr
->
tpc_nr
,
sizeof
(
gr
->
tpc_nr
));
for
(
i
=
0
,
gpc
=
-
1
;
i
<
gr
->
tpc_total
;
i
++
)
{
do
{
gpc
=
(
gpc
+
1
)
%
gr
->
gpc_nr
;
}
while
(
!
tpcnr
[
gpc
]);
tpc
=
gr
->
tpc_nr
[
gpc
]
-
tpcnr
[
gpc
]
--
;
data
[
i
/
8
]
|=
tpc
<<
((
i
%
8
)
*
4
);
}
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0980
),
data
[
0
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0984
),
data
[
1
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0988
),
data
[
2
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x098c
),
data
[
3
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x1bd4
),
magicgpc918
);
}
void
gf100_gr_init_vsc_stream_master
(
struct
gf100_gr
*
gr
)
{
...
...
@@ -1941,11 +1969,7 @@ int
gf100_gr_init
(
struct
gf100_gr
*
gr
)
{
struct
nvkm_device
*
device
=
gr
->
base
.
engine
.
subdev
.
device
;
const
u32
magicgpc918
=
DIV_ROUND_UP
(
0x00800000
,
gr
->
tpc_total
);
u32
data
[
TPC_MAX
/
8
]
=
{};
u8
tpcnr
[
GPC_MAX
];
int
gpc
,
tpc
,
rop
;
int
i
;
gr
->
func
->
init_gpc_mmu
(
gr
);
...
...
@@ -1964,34 +1988,7 @@ gf100_gr_init(struct gf100_gr *gr)
gr
->
func
->
init_bios
(
gr
);
gr
->
func
->
init_vsc_stream_master
(
gr
);
memcpy
(
tpcnr
,
gr
->
tpc_nr
,
sizeof
(
gr
->
tpc_nr
));
for
(
i
=
0
,
gpc
=
-
1
;
i
<
gr
->
tpc_total
;
i
++
)
{
do
{
gpc
=
(
gpc
+
1
)
%
gr
->
gpc_nr
;
}
while
(
!
tpcnr
[
gpc
]);
tpc
=
gr
->
tpc_nr
[
gpc
]
-
tpcnr
[
gpc
]
--
;
data
[
i
/
8
]
|=
tpc
<<
((
i
%
8
)
*
4
);
}
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0980
),
data
[
0
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0984
),
data
[
1
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0988
),
data
[
2
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x098c
),
data
[
3
]);
for
(
gpc
=
0
;
gpc
<
gr
->
gpc_nr
;
gpc
++
)
{
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0914
),
gr
->
screen_tile_row_offset
<<
8
|
gr
->
tpc_nr
[
gpc
]);
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0910
),
0x00040000
|
gr
->
tpc_total
);
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0918
),
magicgpc918
);
}
if
(
device
->
chipset
!=
0xd7
)
nvkm_wr32
(
device
,
GPC_BCAST
(
0x1bd4
),
magicgpc918
);
else
nvkm_wr32
(
device
,
GPC_BCAST
(
0x3fd4
),
magicgpc918
);
gr
->
func
->
init_zcull
(
gr
);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x08ac
),
nvkm_rd32
(
device
,
0x100800
));
...
...
@@ -2076,6 +2073,7 @@ gf100_gr = {
.
init
=
gf100_gr_init
,
.
init_gpc_mmu
=
gf100_gr_init_gpc_mmu
,
.
init_vsc_stream_master
=
gf100_gr_init_vsc_stream_master
,
.
init_zcull
=
gf100_gr_init_zcull
,
.
mmio
=
gf100_gr_pack_mmio
,
.
fecs
.
ucode
=
&
gf100_gr_fecs_ucode
,
.
gpccs
.
ucode
=
&
gf100_gr_gpccs_ucode
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View file @
02917aa3
...
...
@@ -125,6 +125,7 @@ struct gf100_gr_func {
void
(
*
init_r405a14
)(
struct
gf100_gr
*
);
void
(
*
init_bios
)(
struct
gf100_gr
*
);
void
(
*
init_vsc_stream_master
)(
struct
gf100_gr
*
);
void
(
*
init_zcull
)(
struct
gf100_gr
*
);
void
(
*
init_rop_active_fbps
)(
struct
gf100_gr
*
);
void
(
*
init_ppc_exceptions
)(
struct
gf100_gr
*
);
void
(
*
init_swdx_pes_mask
)(
struct
gf100_gr
*
);
...
...
@@ -147,6 +148,9 @@ struct gf100_gr_func {
int
gf100_gr_rops
(
struct
gf100_gr
*
);
int
gf100_gr_init
(
struct
gf100_gr
*
);
void
gf100_gr_init_vsc_stream_master
(
struct
gf100_gr
*
);
void
gf100_gr_init_zcull
(
struct
gf100_gr
*
);
void
gf117_gr_init_zcull
(
struct
gf100_gr
*
);
int
gk104_gr_init
(
struct
gf100_gr
*
);
void
gk104_gr_init_vsc_stream_master
(
struct
gf100_gr
*
);
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
View file @
02917aa3
...
...
@@ -117,6 +117,7 @@ gf104_gr = {
.
init
=
gf100_gr_init
,
.
init_gpc_mmu
=
gf100_gr_init_gpc_mmu
,
.
init_vsc_stream_master
=
gf100_gr_init_vsc_stream_master
,
.
init_zcull
=
gf100_gr_init_zcull
,
.
mmio
=
gf104_gr_pack_mmio
,
.
fecs
.
ucode
=
&
gf100_gr_fecs_ucode
,
.
gpccs
.
ucode
=
&
gf100_gr_gpccs_ucode
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c
View file @
02917aa3
...
...
@@ -115,6 +115,7 @@ gf108_gr = {
.
init_gpc_mmu
=
gf100_gr_init_gpc_mmu
,
.
init_r405a14
=
gf108_gr_init_r405a14
,
.
init_vsc_stream_master
=
gf100_gr_init_vsc_stream_master
,
.
init_zcull
=
gf100_gr_init_zcull
,
.
mmio
=
gf108_gr_pack_mmio
,
.
fecs
.
ucode
=
&
gf100_gr_fecs_ucode
,
.
gpccs
.
ucode
=
&
gf100_gr_gpccs_ucode
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c
View file @
02917aa3
...
...
@@ -89,6 +89,7 @@ gf110_gr = {
.
init
=
gf100_gr_init
,
.
init_gpc_mmu
=
gf100_gr_init_gpc_mmu
,
.
init_vsc_stream_master
=
gf100_gr_init_vsc_stream_master
,
.
init_zcull
=
gf100_gr_init_zcull
,
.
mmio
=
gf110_gr_pack_mmio
,
.
fecs
.
ucode
=
&
gf100_gr_fecs_ucode
,
.
gpccs
.
ucode
=
&
gf100_gr_gpccs_ucode
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c
View file @
02917aa3
...
...
@@ -120,11 +120,40 @@ gf117_gr_gpccs_ucode = {
.
data
.
size
=
sizeof
(
gf117_grgpc_data
),
};
void
gf117_gr_init_zcull
(
struct
gf100_gr
*
gr
)
{
struct
nvkm_device
*
device
=
gr
->
base
.
engine
.
subdev
.
device
;
const
u32
magicgpc918
=
DIV_ROUND_UP
(
0x00800000
,
gr
->
tpc_total
);
u32
data
[
TPC_MAX
/
8
]
=
{};
u8
tpcnr
[
GPC_MAX
];
int
gpc
,
tpc
;
int
i
;
memcpy
(
tpcnr
,
gr
->
tpc_nr
,
sizeof
(
gr
->
tpc_nr
));
for
(
i
=
0
,
gpc
=
-
1
;
i
<
gr
->
tpc_total
;
i
++
)
{
do
{
gpc
=
(
gpc
+
1
)
%
gr
->
gpc_nr
;
}
while
(
!
tpcnr
[
gpc
]);
tpc
=
gr
->
tpc_nr
[
gpc
]
-
tpcnr
[
gpc
]
--
;
data
[
i
/
8
]
|=
tpc
<<
((
i
%
8
)
*
4
);
}
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0980
),
data
[
0
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0984
),
data
[
1
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0988
),
data
[
2
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x098c
),
data
[
3
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x3fd4
),
magicgpc918
);
}
static
const
struct
gf100_gr_func
gf117_gr
=
{
.
init
=
gf100_gr_init
,
.
init_gpc_mmu
=
gf100_gr_init_gpc_mmu
,
.
init_vsc_stream_master
=
gf100_gr_init_vsc_stream_master
,
.
init_zcull
=
gf117_gr_init_zcull
,
.
mmio
=
gf117_gr_pack_mmio
,
.
fecs
.
ucode
=
&
gf117_gr_fecs_ucode
,
.
gpccs
.
ucode
=
&
gf117_gr_gpccs_ucode
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c
View file @
02917aa3
...
...
@@ -180,6 +180,7 @@ gf119_gr = {
.
init
=
gf100_gr_init
,
.
init_gpc_mmu
=
gf100_gr_init_gpc_mmu
,
.
init_vsc_stream_master
=
gf100_gr_init_vsc_stream_master
,
.
init_zcull
=
gf100_gr_init_zcull
,
.
mmio
=
gf119_gr_pack_mmio
,
.
fecs
.
ucode
=
&
gf100_gr_fecs_ucode
,
.
gpccs
.
ucode
=
&
gf100_gr_gpccs_ucode
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
View file @
02917aa3
...
...
@@ -415,11 +415,7 @@ int
gk104_gr_init
(
struct
gf100_gr
*
gr
)
{
struct
nvkm_device
*
device
=
gr
->
base
.
engine
.
subdev
.
device
;
const
u32
magicgpc918
=
DIV_ROUND_UP
(
0x00800000
,
gr
->
tpc_total
);
u32
data
[
TPC_MAX
/
8
]
=
{};
u8
tpcnr
[
GPC_MAX
];
int
gpc
,
tpc
,
rop
;
int
i
;
gr
->
func
->
init_gpc_mmu
(
gr
);
...
...
@@ -429,32 +425,8 @@ gk104_gr_init(struct gf100_gr *gr)
gr
->
func
->
clkgate_pack
);
gr
->
func
->
init_vsc_stream_master
(
gr
);
gr
->
func
->
init_zcull
(
gr
);
memset
(
data
,
0x00
,
sizeof
(
data
));
memcpy
(
tpcnr
,
gr
->
tpc_nr
,
sizeof
(
gr
->
tpc_nr
));
for
(
i
=
0
,
gpc
=
-
1
;
i
<
gr
->
tpc_total
;
i
++
)
{
do
{
gpc
=
(
gpc
+
1
)
%
gr
->
gpc_nr
;
}
while
(
!
tpcnr
[
gpc
]);
tpc
=
gr
->
tpc_nr
[
gpc
]
-
tpcnr
[
gpc
]
--
;
data
[
i
/
8
]
|=
tpc
<<
((
i
%
8
)
*
4
);
}
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0980
),
data
[
0
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0984
),
data
[
1
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0988
),
data
[
2
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x098c
),
data
[
3
]);
for
(
gpc
=
0
;
gpc
<
gr
->
gpc_nr
;
gpc
++
)
{
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0914
),
gr
->
screen_tile_row_offset
<<
8
|
gr
->
tpc_nr
[
gpc
]);
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0910
),
0x00040000
|
gr
->
tpc_total
);
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0918
),
magicgpc918
);
}
nvkm_wr32
(
device
,
GPC_BCAST
(
0x3fd4
),
magicgpc918
);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x08ac
),
nvkm_rd32
(
device
,
0x100800
));
gr
->
func
->
init_rop_active_fbps
(
gr
);
...
...
@@ -544,6 +516,7 @@ gk104_gr = {
.
init
=
gk104_gr_init
,
.
init_gpc_mmu
=
gf100_gr_init_gpc_mmu
,
.
init_vsc_stream_master
=
gk104_gr_init_vsc_stream_master
,
.
init_zcull
=
gf117_gr_init_zcull
,
.
init_rop_active_fbps
=
gk104_gr_init_rop_active_fbps
,
.
init_ppc_exceptions
=
gk104_gr_init_ppc_exceptions
,
.
mmio
=
gk104_gr_pack_mmio
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
View file @
02917aa3
...
...
@@ -339,6 +339,7 @@ gk110_gr = {
.
init
=
gk104_gr_init
,
.
init_gpc_mmu
=
gf100_gr_init_gpc_mmu
,
.
init_vsc_stream_master
=
gk104_gr_init_vsc_stream_master
,
.
init_zcull
=
gf117_gr_init_zcull
,
.
init_rop_active_fbps
=
gk104_gr_init_rop_active_fbps
,
.
init_ppc_exceptions
=
gk104_gr_init_ppc_exceptions
,
.
mmio
=
gk110_gr_pack_mmio
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
View file @
02917aa3
...
...
@@ -105,6 +105,7 @@ gk110b_gr = {
.
init
=
gk104_gr_init
,
.
init_gpc_mmu
=
gf100_gr_init_gpc_mmu
,
.
init_vsc_stream_master
=
gk104_gr_init_vsc_stream_master
,
.
init_zcull
=
gf117_gr_init_zcull
,
.
init_rop_active_fbps
=
gk104_gr_init_rop_active_fbps
,
.
init_ppc_exceptions
=
gk104_gr_init_ppc_exceptions
,
.
mmio
=
gk110b_gr_pack_mmio
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
View file @
02917aa3
...
...
@@ -164,6 +164,7 @@ gk208_gr = {
.
init
=
gk104_gr_init
,
.
init_gpc_mmu
=
gf100_gr_init_gpc_mmu
,
.
init_vsc_stream_master
=
gk104_gr_init_vsc_stream_master
,
.
init_zcull
=
gf117_gr_init_zcull
,
.
init_rop_active_fbps
=
gk104_gr_init_rop_active_fbps
,
.
init_ppc_exceptions
=
gk104_gr_init_ppc_exceptions
,
.
mmio
=
gk208_gr_pack_mmio
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
View file @
02917aa3
...
...
@@ -219,11 +219,7 @@ int
gk20a_gr_init
(
struct
gf100_gr
*
gr
)
{
struct
nvkm_device
*
device
=
gr
->
base
.
engine
.
subdev
.
device
;
const
u32
magicgpc918
=
DIV_ROUND_UP
(
0x00800000
,
gr
->
tpc_total
);
u32
data
[
TPC_MAX
/
8
]
=
{};
u8
tpcnr
[
GPC_MAX
];
int
gpc
,
tpc
;
int
ret
,
i
;
int
ret
;
/* Clear SCC RAM */
nvkm_wr32
(
device
,
0x40802c
,
0x1
);
...
...
@@ -246,31 +242,7 @@ gk20a_gr_init(struct gf100_gr *gr)
nvkm_mask
(
device
,
0x503018
,
0x1
,
0x1
);
/* Zcull init */
memset
(
data
,
0x00
,
sizeof
(
data
));
memcpy
(
tpcnr
,
gr
->
tpc_nr
,
sizeof
(
gr
->
tpc_nr
));
for
(
i
=
0
,
gpc
=
-
1
;
i
<
gr
->
tpc_total
;
i
++
)
{
do
{
gpc
=
(
gpc
+
1
)
%
gr
->
gpc_nr
;
}
while
(
!
tpcnr
[
gpc
]);
tpc
=
gr
->
tpc_nr
[
gpc
]
-
tpcnr
[
gpc
]
--
;
data
[
i
/
8
]
|=
tpc
<<
((
i
%
8
)
*
4
);
}
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0980
),
data
[
0
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0984
),
data
[
1
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0988
),
data
[
2
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x098c
),
data
[
3
]);
for
(
gpc
=
0
;
gpc
<
gr
->
gpc_nr
;
gpc
++
)
{
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0914
),
gr
->
screen_tile_row_offset
<<
8
|
gr
->
tpc_nr
[
gpc
]);
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0910
),
0x00040000
|
gr
->
tpc_total
);
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0918
),
magicgpc918
);
}
nvkm_wr32
(
device
,
GPC_BCAST
(
0x3fd4
),
magicgpc918
);
gr
->
func
->
init_zcull
(
gr
);
gr
->
func
->
init_rop_active_fbps
(
gr
);
...
...
@@ -311,6 +283,7 @@ gk20a_gr_init(struct gf100_gr *gr)
static
const
struct
gf100_gr_func
gk20a_gr
=
{
.
init
=
gk20a_gr_init
,
.
init_zcull
=
gf117_gr_init_zcull
,
.
init_rop_active_fbps
=
gk104_gr_init_rop_active_fbps
,
.
set_hww_esr_report_mask
=
gk20a_gr_set_hww_esr_report_mask
,
.
rops
=
gf100_gr_rops
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
View file @
02917aa3
...
...
@@ -325,11 +325,7 @@ static int
gm107_gr_init
(
struct
gf100_gr
*
gr
)
{
struct
nvkm_device
*
device
=
gr
->
base
.
engine
.
subdev
.
device
;
const
u32
magicgpc918
=
DIV_ROUND_UP
(
0x00800000
,
gr
->
tpc_total
);
u32
data
[
TPC_MAX
/
8
]
=
{};
u8
tpcnr
[
GPC_MAX
];
int
gpc
,
tpc
,
rop
;
int
i
;
gr
->
func
->
init_gpc_mmu
(
gr
);
...
...
@@ -338,32 +334,8 @@ gm107_gr_init(struct gf100_gr *gr)
gr
->
func
->
init_bios
(
gr
);
gr
->
func
->
init_vsc_stream_master
(
gr
);
gr
->
func
->
init_zcull
(
gr
);
memset
(
data
,
0x00
,
sizeof
(
data
));
memcpy
(
tpcnr
,
gr
->
tpc_nr
,
sizeof
(
gr
->
tpc_nr
));
for
(
i
=
0
,
gpc
=
-
1
;
i
<
gr
->
tpc_total
;
i
++
)
{
do
{
gpc
=
(
gpc
+
1
)
%
gr
->
gpc_nr
;
}
while
(
!
tpcnr
[
gpc
]);
tpc
=
gr
->
tpc_nr
[
gpc
]
-
tpcnr
[
gpc
]
--
;
data
[
i
/
8
]
|=
tpc
<<
((
i
%
8
)
*
4
);
}
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0980
),
data
[
0
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0984
),
data
[
1
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0988
),
data
[
2
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x098c
),
data
[
3
]);
for
(
gpc
=
0
;
gpc
<
gr
->
gpc_nr
;
gpc
++
)
{
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0914
),
gr
->
screen_tile_row_offset
<<
8
|
gr
->
tpc_nr
[
gpc
]);
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0910
),
0x00040000
|
gr
->
tpc_total
);
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0918
),
magicgpc918
);
}
nvkm_wr32
(
device
,
GPC_BCAST
(
0x3fd4
),
magicgpc918
);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x08ac
),
nvkm_rd32
(
device
,
0x100800
));
gr
->
func
->
init_rop_active_fbps
(
gr
);
...
...
@@ -453,6 +425,7 @@ gm107_gr = {
.
init_gpc_mmu
=
gm107_gr_init_gpc_mmu
,
.
init_bios
=
gm107_gr_init_bios
,
.
init_vsc_stream_master
=
gk104_gr_init_vsc_stream_master
,
.
init_zcull
=
gf117_gr_init_zcull
,
.
init_rop_active_fbps
=
gk104_gr_init_rop_active_fbps
,
.
init_ppc_exceptions
=
gk104_gr_init_ppc_exceptions
,
.
mmio
=
gm107_gr_pack_mmio
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
View file @
02917aa3
...
...
@@ -65,11 +65,7 @@ static int
gm200_gr_init
(
struct
gf100_gr
*
gr
)
{
struct
nvkm_device
*
device
=
gr
->
base
.
engine
.
subdev
.
device
;
const
u32
magicgpc918
=
DIV_ROUND_UP
(
0x00800000
,
gr
->
tpc_total
);
u32
data
[
TPC_MAX
/
8
]
=
{};
u8
tpcnr
[
GPC_MAX
];
int
gpc
,
tpc
,
rop
;
int
i
;
gr
->
func
->
init_gpc_mmu
(
gr
);
...
...
@@ -78,32 +74,8 @@ gm200_gr_init(struct gf100_gr *gr)
gr
->
func
->
init_bios
(
gr
);
gr
->
func
->
init_vsc_stream_master
(
gr
);
gr
->
func
->
init_zcull
(
gr
);
memset
(
data
,
0x00
,
sizeof
(
data
));
memcpy
(
tpcnr
,
gr
->
tpc_nr
,
sizeof
(
gr
->
tpc_nr
));
for
(
i
=
0
,
gpc
=
-
1
;
i
<
gr
->
tpc_total
;
i
++
)
{
do
{
gpc
=
(
gpc
+
1
)
%
gr
->
gpc_nr
;
}
while
(
!
tpcnr
[
gpc
]);
tpc
=
gr
->
tpc_nr
[
gpc
]
-
tpcnr
[
gpc
]
--
;
data
[
i
/
8
]
|=
tpc
<<
((
i
%
8
)
*
4
);
}
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0980
),
data
[
0
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0984
),
data
[
1
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0988
),
data
[
2
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x098c
),
data
[
3
]);
for
(
gpc
=
0
;
gpc
<
gr
->
gpc_nr
;
gpc
++
)
{
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0914
),
gr
->
screen_tile_row_offset
<<
8
|
gr
->
tpc_nr
[
gpc
]);
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0910
),
0x00040000
|
gr
->
tpc_total
);
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0918
),
magicgpc918
);
}
nvkm_wr32
(
device
,
GPC_BCAST
(
0x3fd4
),
magicgpc918
);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x08ac
),
nvkm_rd32
(
device
,
0x100800
));
nvkm_wr32
(
device
,
GPC_BCAST
(
0x033c
),
nvkm_rd32
(
device
,
0x100804
));
...
...
@@ -212,6 +184,7 @@ gm200_gr = {
.
init_gpc_mmu
=
gm200_gr_init_gpc_mmu
,
.
init_bios
=
gm107_gr_init_bios
,
.
init_vsc_stream_master
=
gk104_gr_init_vsc_stream_master
,
.
init_zcull
=
gf117_gr_init_zcull
,
.
init_rop_active_fbps
=
gm200_gr_init_rop_active_fbps
,
.
init_ppc_exceptions
=
gk104_gr_init_ppc_exceptions
,
.
rops
=
gm200_gr_rops
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c
View file @
02917aa3
...
...
@@ -65,6 +65,7 @@ gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
static
const
struct
gf100_gr_func
gm20b_gr
=
{
.
init
=
gk20a_gr_init
,
.
init_zcull
=
gf117_gr_init_zcull
,
.
init_gpc_mmu
=
gm20b_gr_init_gpc_mmu
,
.
init_rop_active_fbps
=
gk104_gr_init_rop_active_fbps
,
.
set_hww_esr_report_mask
=
gm20b_gr_set_hww_esr_report_mask
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c
View file @
02917aa3
...
...
@@ -53,43 +53,15 @@ int
gp100_gr_init
(
struct
gf100_gr
*
gr
)
{
struct
nvkm_device
*
device
=
gr
->
base
.
engine
.
subdev
.
device
;
const
u32
magicgpc918
=
DIV_ROUND_UP
(
0x00800000
,
gr
->
tpc_total
);
u32
data
[
TPC_MAX
/
8
]
=
{};
u8
tpcnr
[
GPC_MAX
];
int
gpc
,
tpc
,
rop
;
int
i
;
gr
->
func
->
init_gpc_mmu
(
gr
);
gf100_gr_mmio
(
gr
,
gr
->
fuc_sw_nonctx
);
gr
->
func
->
init_vsc_stream_master
(
gr
);
gr
->
func
->
init_zcull
(
gr
);
memset
(
data
,
0x00
,
sizeof
(
data
));
memcpy
(
tpcnr
,
gr
->
tpc_nr
,
sizeof
(
gr
->
tpc_nr
));
for
(
i
=
0
,
gpc
=
-
1
;
i
<
gr
->
tpc_total
;
i
++
)
{
do
{
gpc
=
(
gpc
+
1
)
%
gr
->
gpc_nr
;
}
while
(
!
tpcnr
[
gpc
]);
tpc
=
gr
->
tpc_nr
[
gpc
]
-
tpcnr
[
gpc
]
--
;
data
[
i
/
8
]
|=
tpc
<<
((
i
%
8
)
*
4
);
}
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0980
),
data
[
0
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0984
),
data
[
1
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x0988
),
data
[
2
]);
nvkm_wr32
(
device
,
GPC_BCAST
(
0x098c
),
data
[
3
]);
for
(
gpc
=
0
;
gpc
<
gr
->
gpc_nr
;
gpc
++
)
{
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0914
),
gr
->
screen_tile_row_offset
<<
8
|
gr
->
tpc_nr
[
gpc
]);
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0910
),
0x00040000
|
gr
->
tpc_total
);
nvkm_wr32
(
device
,
GPC_UNIT
(
gpc
,
0x0918
),
magicgpc918
);
}
nvkm_wr32
(
device
,
GPC_BCAST
(
0x3fd4
),
magicgpc918
);
gr
->
func
->
init_num_active_ltcs
(
gr
);
gr
->
func
->
init_rop_active_fbps
(
gr
);
...
...
@@ -161,6 +133,7 @@ gp100_gr = {
.
init
=
gp100_gr_init
,
.
init_gpc_mmu
=
gm200_gr_init_gpc_mmu
,
.
init_vsc_stream_master
=
gk104_gr_init_vsc_stream_master
,
.
init_zcull
=
gf117_gr_init_zcull
,
.
init_rop_active_fbps
=
gp100_gr_init_rop_active_fbps
,
.
init_ppc_exceptions
=
gk104_gr_init_ppc_exceptions
,
.
init_num_active_ltcs
=
gp100_gr_init_num_active_ltcs
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c
View file @
02917aa3
...
...
@@ -45,6 +45,7 @@ gp102_gr = {
.
init
=
gp100_gr_init
,
.
init_gpc_mmu
=
gm200_gr_init_gpc_mmu
,
.
init_vsc_stream_master
=
gk104_gr_init_vsc_stream_master
,
.
init_zcull
=
gf117_gr_init_zcull
,
.
init_rop_active_fbps
=
gp100_gr_init_rop_active_fbps
,
.
init_ppc_exceptions
=
gk104_gr_init_ppc_exceptions
,
.
init_swdx_pes_mask
=
gp102_gr_init_swdx_pes_mask
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c
View file @
02917aa3
...
...
@@ -31,6 +31,7 @@ gp107_gr = {
.
init
=
gp100_gr_init
,
.
init_gpc_mmu
=
gm200_gr_init_gpc_mmu
,
.
init_vsc_stream_master
=
gk104_gr_init_vsc_stream_master
,
.
init_zcull
=
gf117_gr_init_zcull
,
.
init_rop_active_fbps
=
gp100_gr_init_rop_active_fbps
,
.
init_ppc_exceptions
=
gk104_gr_init_ppc_exceptions
,
.
init_swdx_pes_mask
=
gp102_gr_init_swdx_pes_mask
,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c
View file @
02917aa3
...
...
@@ -38,6 +38,7 @@ gp10b_gr = {
.
init
=
gp100_gr_init
,
.
init_gpc_mmu
=
gm200_gr_init_gpc_mmu
,
.
init_vsc_stream_master
=
gk104_gr_init_vsc_stream_master
,
.
init_zcull
=
gf117_gr_init_zcull
,
.
init_rop_active_fbps
=
gp100_gr_init_rop_active_fbps
,
.
init_ppc_exceptions
=
gk104_gr_init_ppc_exceptions
,
.
init_num_active_ltcs
=
gp10b_gr_init_num_active_ltcs
,
...
...
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