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Commit 02bae212 authored by Jeff Garzik's avatar Jeff Garzik
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Merge branch 'features' of git://farnsworth.org/dale/linux-2.6-mv643xx_eth into upstream

parents c7ffb6bb c1f395f1
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drivers/net/Kconfig
View file @ 02bae212
...@@ -2371,13 +2371,16 @@ config UGETH_TX_ON_DEMAND ...@@ -2371,13 +2371,16 @@ config UGETH_TX_ON_DEMAND
depends on UCC_GETH depends on UCC_GETH
config MV643XX_ETH config MV643XX_ETH
tristate "MV-643XX Ethernet support" tristate "Marvell Discovery (643XX) and Orion ethernet support"
depends on MV64360 || MV64X60 || (PPC_MULTIPLATFORM && PPC32) depends on MV64360 || MV64X60 || (PPC_MULTIPLATFORM && PPC32) || ARCH_ORION
select MII select MII
help help
This driver supports the gigabit Ethernet on the Marvell MV643XX This driver supports the gigabit ethernet MACs in the
chipset which is used in the Momenco Ocelot C and Jaguar ATX and Marvell Discovery PPC/MIPS chipset family (MV643XX) and
Pegasos II, amongst other PPC and MIPS boards. in the Marvell Orion ARM SoC family.
Some boards that use the Discovery chipset are the Momenco
Ocelot C and Jaguar ATX and Pegasos II.
config QLA3XXX config QLA3XXX
tristate "QLogic QLA3XXX Network Driver Support" tristate "QLogic QLA3XXX Network Driver Support"
......
drivers/net/mv643xx_eth.c
View file @ 02bae212
/* /*
* drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
* Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
* *
* Based on the 64360 driver from: * Based on the 64360 driver from:
...@@ -43,14 +43,567 @@ ...@@ -43,14 +43,567 @@
#include <linux/ethtool.h> #include <linux/ethtool.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/mii.h>
#include <linux/mv643xx_eth.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/types.h> #include <asm/types.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/system.h> #include <asm/system.h>
#include <asm/delay.h> #include <asm/delay.h>
#include "mv643xx_eth.h" #include <asm/dma-mapping.h>
#define MV643XX_CHECKSUM_OFFLOAD_TX
#define MV643XX_NAPI
#define MV643XX_TX_FAST_REFILL
#undef MV643XX_COAL
/*
* Number of RX / TX descriptors on RX / TX rings.
* Note that allocating RX descriptors is done by allocating the RX
* ring AND a preallocated RX buffers (skb's) for each descriptor.
* The TX descriptors only allocates the TX descriptors ring,
* with no pre allocated TX buffers (skb's are allocated by higher layers.
*/
/* Default TX ring size is 1000 descriptors */
#define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
/* Default RX ring size is 400 descriptors */
#define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
#define MV643XX_TX_COAL 100
#ifdef MV643XX_COAL
#define MV643XX_RX_COAL 100
#endif
#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
#else
#define MAX_DESCS_PER_SKB 1
#endif
#define ETH_VLAN_HLEN 4
#define ETH_FCS_LEN 4
#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
#define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
ETH_VLAN_HLEN + ETH_FCS_LEN)
#define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
dma_get_cache_alignment())
/*
* Registers shared between all ports.
*/
#define PHY_ADDR_REG 0x0000
#define SMI_REG 0x0004
/*
* Per-port registers.
*/
#define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10))
#define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10))
#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
#define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10))
#define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10))
#define PORT_STATUS_REG(p) (0x0444 + ((p) << 10))
#define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10))
#define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10))
#define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10))
#define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10))
#define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10))
#define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10))
#define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10))
#define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10))
#define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10))
#define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10))
#define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7))
#define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10))
#define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10))
#define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10))
/* These macros describe Ethernet Port configuration reg (Px_cR) bits */
#define UNICAST_NORMAL_MODE (0 << 0)
#define UNICAST_PROMISCUOUS_MODE (1 << 0)
#define DEFAULT_RX_QUEUE(queue) ((queue) << 1)
#define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4)
#define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7)
#define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
#define RECEIVE_BC_IF_IP (0 << 8)
#define REJECT_BC_IF_IP (1 << 8)
#define RECEIVE_BC_IF_ARP (0 << 9)
#define REJECT_BC_IF_ARP (1 << 9)
#define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12)
#define CAPTURE_TCP_FRAMES_DIS (0 << 14)
#define CAPTURE_TCP_FRAMES_EN (1 << 14)
#define CAPTURE_UDP_FRAMES_DIS (0 << 15)
#define CAPTURE_UDP_FRAMES_EN (1 << 15)
#define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16)
#define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19)
#define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22)
#define PORT_CONFIG_DEFAULT_VALUE \
UNICAST_NORMAL_MODE | \
DEFAULT_RX_QUEUE(0) | \
DEFAULT_RX_ARP_QUEUE(0) | \
RECEIVE_BC_IF_NOT_IP_OR_ARP | \
RECEIVE_BC_IF_IP | \
RECEIVE_BC_IF_ARP | \
CAPTURE_TCP_FRAMES_DIS | \
CAPTURE_UDP_FRAMES_DIS | \
DEFAULT_RX_TCP_QUEUE(0) | \
DEFAULT_RX_UDP_QUEUE(0) | \
DEFAULT_RX_BPDU_QUEUE(0)
/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
#define CLASSIFY_EN (1 << 0)
#define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1)
#define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1)
#define PARTITION_DISABLE (0 << 2)
#define PARTITION_ENABLE (1 << 2)
#define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
SPAN_BPDU_PACKETS_AS_NORMAL | \
PARTITION_DISABLE
/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
#define RIFB (1 << 0)
#define RX_BURST_SIZE_1_64BIT (0 << 1)
#define RX_BURST_SIZE_2_64BIT (1 << 1)
#define RX_BURST_SIZE_4_64BIT (2 << 1)
#define RX_BURST_SIZE_8_64BIT (3 << 1)
#define RX_BURST_SIZE_16_64BIT (4 << 1)
#define BLM_RX_NO_SWAP (1 << 4)
#define BLM_RX_BYTE_SWAP (0 << 4)
#define BLM_TX_NO_SWAP (1 << 5)
#define BLM_TX_BYTE_SWAP (0 << 5)
#define DESCRIPTORS_BYTE_SWAP (1 << 6)
#define DESCRIPTORS_NO_SWAP (0 << 6)
#define IPG_INT_RX(value) (((value) & 0x3fff) << 8)
#define TX_BURST_SIZE_1_64BIT (0 << 22)
#define TX_BURST_SIZE_2_64BIT (1 << 22)
#define TX_BURST_SIZE_4_64BIT (2 << 22)
#define TX_BURST_SIZE_8_64BIT (3 << 22)
#define TX_BURST_SIZE_16_64BIT (4 << 22)
#if defined(__BIG_ENDIAN)
#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
RX_BURST_SIZE_4_64BIT | \
IPG_INT_RX(0) | \
TX_BURST_SIZE_4_64BIT
#elif defined(__LITTLE_ENDIAN)
#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
RX_BURST_SIZE_4_64BIT | \
BLM_RX_NO_SWAP | \
BLM_TX_NO_SWAP | \
IPG_INT_RX(0) | \
TX_BURST_SIZE_4_64BIT
#else
#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
#endif
/* These macros describe Ethernet Port serial control reg (PSCR) bits */
#define SERIAL_PORT_DISABLE (0 << 0)
#define SERIAL_PORT_ENABLE (1 << 0)
#define DO_NOT_FORCE_LINK_PASS (0 << 1)
#define FORCE_LINK_PASS (1 << 1)
#define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2)
#define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2)
#define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3)
#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
#define ADV_NO_FLOW_CTRL (0 << 4)
#define ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
#define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5)
#define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
#define FORCE_BP_MODE_NO_JAM (0 << 7)
#define FORCE_BP_MODE_JAM_TX (1 << 7)
#define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7)
#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
#define FORCE_LINK_FAIL (0 << 10)
#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
#define RETRANSMIT_16_ATTEMPTS (0 << 11)
#define RETRANSMIT_FOREVER (1 << 11)
#define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13)
#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
#define DTE_ADV_0 (0 << 14)
#define DTE_ADV_1 (1 << 14)
#define DISABLE_AUTO_NEG_BYPASS (0 << 15)
#define ENABLE_AUTO_NEG_BYPASS (1 << 15)
#define AUTO_NEG_NO_CHANGE (0 << 16)
#define RESTART_AUTO_NEG (1 << 16)
#define MAX_RX_PACKET_1518BYTE (0 << 17)
#define MAX_RX_PACKET_1522BYTE (1 << 17)
#define MAX_RX_PACKET_1552BYTE (2 << 17)
#define MAX_RX_PACKET_9022BYTE (3 << 17)
#define MAX_RX_PACKET_9192BYTE (4 << 17)
#define MAX_RX_PACKET_9700BYTE (5 << 17)
#define MAX_RX_PACKET_MASK (7 << 17)
#define CLR_EXT_LOOPBACK (0 << 20)
#define SET_EXT_LOOPBACK (1 << 20)
#define SET_HALF_DUPLEX_MODE (0 << 21)
#define SET_FULL_DUPLEX_MODE (1 << 21)
#define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22)
#define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
#define SET_GMII_SPEED_TO_10_100 (0 << 23)
#define SET_GMII_SPEED_TO_1000 (1 << 23)
#define SET_MII_SPEED_TO_10 (0 << 24)
#define SET_MII_SPEED_TO_100 (1 << 24)
#define PORT_SERIAL_CONTROL_DEFAULT_VALUE \
DO_NOT_FORCE_LINK_PASS | \
ENABLE_AUTO_NEG_FOR_DUPLX | \
DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
ADV_SYMMETRIC_FLOW_CTRL | \
FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* reserved */ | \
DO_NOT_FORCE_LINK_FAIL | \
RETRANSMIT_16_ATTEMPTS | \
ENABLE_AUTO_NEG_SPEED_GMII | \
DTE_ADV_0 | \
DISABLE_AUTO_NEG_BYPASS | \
AUTO_NEG_NO_CHANGE | \
MAX_RX_PACKET_9700BYTE | \
CLR_EXT_LOOPBACK | \
SET_FULL_DUPLEX_MODE | \
ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
/* These macros describe Ethernet Serial Status reg (PSR) bits */
#define PORT_STATUS_MODE_10_BIT (1 << 0)
#define PORT_STATUS_LINK_UP (1 << 1)
#define PORT_STATUS_FULL_DUPLEX (1 << 2)
#define PORT_STATUS_FLOW_CONTROL (1 << 3)
#define PORT_STATUS_GMII_1000 (1 << 4)
#define PORT_STATUS_MII_100 (1 << 5)
/* PSR bit 6 is undocumented */
#define PORT_STATUS_TX_IN_PROGRESS (1 << 7)
#define PORT_STATUS_AUTONEG_BYPASSED (1 << 8)
#define PORT_STATUS_PARTITION (1 << 9)
#define PORT_STATUS_TX_FIFO_EMPTY (1 << 10)
/* PSR bits 11-31 are reserved */
#define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
#define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
#define DESC_SIZE 64
#define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
#define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
#define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
#define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
#define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
#define ETH_INT_CAUSE_EXT 0x00000002
#define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
#define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
#define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
#define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
#define ETH_INT_CAUSE_PHY 0x00010000
#define ETH_INT_CAUSE_STATE 0x00100000
#define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
ETH_INT_CAUSE_STATE)
#define ETH_INT_MASK_ALL 0x00000000
#define ETH_INT_MASK_ALL_EXT 0x00000000
#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
#define PHY_WAIT_MICRO_SECONDS 10
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Gigabit Ethernet Unit Global Registers */
/* MIB Counters register definitions */
#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
#define ETH_MIB_FRAMES_64_OCTETS 0x20
#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
#define ETH_MIB_GOOD_FRAMES_SENT 0x40
#define ETH_MIB_EXCESSIVE_COLLISION 0x44
#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
#define ETH_MIB_FC_SENT 0x54
#define ETH_MIB_GOOD_FC_RECEIVED 0x58
#define ETH_MIB_BAD_FC_RECEIVED 0x5c
#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
#define ETH_MIB_OVERSIZE_RECEIVED 0x68
#define ETH_MIB_JABBER_RECEIVED 0x6c
#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
#define ETH_MIB_BAD_CRC_EVENT 0x74
#define ETH_MIB_COLLISION 0x78
#define ETH_MIB_LATE_COLLISION 0x7c
/* Port serial status reg (PSR) */
#define ETH_INTERFACE_PCM 0x00000001
#define ETH_LINK_IS_UP 0x00000002
#define ETH_PORT_AT_FULL_DUPLEX 0x00000004
#define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
#define ETH_GMII_SPEED_1000 0x00000010
#define ETH_MII_SPEED_100 0x00000020
#define ETH_TX_IN_PROGRESS 0x00000080
#define ETH_BYPASS_ACTIVE 0x00000100
#define ETH_PORT_AT_PARTITION_STATE 0x00000200
#define ETH_PORT_TX_FIFO_EMPTY 0x00000400
/* SMI reg */
#define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
#define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
#define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
/* Interrupt Cause Register Bit Definitions */
/* SDMA command status fields macros */
/* Tx & Rx descriptors status */
#define ETH_ERROR_SUMMARY 0x00000001
/* Tx & Rx descriptors command */
#define ETH_BUFFER_OWNED_BY_DMA 0x80000000
/* Tx descriptors status */
#define ETH_LC_ERROR 0
#define ETH_UR_ERROR 0x00000002
#define ETH_RL_ERROR 0x00000004
#define ETH_LLC_SNAP_FORMAT 0x00000200
/* Rx descriptors status */
#define ETH_OVERRUN_ERROR 0x00000002
#define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
#define ETH_RESOURCE_ERROR 0x00000006
#define ETH_VLAN_TAGGED 0x00080000
#define ETH_BPDU_FRAME 0x00100000
#define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
#define ETH_OTHER_FRAME_TYPE 0x00400000
#define ETH_LAYER_2_IS_ETH_V_2 0x00800000
#define ETH_FRAME_TYPE_IP_V_4 0x01000000
#define ETH_FRAME_HEADER_OK 0x02000000
#define ETH_RX_LAST_DESC 0x04000000
#define ETH_RX_FIRST_DESC 0x08000000
#define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
#define ETH_RX_ENABLE_INTERRUPT 0x20000000
#define ETH_LAYER_4_CHECKSUM_OK 0x40000000
/* Rx descriptors byte count */
#define ETH_FRAME_FRAGMENTED 0x00000004
/* Tx descriptors command */
#define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
#define ETH_FRAME_SET_TO_VLAN 0x00008000
#define ETH_UDP_FRAME 0x00010000
#define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
#define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
#define ETH_ZERO_PADDING 0x00080000
#define ETH_TX_LAST_DESC 0x00100000
#define ETH_TX_FIRST_DESC 0x00200000
#define ETH_GEN_CRC 0x00400000
#define ETH_TX_ENABLE_INTERRUPT 0x00800000
#define ETH_AUTO_MODE 0x40000000
#define ETH_TX_IHL_SHIFT 11
/* typedefs */
typedef enum _eth_func_ret_status {
ETH_OK, /* Returned as expected. */
ETH_ERROR, /* Fundamental error. */
ETH_RETRY, /* Could not process request. Try later.*/
ETH_END_OF_JOB, /* Ring has nothing to process. */
ETH_QUEUE_FULL, /* Ring resource error. */
ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
} ETH_FUNC_RET_STATUS;
typedef enum _eth_target {
ETH_TARGET_DRAM,
ETH_TARGET_DEVICE,
ETH_TARGET_CBS,
ETH_TARGET_PCI0,
ETH_TARGET_PCI1
} ETH_TARGET;
/* These are for big-endian machines. Little endian needs different
* definitions.
*/
#if defined(__BIG_ENDIAN)
struct eth_rx_desc {
u16 byte_cnt; /* Descriptor buffer byte count */
u16 buf_size; /* Buffer size */
u32 cmd_sts; /* Descriptor command status */
u32 next_desc_ptr; /* Next descriptor pointer */
u32 buf_ptr; /* Descriptor buffer pointer */
};
struct eth_tx_desc {
u16 byte_cnt; /* buffer byte count */
u16 l4i_chk; /* CPU provided TCP checksum */
u32 cmd_sts; /* Command/status field */
u32 next_desc_ptr; /* Pointer to next descriptor */
u32 buf_ptr; /* pointer to buffer for this descriptor*/
};
#elif defined(__LITTLE_ENDIAN)
struct eth_rx_desc {
u32 cmd_sts; /* Descriptor command status */
u16 buf_size; /* Buffer size */
u16 byte_cnt; /* Descriptor buffer byte count */
u32 buf_ptr; /* Descriptor buffer pointer */
u32 next_desc_ptr; /* Next descriptor pointer */
};
struct eth_tx_desc {
u32 cmd_sts; /* Command/status field */
u16 l4i_chk; /* CPU provided TCP checksum */
u16 byte_cnt; /* buffer byte count */
u32 buf_ptr; /* pointer to buffer for this descriptor*/
u32 next_desc_ptr; /* Pointer to next descriptor */
};
#else
#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
#endif
/* Unified struct for Rx and Tx operations. The user is not required to */
/* be familier with neither Tx nor Rx descriptors. */
struct pkt_info {
unsigned short byte_cnt; /* Descriptor buffer byte count */
unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
unsigned int cmd_sts; /* Descriptor command status */
dma_addr_t buf_ptr; /* Descriptor buffer pointer */
struct sk_buff *return_info; /* User resource return information */
};
/* Ethernet port specific information */
struct mv643xx_mib_counters {
u64 good_octets_received;
u32 bad_octets_received;
u32 internal_mac_transmit_err;
u32 good_frames_received;
u32 bad_frames_received;
u32 broadcast_frames_received;
u32 multicast_frames_received;
u32 frames_64_octets;
u32 frames_65_to_127_octets;
u32 frames_128_to_255_octets;
u32 frames_256_to_511_octets;
u32 frames_512_to_1023_octets;
u32 frames_1024_to_max_octets;
u64 good_octets_sent;
u32 good_frames_sent;
u32 excessive_collision;
u32 multicast_frames_sent;
u32 broadcast_frames_sent;
u32 unrec_mac_control_received;
u32 fc_sent;
u32 good_fc_received;
u32 bad_fc_received;
u32 undersize_received;
u32 fragments_received;
u32 oversize_received;
u32 jabber_received;
u32 mac_receive_error;
u32 bad_crc_event;
u32 collision;
u32 late_collision;
};
struct mv643xx_private {
int port_num; /* User Ethernet port number */
u32 rx_sram_addr; /* Base address of rx sram area */
u32 rx_sram_size; /* Size of rx sram area */
u32 tx_sram_addr; /* Base address of tx sram area */
u32 tx_sram_size; /* Size of tx sram area */
int rx_resource_err; /* Rx ring resource error flag */
/* Tx/Rx rings managment indexes fields. For driver use */
/* Next available and first returning Rx resource */
int rx_curr_desc_q, rx_used_desc_q;
/* Next available and first returning Tx resource */
int tx_curr_desc_q, tx_used_desc_q;
#ifdef MV643XX_TX_FAST_REFILL
u32 tx_clean_threshold;
#endif
struct eth_rx_desc *p_rx_desc_area;
dma_addr_t rx_desc_dma;
int rx_desc_area_size;
struct sk_buff **rx_skb;
struct eth_tx_desc *p_tx_desc_area;
dma_addr_t tx_desc_dma;
int tx_desc_area_size;
struct sk_buff **tx_skb;
struct work_struct tx_timeout_task;
struct net_device *dev;
struct napi_struct napi;
struct net_device_stats stats;
struct mv643xx_mib_counters mib_counters;
spinlock_t lock;
/* Size of Tx Ring per queue */
int tx_ring_size;
/* Number of tx descriptors in use */
int tx_desc_count;
/* Size of Rx Ring per queue */
int rx_ring_size;
/* Number of rx descriptors in use */
int rx_desc_count;
/*
* Used in case RX Ring is empty, which can be caused when
* system does not have resources (skb's)
*/
struct timer_list timeout;
u32 rx_int_coal;
u32 tx_int_coal;
struct mii_if_info mii;
};
/* Static function declarations */ /* Static function declarations */
static void eth_port_init(struct mv643xx_private *mp);
static void eth_port_reset(unsigned int eth_port_num);
static void eth_port_start(struct net_device *dev);
static void ethernet_phy_reset(unsigned int eth_port_num);
static void eth_port_write_smi_reg(unsigned int eth_port_num,
unsigned int phy_reg, unsigned int value);
static void eth_port_read_smi_reg(unsigned int eth_port_num,
unsigned int phy_reg, unsigned int *value);
static void eth_clear_mib_counters(unsigned int eth_port_num);
static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
struct pkt_info *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
struct pkt_info *p_pkt_info);
static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr); static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr);
static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr); static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr);
static void eth_port_set_multicast_list(struct net_device *); static void eth_port_set_multicast_list(struct net_device *);
...@@ -78,26 +631,19 @@ static const struct ethtool_ops mv643xx_ethtool_ops; ...@@ -78,26 +631,19 @@ static const struct ethtool_ops mv643xx_ethtool_ops;
static char mv643xx_driver_name[] = "mv643xx_eth"; static char mv643xx_driver_name[] = "mv643xx_eth";
static char mv643xx_driver_version[] = "1.0"; static char mv643xx_driver_version[] = "1.0";
static void __iomem *mv643xx_eth_shared_base; static void __iomem *mv643xx_eth_base;
/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */ /* used to protect SMI_REG, which is shared across ports */
static DEFINE_SPINLOCK(mv643xx_eth_phy_lock); static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
static inline u32 mv_read(int offset) static inline u32 mv_read(int offset)
{ {
void __iomem *reg_base; return readl(mv643xx_eth_base + offset);
reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
return readl(reg_base + offset);
} }
static inline void mv_write(int offset, u32 data) static inline void mv_write(int offset, u32 data)
{ {
void __iomem *reg_base; writel(data, mv643xx_eth_base + offset);
reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
writel(data, reg_base + offset);
} }
/* /*
...@@ -221,12 +767,12 @@ static void mv643xx_eth_set_rx_mode(struct net_device *dev) ...@@ -221,12 +767,12 @@ static void mv643xx_eth_set_rx_mode(struct net_device *dev)
struct mv643xx_private *mp = netdev_priv(dev); struct mv643xx_private *mp = netdev_priv(dev);
u32 config_reg; u32 config_reg;
config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num)); config_reg = mv_read(PORT_CONFIG_REG(mp->port_num));
if (dev->flags & IFF_PROMISC) if (dev->flags & IFF_PROMISC)
config_reg |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE; config_reg |= (u32) UNICAST_PROMISCUOUS_MODE;
else else
config_reg &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE; config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE;
mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), config_reg); mv_write(PORT_CONFIG_REG(mp->port_num), config_reg);
eth_port_set_multicast_list(dev); eth_port_set_multicast_list(dev);
} }
...@@ -462,41 +1008,37 @@ static void mv643xx_eth_update_pscr(struct net_device *dev, ...@@ -462,41 +1008,37 @@ static void mv643xx_eth_update_pscr(struct net_device *dev,
u32 o_pscr, n_pscr; u32 o_pscr, n_pscr;
unsigned int queues; unsigned int queues;
o_pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); o_pscr = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
n_pscr = o_pscr; n_pscr = o_pscr;
/* clear speed, duplex and rx buffer size fields */ /* clear speed, duplex and rx buffer size fields */
n_pscr &= ~(MV643XX_ETH_SET_MII_SPEED_TO_100 | n_pscr &= ~(SET_MII_SPEED_TO_100 |
MV643XX_ETH_SET_GMII_SPEED_TO_1000 | SET_GMII_SPEED_TO_1000 |
MV643XX_ETH_SET_FULL_DUPLEX_MODE | SET_FULL_DUPLEX_MODE |
MV643XX_ETH_MAX_RX_PACKET_MASK); MAX_RX_PACKET_MASK);
if (ecmd->duplex == DUPLEX_FULL) if (ecmd->duplex == DUPLEX_FULL)
n_pscr |= MV643XX_ETH_SET_FULL_DUPLEX_MODE; n_pscr |= SET_FULL_DUPLEX_MODE;
if (ecmd->speed == SPEED_1000) if (ecmd->speed == SPEED_1000)
n_pscr |= MV643XX_ETH_SET_GMII_SPEED_TO_1000 | n_pscr |= SET_GMII_SPEED_TO_1000 |
MV643XX_ETH_MAX_RX_PACKET_9700BYTE; MAX_RX_PACKET_9700BYTE;
else { else {
if (ecmd->speed == SPEED_100) if (ecmd->speed == SPEED_100)
n_pscr |= MV643XX_ETH_SET_MII_SPEED_TO_100; n_pscr |= SET_MII_SPEED_TO_100;
n_pscr |= MV643XX_ETH_MAX_RX_PACKET_1522BYTE; n_pscr |= MAX_RX_PACKET_1522BYTE;
} }
if (n_pscr != o_pscr) { if (n_pscr != o_pscr) {
if ((o_pscr & MV643XX_ETH_SERIAL_PORT_ENABLE) == 0) if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
n_pscr);
else { else {
queues = mv643xx_eth_port_disable_tx(port_num); queues = mv643xx_eth_port_disable_tx(port_num);
o_pscr &= ~MV643XX_ETH_SERIAL_PORT_ENABLE; o_pscr &= ~SERIAL_PORT_ENABLE;
mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), mv_write(PORT_SERIAL_CONTROL_REG(port_num), o_pscr);
o_pscr); mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
n_pscr);
mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
n_pscr);
if (queues) if (queues)
mv643xx_eth_port_enable_tx(port_num, queues); mv643xx_eth_port_enable_tx(port_num, queues);
} }
...@@ -522,13 +1064,13 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) ...@@ -522,13 +1064,13 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
unsigned int port_num = mp->port_num; unsigned int port_num = mp->port_num;
/* Read interrupt cause registers */ /* Read interrupt cause registers */
eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) & eth_int_cause = mv_read(INTERRUPT_CAUSE_REG(port_num)) &
ETH_INT_UNMASK_ALL; ETH_INT_UNMASK_ALL;
if (eth_int_cause & ETH_INT_CAUSE_EXT) { if (eth_int_cause & ETH_INT_CAUSE_EXT) {
eth_int_cause_ext = mv_read( eth_int_cause_ext = mv_read(
MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) & INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
ETH_INT_UNMASK_ALL_EXT; ETH_INT_UNMASK_ALL_EXT;
mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num),
~eth_int_cause_ext); ~eth_int_cause_ext);
} }
...@@ -556,10 +1098,10 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) ...@@ -556,10 +1098,10 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
#ifdef MV643XX_NAPI #ifdef MV643XX_NAPI
if (eth_int_cause & ETH_INT_CAUSE_RX) { if (eth_int_cause & ETH_INT_CAUSE_RX) {
/* schedule the NAPI poll routine to maintain port */ /* schedule the NAPI poll routine to maintain port */
mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
ETH_INT_MASK_ALL);
/* wait for previous write to complete */ /* wait for previous write to complete */
mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); mv_read(INTERRUPT_MASK_REG(port_num));
netif_rx_schedule(dev, &mp->napi); netif_rx_schedule(dev, &mp->napi);
} }
...@@ -611,9 +1153,9 @@ static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num, ...@@ -611,9 +1153,9 @@ static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
unsigned int coal = ((t_clk / 1000000) * delay) / 64; unsigned int coal = ((t_clk / 1000000) * delay) / 64;
/* Set RX Coalescing mechanism */ /* Set RX Coalescing mechanism */
mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num), mv_write(SDMA_CONFIG_REG(eth_port_num),
((coal & 0x3fff) << 8) | ((coal & 0x3fff) << 8) |
(mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num)) (mv_read(SDMA_CONFIG_REG(eth_port_num))
& 0xffc000ff)); & 0xffc000ff));
return coal; return coal;
...@@ -649,8 +1191,7 @@ static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num, ...@@ -649,8 +1191,7 @@ static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
unsigned int coal; unsigned int coal;
coal = ((t_clk / 1000000) * delay) / 64; coal = ((t_clk / 1000000) * delay) / 64;
/* Set TX Coalescing mechanism */ /* Set TX Coalescing mechanism */
mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num), mv_write(TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num), coal << 4);
coal << 4);
return coal; return coal;
} }
...@@ -786,10 +1327,10 @@ static int mv643xx_eth_open(struct net_device *dev) ...@@ -786,10 +1327,10 @@ static int mv643xx_eth_open(struct net_device *dev)
int err; int err;
/* Clear any pending ethernet port interrupts */ /* Clear any pending ethernet port interrupts */
mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0); mv_write(INTERRUPT_CAUSE_REG(port_num), 0);
mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
/* wait for previous write to complete */ /* wait for previous write to complete */
mv_read (MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)); mv_read (INTERRUPT_CAUSE_EXTEND_REG(port_num));
err = request_irq(dev->irq, mv643xx_eth_int_handler, err = request_irq(dev->irq, mv643xx_eth_int_handler,
IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
...@@ -896,11 +1437,10 @@ static int mv643xx_eth_open(struct net_device *dev) ...@@ -896,11 +1437,10 @@ static int mv643xx_eth_open(struct net_device *dev)
eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL); eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
/* Unmask phy and link status changes interrupts */ /* Unmask phy and link status changes interrupts */
mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), mv_write(INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT);
ETH_INT_UNMASK_ALL_EXT);
/* Unmask RX buffer and TX end interrupt */ /* Unmask RX buffer and TX end interrupt */
mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
return 0; return 0;
...@@ -980,9 +1520,9 @@ static int mv643xx_eth_stop(struct net_device *dev) ...@@ -980,9 +1520,9 @@ static int mv643xx_eth_stop(struct net_device *dev)
unsigned int port_num = mp->port_num; unsigned int port_num = mp->port_num;
/* Mask all interrupts on ethernet port */ /* Mask all interrupts on ethernet port */
mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
/* wait for previous write to complete */ /* wait for previous write to complete */
mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); mv_read(INTERRUPT_MASK_REG(port_num));
#ifdef MV643XX_NAPI #ifdef MV643XX_NAPI
napi_disable(&mp->napi); napi_disable(&mp->napi);
...@@ -1021,16 +1561,15 @@ static int mv643xx_poll(struct napi_struct *napi, int budget) ...@@ -1021,16 +1561,15 @@ static int mv643xx_poll(struct napi_struct *napi, int budget)
#endif #endif
work_done = 0; work_done = 0;
if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) if ((mv_read(RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
!= (u32) mp->rx_used_desc_q) != (u32) mp->rx_used_desc_q)
work_done = mv643xx_eth_receive_queue(dev, budget); work_done = mv643xx_eth_receive_queue(dev, budget);
if (work_done < budget) { if (work_done < budget) {
netif_rx_complete(dev, napi); netif_rx_complete(dev, napi);
mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0); mv_write(INTERRUPT_CAUSE_REG(port_num), 0);
mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
ETH_INT_UNMASK_ALL);
} }
return work_done; return work_done;
...@@ -1233,13 +1772,13 @@ static void mv643xx_netpoll(struct net_device *netdev) ...@@ -1233,13 +1772,13 @@ static void mv643xx_netpoll(struct net_device *netdev)
struct mv643xx_private *mp = netdev_priv(netdev); struct mv643xx_private *mp = netdev_priv(netdev);
int port_num = mp->port_num; int port_num = mp->port_num;
mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
/* wait for previous write to complete */ /* wait for previous write to complete */
mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); mv_read(INTERRUPT_MASK_REG(port_num));
mv643xx_eth_int_handler(netdev->irq, netdev); mv643xx_eth_int_handler(netdev->irq, netdev);
mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
} }
#endif #endif
...@@ -1357,8 +1896,8 @@ static int mv643xx_eth_probe(struct platform_device *pdev) ...@@ -1357,8 +1896,8 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
/* set default config values */ /* set default config values */
eth_port_uc_addr_get(port_num, dev->dev_addr); eth_port_uc_addr_get(port_num, dev->dev_addr);
mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE; mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE; mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
if (is_valid_ether_addr(pd->mac_addr)) if (is_valid_ether_addr(pd->mac_addr))
memcpy(dev->dev_addr, pd->mac_addr, 6); memcpy(dev->dev_addr, pd->mac_addr, 6);
...@@ -1470,9 +2009,8 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev) ...@@ -1470,9 +2009,8 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
if (res == NULL) if (res == NULL)
return -ENODEV; return -ENODEV;
mv643xx_eth_shared_base = ioremap(res->start, mv643xx_eth_base = ioremap(res->start, res->end - res->start + 1);
MV643XX_ETH_SHARED_REGS_SIZE); if (mv643xx_eth_base == NULL)
if (mv643xx_eth_shared_base == NULL)
return -ENOMEM; return -ENOMEM;
return 0; return 0;
...@@ -1481,8 +2019,8 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev) ...@@ -1481,8 +2019,8 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
static int mv643xx_eth_shared_remove(struct platform_device *pdev) static int mv643xx_eth_shared_remove(struct platform_device *pdev)
{ {
iounmap(mv643xx_eth_shared_base); iounmap(mv643xx_eth_base);
mv643xx_eth_shared_base = NULL; mv643xx_eth_base = NULL;
return 0; return 0;
} }
...@@ -1494,8 +2032,8 @@ static void mv643xx_eth_shutdown(struct platform_device *pdev) ...@@ -1494,8 +2032,8 @@ static void mv643xx_eth_shutdown(struct platform_device *pdev)
unsigned int port_num = mp->port_num; unsigned int port_num = mp->port_num;
/* Mask all interrupts on ethernet port */ /* Mask all interrupts on ethernet port */
mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0); mv_write(INTERRUPT_MASK_REG(port_num), 0);
mv_read (MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); mv_read (INTERRUPT_MASK_REG(port_num));
eth_port_reset(port_num); eth_port_reset(port_num);
} }
...@@ -1762,49 +2300,49 @@ static void eth_port_start(struct net_device *dev) ...@@ -1762,49 +2300,49 @@ static void eth_port_start(struct net_device *dev)
/* Assignment of Tx CTRP of given queue */ /* Assignment of Tx CTRP of given queue */
tx_curr_desc = mp->tx_curr_desc_q; tx_curr_desc = mp->tx_curr_desc_q;
mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num), mv_write(TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
(u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc)); (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
/* Assignment of Rx CRDP of given queue */ /* Assignment of Rx CRDP of given queue */
rx_curr_desc = mp->rx_curr_desc_q; rx_curr_desc = mp->rx_curr_desc_q;
mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num), mv_write(RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
(u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc)); (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
/* Add the assigned Ethernet address to the port's address table */ /* Add the assigned Ethernet address to the port's address table */
eth_port_uc_addr_set(port_num, dev->dev_addr); eth_port_uc_addr_set(port_num, dev->dev_addr);
/* Assign port configuration and command. */ /* Assign port configuration and command. */
mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mv_write(PORT_CONFIG_REG(port_num),
MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE); PORT_CONFIG_DEFAULT_VALUE);
mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num), mv_write(PORT_CONFIG_EXTEND_REG(port_num),
MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE); PORT_CONFIG_EXTEND_DEFAULT_VALUE);
pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); pscr = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
pscr &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | MV643XX_ETH_FORCE_LINK_PASS); pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr); mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
pscr |= MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII | DISABLE_AUTO_NEG_SPEED_GMII |
MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX | DISABLE_AUTO_NEG_FOR_DUPLX |
MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | DO_NOT_FORCE_LINK_FAIL |
MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED; SERIAL_PORT_CONTROL_RESERVED;
mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr); mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
pscr |= MV643XX_ETH_SERIAL_PORT_ENABLE; pscr |= SERIAL_PORT_ENABLE;
mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr); mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
/* Assign port SDMA configuration */ /* Assign port SDMA configuration */
mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num), mv_write(SDMA_CONFIG_REG(port_num),
MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE); PORT_SDMA_CONFIG_DEFAULT_VALUE);
/* Enable port Rx. */ /* Enable port Rx. */
mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED); mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED);
/* Disable port bandwidth limits by clearing MTU register */ /* Disable port bandwidth limits by clearing MTU register */
mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0); mv_write(MAXIMUM_TRANSMIT_UNIT(port_num), 0);
/* save phy settings across reset */ /* save phy settings across reset */
mv643xx_get_settings(dev, &ethtool_cmd); mv643xx_get_settings(dev, &ethtool_cmd);
...@@ -1825,11 +2363,11 @@ static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr) ...@@ -1825,11 +2363,11 @@ static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr)
mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
(p_addr[3] << 0); (p_addr[3] << 0);
mv_write(MV643XX_ETH_MAC_ADDR_LOW(port_num), mac_l); mv_write(MAC_ADDR_LOW(port_num), mac_l);
mv_write(MV643XX_ETH_MAC_ADDR_HIGH(port_num), mac_h); mv_write(MAC_ADDR_HIGH(port_num), mac_h);
/* Accept frames with this address */ /* Accept frames with this address */
table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port_num); table = DA_FILTER_UNICAST_TABLE_BASE(port_num);
eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f); eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
} }
...@@ -1841,8 +2379,8 @@ static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr) ...@@ -1841,8 +2379,8 @@ static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr)
unsigned int mac_h; unsigned int mac_h;
unsigned int mac_l; unsigned int mac_l;
mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(port_num)); mac_h = mv_read(MAC_ADDR_HIGH(port_num));
mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(port_num)); mac_l = mv_read(MAC_ADDR_LOW(port_num));
p_addr[0] = (mac_h >> 24) & 0xff; p_addr[0] = (mac_h >> 24) & 0xff;
p_addr[1] = (mac_h >> 16) & 0xff; p_addr[1] = (mac_h >> 16) & 0xff;
...@@ -1902,7 +2440,7 @@ static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr) ...@@ -1902,7 +2440,7 @@ static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
(p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
(eth_port_num); (eth_port_num);
eth_port_set_filter_table_entry(table, p_addr[5]); eth_port_set_filter_table_entry(table, p_addr[5]);
return; return;
...@@ -1976,7 +2514,7 @@ static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr) ...@@ -1976,7 +2514,7 @@ static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
for (i = 0; i < 8; i++) for (i = 0; i < 8; i++)
crc_result = crc_result | (crc[i] << i); crc_result = crc_result | (crc[i] << i);
table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num); table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
eth_port_set_filter_table_entry(table, crc_result); eth_port_set_filter_table_entry(table, crc_result);
} }
...@@ -2006,7 +2544,7 @@ static void eth_port_set_multicast_list(struct net_device *dev) ...@@ -2006,7 +2544,7 @@ static void eth_port_set_multicast_list(struct net_device *dev)
* 3-1 Queue ETH_Q0=0 * 3-1 Queue ETH_Q0=0
* 7-4 Reserved = 0; * 7-4 Reserved = 0;
*/ */
mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
/* Set all entries in DA filter other multicast /* Set all entries in DA filter other multicast
* table (Ex_dFOMT) * table (Ex_dFOMT)
...@@ -2016,7 +2554,7 @@ static void eth_port_set_multicast_list(struct net_device *dev) ...@@ -2016,7 +2554,7 @@ static void eth_port_set_multicast_list(struct net_device *dev)
* 3-1 Queue ETH_Q0=0 * 3-1 Queue ETH_Q0=0
* 7-4 Reserved = 0; * 7-4 Reserved = 0;
*/ */
mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
} }
return; return;
} }
...@@ -2026,11 +2564,11 @@ static void eth_port_set_multicast_list(struct net_device *dev) ...@@ -2026,11 +2564,11 @@ static void eth_port_set_multicast_list(struct net_device *dev)
*/ */
for (table_index = 0; table_index <= 0xFC; table_index += 4) { for (table_index = 0; table_index <= 0xFC; table_index += 4) {
/* Clear DA filter special multicast table (Ex_dFSMT) */ /* Clear DA filter special multicast table (Ex_dFSMT) */
mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
(eth_port_num) + table_index, 0); (eth_port_num) + table_index, 0);
/* Clear DA filter other multicast table (Ex_dFOMT) */ /* Clear DA filter other multicast table (Ex_dFOMT) */
mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE
(eth_port_num) + table_index, 0); (eth_port_num) + table_index, 0);
} }
...@@ -2064,15 +2602,15 @@ static void eth_port_init_mac_tables(unsigned int eth_port_num) ...@@ -2064,15 +2602,15 @@ static void eth_port_init_mac_tables(unsigned int eth_port_num)
/* Clear DA filter unicast table (Ex_dFUT) */ /* Clear DA filter unicast table (Ex_dFUT) */
for (table_index = 0; table_index <= 0xC; table_index += 4) for (table_index = 0; table_index <= 0xC; table_index += 4)
mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE mv_write(DA_FILTER_UNICAST_TABLE_BASE
(eth_port_num) + table_index, 0); (eth_port_num) + table_index, 0);
for (table_index = 0; table_index <= 0xFC; table_index += 4) { for (table_index = 0; table_index <= 0xFC; table_index += 4) {
/* Clear DA filter special multicast table (Ex_dFSMT) */ /* Clear DA filter special multicast table (Ex_dFSMT) */
mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
(eth_port_num) + table_index, 0); (eth_port_num) + table_index, 0);
/* Clear DA filter other multicast table (Ex_dFOMT) */ /* Clear DA filter other multicast table (Ex_dFOMT) */
mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE
(eth_port_num) + table_index, 0); (eth_port_num) + table_index, 0);
} }
} }
...@@ -2101,12 +2639,12 @@ static void eth_clear_mib_counters(unsigned int eth_port_num) ...@@ -2101,12 +2639,12 @@ static void eth_clear_mib_counters(unsigned int eth_port_num)
/* Perform dummy reads from MIB counters */ /* Perform dummy reads from MIB counters */
for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
i += 4) i += 4)
mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i); mv_read(MIB_COUNTERS_BASE(eth_port_num) + i);
} }
static inline u32 read_mib(struct mv643xx_private *mp, int offset) static inline u32 read_mib(struct mv643xx_private *mp, int offset)
{ {
return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset); return mv_read(MIB_COUNTERS_BASE(mp->port_num) + offset);
} }
static void eth_update_mib_counters(struct mv643xx_private *mp) static void eth_update_mib_counters(struct mv643xx_private *mp)
...@@ -2191,7 +2729,7 @@ static int ethernet_phy_get(unsigned int eth_port_num) ...@@ -2191,7 +2729,7 @@ static int ethernet_phy_get(unsigned int eth_port_num)
{ {
unsigned int reg_data; unsigned int reg_data;
reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG); reg_data = mv_read(PHY_ADDR_REG);
return ((reg_data >> (5 * eth_port_num)) & 0x1f); return ((reg_data >> (5 * eth_port_num)) & 0x1f);
} }
...@@ -2218,10 +2756,10 @@ static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr) ...@@ -2218,10 +2756,10 @@ static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
u32 reg_data; u32 reg_data;
int addr_shift = 5 * eth_port_num; int addr_shift = 5 * eth_port_num;
reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG); reg_data = mv_read(PHY_ADDR_REG);
reg_data &= ~(0x1f << addr_shift); reg_data &= ~(0x1f << addr_shift);
reg_data |= (phy_addr & 0x1f) << addr_shift; reg_data |= (phy_addr & 0x1f) << addr_shift;
mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data); mv_write(PHY_ADDR_REG, reg_data);
} }
/* /*
...@@ -2259,13 +2797,13 @@ static void ethernet_phy_reset(unsigned int eth_port_num) ...@@ -2259,13 +2797,13 @@ static void ethernet_phy_reset(unsigned int eth_port_num)
static void mv643xx_eth_port_enable_tx(unsigned int port_num, static void mv643xx_eth_port_enable_tx(unsigned int port_num,
unsigned int queues) unsigned int queues)
{ {
mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), queues); mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num), queues);
} }
static void mv643xx_eth_port_enable_rx(unsigned int port_num, static void mv643xx_eth_port_enable_rx(unsigned int port_num,
unsigned int queues) unsigned int queues)
{ {
mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), queues); mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num), queues);
} }
static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num) static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
...@@ -2273,21 +2811,18 @@ static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num) ...@@ -2273,21 +2811,18 @@ static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
u32 queues; u32 queues;
/* Stop Tx port activity. Check port Tx activity. */ /* Stop Tx port activity. Check port Tx activity. */
queues = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num)) queues = mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF;
& 0xFF;
if (queues) { if (queues) {
/* Issue stop command for active queues only */ /* Issue stop command for active queues only */
mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8));
(queues << 8));
/* Wait for all Tx activity to terminate. */ /* Wait for all Tx activity to terminate. */
/* Check port cause register that all Tx queues are stopped */ /* Check port cause register that all Tx queues are stopped */
while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num)) while (mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF)
& 0xFF)
udelay(PHY_WAIT_MICRO_SECONDS); udelay(PHY_WAIT_MICRO_SECONDS);
/* Wait for Tx FIFO to empty */ /* Wait for Tx FIFO to empty */
while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) & while (mv_read(PORT_STATUS_REG(port_num)) &
ETH_PORT_TX_FIFO_EMPTY) ETH_PORT_TX_FIFO_EMPTY)
udelay(PHY_WAIT_MICRO_SECONDS); udelay(PHY_WAIT_MICRO_SECONDS);
} }
...@@ -2300,17 +2835,14 @@ static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num) ...@@ -2300,17 +2835,14 @@ static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
u32 queues; u32 queues;
/* Stop Rx port activity. Check port Rx activity. */ /* Stop Rx port activity. Check port Rx activity. */
queues = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num)) queues = mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF;
& 0xFF;
if (queues) { if (queues) {
/* Issue stop command for active queues only */ /* Issue stop command for active queues only */
mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8));
(queues << 8));
/* Wait for all Rx activity to terminate. */ /* Wait for all Rx activity to terminate. */
/* Check port cause register that all Rx queues are stopped */ /* Check port cause register that all Rx queues are stopped */
while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num)) while (mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF)
& 0xFF)
udelay(PHY_WAIT_MICRO_SECONDS); udelay(PHY_WAIT_MICRO_SECONDS);
} }
...@@ -2346,11 +2878,11 @@ static void eth_port_reset(unsigned int port_num) ...@@ -2346,11 +2878,11 @@ static void eth_port_reset(unsigned int port_num)
eth_clear_mib_counters(port_num); eth_clear_mib_counters(port_num);
/* Reset the Enable bit in the Configuration Register */ /* Reset the Enable bit in the Configuration Register */
reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); reg_data = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
reg_data &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | reg_data &= ~(SERIAL_PORT_ENABLE |
MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | DO_NOT_FORCE_LINK_FAIL |
MV643XX_ETH_FORCE_LINK_PASS); FORCE_LINK_PASS);
mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data); mv_write(PORT_SERIAL_CONTROL_REG(port_num), reg_data);
} }
...@@ -2385,7 +2917,7 @@ static void eth_port_read_smi_reg(unsigned int port_num, ...@@ -2385,7 +2917,7 @@ static void eth_port_read_smi_reg(unsigned int port_num,
spin_lock_irqsave(&mv643xx_eth_phy_lock, flags); spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
/* wait for the SMI register to become available */ /* wait for the SMI register to become available */
for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) { for (i = 0; mv_read(SMI_REG) & ETH_SMI_BUSY; i++) {
if (i == PHY_WAIT_ITERATIONS) { if (i == PHY_WAIT_ITERATIONS) {
printk("mv643xx PHY busy timeout, port %d\n", port_num); printk("mv643xx PHY busy timeout, port %d\n", port_num);
goto out; goto out;
...@@ -2393,11 +2925,11 @@ static void eth_port_read_smi_reg(unsigned int port_num, ...@@ -2393,11 +2925,11 @@ static void eth_port_read_smi_reg(unsigned int port_num,
udelay(PHY_WAIT_MICRO_SECONDS); udelay(PHY_WAIT_MICRO_SECONDS);
} }
mv_write(MV643XX_ETH_SMI_REG, mv_write(SMI_REG,
(phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ); (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
/* now wait for the data to be valid */ /* now wait for the data to be valid */
for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) { for (i = 0; !(mv_read(SMI_REG) & ETH_SMI_READ_VALID); i++) {
if (i == PHY_WAIT_ITERATIONS) { if (i == PHY_WAIT_ITERATIONS) {
printk("mv643xx PHY read timeout, port %d\n", port_num); printk("mv643xx PHY read timeout, port %d\n", port_num);
goto out; goto out;
...@@ -2405,7 +2937,7 @@ static void eth_port_read_smi_reg(unsigned int port_num, ...@@ -2405,7 +2937,7 @@ static void eth_port_read_smi_reg(unsigned int port_num,
udelay(PHY_WAIT_MICRO_SECONDS); udelay(PHY_WAIT_MICRO_SECONDS);
} }
*value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff; *value = mv_read(SMI_REG) & 0xffff;
out: out:
spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags); spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
} }
...@@ -2443,7 +2975,7 @@ static void eth_port_write_smi_reg(unsigned int eth_port_num, ...@@ -2443,7 +2975,7 @@ static void eth_port_write_smi_reg(unsigned int eth_port_num,
spin_lock_irqsave(&mv643xx_eth_phy_lock, flags); spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
/* wait for the SMI register to become available */ /* wait for the SMI register to become available */
for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) { for (i = 0; mv_read(SMI_REG) & ETH_SMI_BUSY; i++) {
if (i == PHY_WAIT_ITERATIONS) { if (i == PHY_WAIT_ITERATIONS) {
printk("mv643xx PHY busy timeout, port %d\n", printk("mv643xx PHY busy timeout, port %d\n",
eth_port_num); eth_port_num);
...@@ -2452,7 +2984,7 @@ static void eth_port_write_smi_reg(unsigned int eth_port_num, ...@@ -2452,7 +2984,7 @@ static void eth_port_write_smi_reg(unsigned int eth_port_num,
udelay(PHY_WAIT_MICRO_SECONDS); udelay(PHY_WAIT_MICRO_SECONDS);
} }
mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) | mv_write(SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
ETH_SMI_OPCODE_WRITE | (value & 0xffff)); ETH_SMI_OPCODE_WRITE | (value & 0xffff));
out: out:
spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags); spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
......
drivers/net/mv643xx_eth.h deleted 100644 → 0
View file @ c7ffb6bb
#ifndef __MV643XX_ETH_H__
#define __MV643XX_ETH_H__
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/mii.h>
#include <linux/mv643xx.h>
#include <asm/dma-mapping.h>
/* Checksum offload for Tx works for most packets, but
* fails if previous packet sent did not use hw csum
*/
#define MV643XX_CHECKSUM_OFFLOAD_TX
#define MV643XX_NAPI
#define MV643XX_TX_FAST_REFILL
#undef MV643XX_COAL
/*
* Number of RX / TX descriptors on RX / TX rings.
* Note that allocating RX descriptors is done by allocating the RX
* ring AND a preallocated RX buffers (skb's) for each descriptor.
* The TX descriptors only allocates the TX descriptors ring,
* with no pre allocated TX buffers (skb's are allocated by higher layers.
*/
/* Default TX ring size is 1000 descriptors */
#define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
/* Default RX ring size is 400 descriptors */
#define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
#define MV643XX_TX_COAL 100
#ifdef MV643XX_COAL
#define MV643XX_RX_COAL 100
#endif
#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
#else
#define MAX_DESCS_PER_SKB 1
#endif
#define ETH_VLAN_HLEN 4
#define ETH_FCS_LEN 4
#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
#define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
ETH_VLAN_HLEN + ETH_FCS_LEN)
#define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + dma_get_cache_alignment())
#define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
#define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
#define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
#define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
#define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
#define ETH_INT_CAUSE_EXT 0x00000002
#define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
#define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
#define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
#define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
#define ETH_INT_CAUSE_PHY 0x00010000
#define ETH_INT_CAUSE_STATE 0x00100000
#define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
ETH_INT_CAUSE_STATE)
#define ETH_INT_MASK_ALL 0x00000000
#define ETH_INT_MASK_ALL_EXT 0x00000000
#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
#define PHY_WAIT_MICRO_SECONDS 10
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Gigabit Ethernet Unit Global Registers */
/* MIB Counters register definitions */
#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
#define ETH_MIB_FRAMES_64_OCTETS 0x20
#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
#define ETH_MIB_GOOD_FRAMES_SENT 0x40
#define ETH_MIB_EXCESSIVE_COLLISION 0x44
#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
#define ETH_MIB_FC_SENT 0x54
#define ETH_MIB_GOOD_FC_RECEIVED 0x58
#define ETH_MIB_BAD_FC_RECEIVED 0x5c
#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
#define ETH_MIB_OVERSIZE_RECEIVED 0x68
#define ETH_MIB_JABBER_RECEIVED 0x6c
#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
#define ETH_MIB_BAD_CRC_EVENT 0x74
#define ETH_MIB_COLLISION 0x78
#define ETH_MIB_LATE_COLLISION 0x7c
/* Port serial status reg (PSR) */
#define ETH_INTERFACE_PCM 0x00000001
#define ETH_LINK_IS_UP 0x00000002
#define ETH_PORT_AT_FULL_DUPLEX 0x00000004
#define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
#define ETH_GMII_SPEED_1000 0x00000010
#define ETH_MII_SPEED_100 0x00000020
#define ETH_TX_IN_PROGRESS 0x00000080
#define ETH_BYPASS_ACTIVE 0x00000100
#define ETH_PORT_AT_PARTITION_STATE 0x00000200
#define ETH_PORT_TX_FIFO_EMPTY 0x00000400
/* SMI reg */
#define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
#define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
#define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
/* Interrupt Cause Register Bit Definitions */
/* SDMA command status fields macros */
/* Tx & Rx descriptors status */
#define ETH_ERROR_SUMMARY 0x00000001
/* Tx & Rx descriptors command */
#define ETH_BUFFER_OWNED_BY_DMA 0x80000000
/* Tx descriptors status */
#define ETH_LC_ERROR 0
#define ETH_UR_ERROR 0x00000002
#define ETH_RL_ERROR 0x00000004
#define ETH_LLC_SNAP_FORMAT 0x00000200
/* Rx descriptors status */
#define ETH_OVERRUN_ERROR 0x00000002
#define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
#define ETH_RESOURCE_ERROR 0x00000006
#define ETH_VLAN_TAGGED 0x00080000
#define ETH_BPDU_FRAME 0x00100000
#define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
#define ETH_OTHER_FRAME_TYPE 0x00400000
#define ETH_LAYER_2_IS_ETH_V_2 0x00800000
#define ETH_FRAME_TYPE_IP_V_4 0x01000000
#define ETH_FRAME_HEADER_OK 0x02000000
#define ETH_RX_LAST_DESC 0x04000000
#define ETH_RX_FIRST_DESC 0x08000000
#define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
#define ETH_RX_ENABLE_INTERRUPT 0x20000000
#define ETH_LAYER_4_CHECKSUM_OK 0x40000000
/* Rx descriptors byte count */
#define ETH_FRAME_FRAGMENTED 0x00000004
/* Tx descriptors command */
#define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
#define ETH_FRAME_SET_TO_VLAN 0x00008000
#define ETH_UDP_FRAME 0x00010000
#define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
#define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
#define ETH_ZERO_PADDING 0x00080000
#define ETH_TX_LAST_DESC 0x00100000
#define ETH_TX_FIRST_DESC 0x00200000
#define ETH_GEN_CRC 0x00400000
#define ETH_TX_ENABLE_INTERRUPT 0x00800000
#define ETH_AUTO_MODE 0x40000000
#define ETH_TX_IHL_SHIFT 11
/* typedefs */
typedef enum _eth_func_ret_status {
ETH_OK, /* Returned as expected. */
ETH_ERROR, /* Fundamental error. */
ETH_RETRY, /* Could not process request. Try later.*/
ETH_END_OF_JOB, /* Ring has nothing to process. */
ETH_QUEUE_FULL, /* Ring resource error. */
ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
} ETH_FUNC_RET_STATUS;
typedef enum _eth_target {
ETH_TARGET_DRAM,
ETH_TARGET_DEVICE,
ETH_TARGET_CBS,
ETH_TARGET_PCI0,
ETH_TARGET_PCI1
} ETH_TARGET;
/* These are for big-endian machines. Little endian needs different
* definitions.
*/
#if defined(__BIG_ENDIAN)
struct eth_rx_desc {
u16 byte_cnt; /* Descriptor buffer byte count */
u16 buf_size; /* Buffer size */
u32 cmd_sts; /* Descriptor command status */
u32 next_desc_ptr; /* Next descriptor pointer */
u32 buf_ptr; /* Descriptor buffer pointer */
};
struct eth_tx_desc {
u16 byte_cnt; /* buffer byte count */
u16 l4i_chk; /* CPU provided TCP checksum */
u32 cmd_sts; /* Command/status field */
u32 next_desc_ptr; /* Pointer to next descriptor */
u32 buf_ptr; /* pointer to buffer for this descriptor*/
};
#elif defined(__LITTLE_ENDIAN)
struct eth_rx_desc {
u32 cmd_sts; /* Descriptor command status */
u16 buf_size; /* Buffer size */
u16 byte_cnt; /* Descriptor buffer byte count */
u32 buf_ptr; /* Descriptor buffer pointer */
u32 next_desc_ptr; /* Next descriptor pointer */
};
struct eth_tx_desc {
u32 cmd_sts; /* Command/status field */
u16 l4i_chk; /* CPU provided TCP checksum */
u16 byte_cnt; /* buffer byte count */
u32 buf_ptr; /* pointer to buffer for this descriptor*/
u32 next_desc_ptr; /* Pointer to next descriptor */
};
#else
#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
#endif
/* Unified struct for Rx and Tx operations. The user is not required to */
/* be familier with neither Tx nor Rx descriptors. */
struct pkt_info {
unsigned short byte_cnt; /* Descriptor buffer byte count */
unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
unsigned int cmd_sts; /* Descriptor command status */
dma_addr_t buf_ptr; /* Descriptor buffer pointer */
struct sk_buff *return_info; /* User resource return information */
};
/* Ethernet port specific information */
struct mv643xx_mib_counters {
u64 good_octets_received;
u32 bad_octets_received;
u32 internal_mac_transmit_err;
u32 good_frames_received;
u32 bad_frames_received;
u32 broadcast_frames_received;
u32 multicast_frames_received;
u32 frames_64_octets;
u32 frames_65_to_127_octets;
u32 frames_128_to_255_octets;
u32 frames_256_to_511_octets;
u32 frames_512_to_1023_octets;
u32 frames_1024_to_max_octets;
u64 good_octets_sent;
u32 good_frames_sent;
u32 excessive_collision;
u32 multicast_frames_sent;
u32 broadcast_frames_sent;
u32 unrec_mac_control_received;
u32 fc_sent;
u32 good_fc_received;
u32 bad_fc_received;
u32 undersize_received;
u32 fragments_received;
u32 oversize_received;
u32 jabber_received;
u32 mac_receive_error;
u32 bad_crc_event;
u32 collision;
u32 late_collision;
};
struct mv643xx_private {
int port_num; /* User Ethernet port number */
u32 rx_sram_addr; /* Base address of rx sram area */
u32 rx_sram_size; /* Size of rx sram area */
u32 tx_sram_addr; /* Base address of tx sram area */
u32 tx_sram_size; /* Size of tx sram area */
int rx_resource_err; /* Rx ring resource error flag */
/* Tx/Rx rings managment indexes fields. For driver use */
/* Next available and first returning Rx resource */
int rx_curr_desc_q, rx_used_desc_q;
/* Next available and first returning Tx resource */
int tx_curr_desc_q, tx_used_desc_q;
#ifdef MV643XX_TX_FAST_REFILL
u32 tx_clean_threshold;
#endif
struct eth_rx_desc *p_rx_desc_area;
dma_addr_t rx_desc_dma;
int rx_desc_area_size;
struct sk_buff **rx_skb;
struct eth_tx_desc *p_tx_desc_area;
dma_addr_t tx_desc_dma;
int tx_desc_area_size;
struct sk_buff **tx_skb;
struct work_struct tx_timeout_task;
struct net_device *dev;
struct napi_struct napi;
struct net_device_stats stats;
struct mv643xx_mib_counters mib_counters;
spinlock_t lock;
/* Size of Tx Ring per queue */
int tx_ring_size;
/* Number of tx descriptors in use */
int tx_desc_count;
/* Size of Rx Ring per queue */
int rx_ring_size;
/* Number of rx descriptors in use */
int rx_desc_count;
/*
* Used in case RX Ring is empty, which can be caused when
* system does not have resources (skb's)
*/
struct timer_list timeout;
u32 rx_int_coal;
u32 tx_int_coal;
struct mii_if_info mii;
};
/* Port operation control routines */
static void eth_port_init(struct mv643xx_private *mp);
static void eth_port_reset(unsigned int eth_port_num);
static void eth_port_start(struct net_device *dev);
/* PHY and MIB routines */
static void ethernet_phy_reset(unsigned int eth_port_num);
static void eth_port_write_smi_reg(unsigned int eth_port_num,
unsigned int phy_reg, unsigned int value);
static void eth_port_read_smi_reg(unsigned int eth_port_num,
unsigned int phy_reg, unsigned int *value);
static void eth_clear_mib_counters(unsigned int eth_port_num);
/* Port data flow control routines */
static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
struct pkt_info *p_pkt_info);
static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
struct pkt_info *p_pkt_info);
#endif /* __MV643XX_ETH_H__ */
include/linux/mv643xx.h
View file @ 02bae212
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#define __ASM_MV643XX_H #define __ASM_MV643XX_H
#include <asm/types.h> #include <asm/types.h>
#include <linux/mv643xx_eth.h>
/****************************************/ /****************************************/
/* Processor Address Space */ /* Processor Address Space */
...@@ -658,120 +659,6 @@ ...@@ -658,120 +659,6 @@
/* Ethernet Unit Registers */ /* Ethernet Unit Registers */
/****************************************/ /****************************************/
#define MV643XX_ETH_SHARED_REGS 0x2000
#define MV643XX_ETH_SHARED_REGS_SIZE 0x2000
#define MV643XX_ETH_PHY_ADDR_REG 0x2000
#define MV643XX_ETH_SMI_REG 0x2004
#define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
#define MV643XX_ETH_UNIT_DEFAULTID_REG 0x200c
#define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
#define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
#define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x24fc
#define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x2094
#define MV643XX_ETH_BAR_0 0x2200
#define MV643XX_ETH_BAR_1 0x2208
#define MV643XX_ETH_BAR_2 0x2210
#define MV643XX_ETH_BAR_3 0x2218
#define MV643XX_ETH_BAR_4 0x2220
#define MV643XX_ETH_BAR_5 0x2228
#define MV643XX_ETH_SIZE_REG_0 0x2204
#define MV643XX_ETH_SIZE_REG_1 0x220c
#define MV643XX_ETH_SIZE_REG_2 0x2214
#define MV643XX_ETH_SIZE_REG_3 0x221c
#define MV643XX_ETH_SIZE_REG_4 0x2224
#define MV643XX_ETH_SIZE_REG_5 0x222c
#define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x2230
#define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290
#define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
#define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
#define MV643XX_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
#define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
#define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
#define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
#define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
#define MV643XX_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
#define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
#define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
#define MV643XX_ETH_DSCP_0(port) (0x2420 + (port<<10))
#define MV643XX_ETH_DSCP_1(port) (0x2424 + (port<<10))
#define MV643XX_ETH_DSCP_2(port) (0x2428 + (port<<10))
#define MV643XX_ETH_DSCP_3(port) (0x242c + (port<<10))
#define MV643XX_ETH_DSCP_4(port) (0x2430 + (port<<10))
#define MV643XX_ETH_DSCP_5(port) (0x2434 + (port<<10))
#define MV643XX_ETH_DSCP_6(port) (0x2438 + (port<<10))
#define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
#define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
#define MV643XX_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
#define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
#define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
#define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
#define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
#define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
#define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
#define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
#define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
#define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
#define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
#define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10))
#define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
#define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
#define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
#define MV643XX_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
#define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
#define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
#define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
#define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
#define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
#define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
/*******************************************/ /*******************************************/
/* CUNIT Registers */ /* CUNIT Registers */
/*******************************************/ /*******************************************/
...@@ -1089,219 +976,6 @@ struct mv64xxx_i2c_pdata { ...@@ -1089,219 +976,6 @@ struct mv64xxx_i2c_pdata {
u32 retries; u32 retries;
}; };
/* These macros describe Ethernet Port configuration reg (Px_cR) bits */
#define MV643XX_ETH_UNICAST_NORMAL_MODE 0
#define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE (1<<0)
#define MV643XX_ETH_DEFAULT_RX_QUEUE_0 0
#define MV643XX_ETH_DEFAULT_RX_QUEUE_1 (1<<1)
#define MV643XX_ETH_DEFAULT_RX_QUEUE_2 (1<<2)
#define MV643XX_ETH_DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1))
#define MV643XX_ETH_DEFAULT_RX_QUEUE_4 (1<<3)
#define MV643XX_ETH_DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1))
#define MV643XX_ETH_DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2))
#define MV643XX_ETH_DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1))
#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 0
#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_1 (1<<4)
#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_2 (1<<5)
#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4))
#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_4 (1<<6)
#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4))
#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5))
#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4))
#define MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
#define MV643XX_ETH_REJECT_BC_IF_NOT_IP_OR_ARP (1<<7)
#define MV643XX_ETH_RECEIVE_BC_IF_IP 0
#define MV643XX_ETH_REJECT_BC_IF_IP (1<<8)
#define MV643XX_ETH_RECEIVE_BC_IF_ARP 0
#define MV643XX_ETH_REJECT_BC_IF_ARP (1<<9)
#define MV643XX_ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12)
#define MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS 0
#define MV643XX_ETH_CAPTURE_TCP_FRAMES_EN (1<<14)
#define MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS 0
#define MV643XX_ETH_CAPTURE_UDP_FRAMES_EN (1<<15)
#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 0
#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_1 (1<<16)
#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_2 (1<<17)
#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16))
#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_4 (1<<18)
#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16))
#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17))
#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16))
#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 0
#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_1 (1<<19)
#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_2 (1<<20)
#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))
#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 (1<<21)
#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19))
#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20))
#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19))
#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0 0
#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_1 (1<<22)
#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_2 (1<<23)
#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22))
#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_4 (1<<24)
#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22))
#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23))
#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22))
#define MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE \
MV643XX_ETH_UNICAST_NORMAL_MODE | \
MV643XX_ETH_DEFAULT_RX_QUEUE_0 | \
MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 | \
MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
MV643XX_ETH_RECEIVE_BC_IF_IP | \
MV643XX_ETH_RECEIVE_BC_IF_ARP | \
MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS | \
MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS | \
MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 | \
MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 | \
MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0
/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
#define MV643XX_ETH_CLASSIFY_EN (1<<0)
#define MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
#define MV643XX_ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1)
#define MV643XX_ETH_PARTITION_DISABLE 0
#define MV643XX_ETH_PARTITION_ENABLE (1<<2)
#define MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE \
MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
MV643XX_ETH_PARTITION_DISABLE
/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
#define MV643XX_ETH_RIFB (1<<0)
#define MV643XX_ETH_RX_BURST_SIZE_1_64BIT 0
#define MV643XX_ETH_RX_BURST_SIZE_2_64BIT (1<<1)
#define MV643XX_ETH_RX_BURST_SIZE_4_64BIT (1<<2)
#define MV643XX_ETH_RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1))
#define MV643XX_ETH_RX_BURST_SIZE_16_64BIT (1<<3)
#define MV643XX_ETH_BLM_RX_NO_SWAP (1<<4)
#define MV643XX_ETH_BLM_RX_BYTE_SWAP 0
#define MV643XX_ETH_BLM_TX_NO_SWAP (1<<5)
#define MV643XX_ETH_BLM_TX_BYTE_SWAP 0
#define MV643XX_ETH_DESCRIPTORS_BYTE_SWAP (1<<6)
#define MV643XX_ETH_DESCRIPTORS_NO_SWAP 0
#define MV643XX_ETH_TX_BURST_SIZE_1_64BIT 0
#define MV643XX_ETH_TX_BURST_SIZE_2_64BIT (1<<22)
#define MV643XX_ETH_TX_BURST_SIZE_4_64BIT (1<<23)
#define MV643XX_ETH_TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22))
#define MV643XX_ETH_TX_BURST_SIZE_16_64BIT (1<<24)
#define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8)
#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
MV643XX_ETH_IPG_INT_RX(0) | \
MV643XX_ETH_TX_BURST_SIZE_4_64BIT
/* These macros describe Ethernet Port serial control reg (PSCR) bits */
#define MV643XX_ETH_SERIAL_PORT_DISABLE 0
#define MV643XX_ETH_SERIAL_PORT_ENABLE (1<<0)
#define MV643XX_ETH_FORCE_LINK_PASS (1<<1)
#define MV643XX_ETH_DO_NOT_FORCE_LINK_PASS 0
#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX (1<<2)
#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3)
#define MV643XX_ETH_ADV_NO_FLOW_CTRL 0
#define MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL (1<<4)
#define MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
#define MV643XX_ETH_FORCE_FC_MODE_TX_PAUSE_DIS (1<<5)
#define MV643XX_ETH_FORCE_BP_MODE_NO_JAM 0
#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX (1<<7)
#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8)
#define MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED (1<<9)
#define MV643XX_ETH_FORCE_LINK_FAIL 0
#define MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL (1<<10)
#define MV643XX_ETH_RETRANSMIT_16_ATTEMPTS 0
#define MV643XX_ETH_RETRANSMIT_FOREVER (1<<11)
#define MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII (1<<13)
#define MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
#define MV643XX_ETH_DTE_ADV_0 0
#define MV643XX_ETH_DTE_ADV_1 (1<<14)
#define MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS 0
#define MV643XX_ETH_ENABLE_AUTO_NEG_BYPASS (1<<15)
#define MV643XX_ETH_AUTO_NEG_NO_CHANGE 0
#define MV643XX_ETH_RESTART_AUTO_NEG (1<<16)
#define MV643XX_ETH_MAX_RX_PACKET_1518BYTE 0
#define MV643XX_ETH_MAX_RX_PACKET_1522BYTE (1<<17)
#define MV643XX_ETH_MAX_RX_PACKET_1552BYTE (1<<18)
#define MV643XX_ETH_MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17))
#define MV643XX_ETH_MAX_RX_PACKET_9192BYTE (1<<19)
#define MV643XX_ETH_MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17))
#define MV643XX_ETH_SET_EXT_LOOPBACK (1<<20)
#define MV643XX_ETH_CLR_EXT_LOOPBACK 0
#define MV643XX_ETH_SET_FULL_DUPLEX_MODE (1<<21)
#define MV643XX_ETH_SET_HALF_DUPLEX_MODE 0
#define MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22)
#define MV643XX_ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
#define MV643XX_ETH_SET_GMII_SPEED_TO_10_100 0
#define MV643XX_ETH_SET_GMII_SPEED_TO_1000 (1<<23)
#define MV643XX_ETH_SET_MII_SPEED_TO_10 0
#define MV643XX_ETH_SET_MII_SPEED_TO_100 (1<<24)
#define MV643XX_ETH_MAX_RX_PACKET_MASK (0x7<<17)
#define MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE \
MV643XX_ETH_DO_NOT_FORCE_LINK_PASS | \
MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL | \
MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
MV643XX_ETH_FORCE_BP_MODE_NO_JAM | \
(1<<9) /* reserved */ | \
MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | \
MV643XX_ETH_RETRANSMIT_16_ATTEMPTS | \
MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
MV643XX_ETH_DTE_ADV_0 | \
MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS | \
MV643XX_ETH_AUTO_NEG_NO_CHANGE | \
MV643XX_ETH_MAX_RX_PACKET_9700BYTE | \
MV643XX_ETH_CLR_EXT_LOOPBACK | \
MV643XX_ETH_SET_FULL_DUPLEX_MODE | \
MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
/* These macros describe Ethernet Serial Status reg (PSR) bits */
#define MV643XX_ETH_PORT_STATUS_MODE_10_BIT (1<<0)
#define MV643XX_ETH_PORT_STATUS_LINK_UP (1<<1)
#define MV643XX_ETH_PORT_STATUS_FULL_DUPLEX (1<<2)
#define MV643XX_ETH_PORT_STATUS_FLOW_CONTROL (1<<3)
#define MV643XX_ETH_PORT_STATUS_GMII_1000 (1<<4)
#define MV643XX_ETH_PORT_STATUS_MII_100 (1<<5)
/* PSR bit 6 is undocumented */
#define MV643XX_ETH_PORT_STATUS_TX_IN_PROGRESS (1<<7)
#define MV643XX_ETH_PORT_STATUS_AUTONEG_BYPASSED (1<<8)
#define MV643XX_ETH_PORT_STATUS_PARTITION (1<<9)
#define MV643XX_ETH_PORT_STATUS_TX_FIFO_EMPTY (1<<10)
/* PSR bits 11-31 are reserved */
#define MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
#define MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
#define MV643XX_ETH_DESC_SIZE 64
#define MV643XX_ETH_SHARED_NAME "mv643xx_eth_shared"
#define MV643XX_ETH_NAME "mv643xx_eth"
struct mv643xx_eth_platform_data {
int port_number;
u16 force_phy_addr; /* force override if phy_addr == 0 */
u16 phy_addr;
/* If speed is 0, then speed and duplex are autonegotiated. */
int speed; /* 0, SPEED_10, SPEED_100, SPEED_1000 */
int duplex; /* DUPLEX_HALF or DUPLEX_FULL */
/* non-zero values of the following fields override defaults */
u32 tx_queue_size;
u32 rx_queue_size;
u32 tx_sram_addr;
u32 tx_sram_size;
u32 rx_sram_addr;
u32 rx_sram_size;
u8 mac_addr[6]; /* mac address if non-zero*/
};
/* Watchdog Platform Device, Driver Data */ /* Watchdog Platform Device, Driver Data */
#define MV64x60_WDT_NAME "mv64x60_wdt" #define MV64x60_WDT_NAME "mv64x60_wdt"
......
include/linux/mv643xx_eth.h 0 → 100644
View file @ 02bae212
/*
* MV-643XX ethernet platform device data definition file.
*/
#ifndef __LINUX_MV643XX_ETH_H
#define __LINUX_MV643XX_ETH_H
#define MV643XX_ETH_SHARED_NAME "mv643xx_eth_shared"
#define MV643XX_ETH_NAME "mv643xx_eth"
#define MV643XX_ETH_SHARED_REGS 0x2000
#define MV643XX_ETH_SHARED_REGS_SIZE 0x2000
struct mv643xx_eth_platform_data {
int port_number;
u16 force_phy_addr; /* force override if phy_addr == 0 */
u16 phy_addr;
/* If speed is 0, then speed and duplex are autonegotiated. */
int speed; /* 0, SPEED_10, SPEED_100, SPEED_1000 */
int duplex; /* DUPLEX_HALF or DUPLEX_FULL */
/* non-zero values of the following fields override defaults */
u32 tx_queue_size;
u32 rx_queue_size;
u32 tx_sram_addr;
u32 tx_sram_size;
u32 rx_sram_addr;
u32 rx_sram_size;
u8 mac_addr[6]; /* mac address if non-zero*/
};
#endif /* __LINUX_MV643XX_ETH_H */
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