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Commit 062d1647 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
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Staging: dt3155: coding cleanups for dt3155_io.h 

This fixes up some coding style issues in the dt3155_io.h file

Cc: Scott Smedley <ss@aao.gov.au>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent f721ad7a
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Showing with 212 additions and 251 deletions
drivers/staging/dt3155/dt3155_io.h
View file @ 062d1647
...@@ -70,151 +70,115 @@ MA 02111-1307 USA ...@@ -70,151 +70,115 @@ MA 02111-1307 USA
/******** Assignments and Typedefs for 32 bit Memory Mapped Registers ********/ /******** Assignments and Typedefs for 32 bit Memory Mapped Registers ********/
/**********************************
* fifo_trigger_tag
*/
typedef union fifo_trigger_tag { typedef union fifo_trigger_tag {
u_long reg; u_long reg;
struct struct {
{ u_long PACKED:6;
u_long PACKED : 6; u_long :9;
u_long : 9; u_long PLANER:7;
u_long PLANER : 7; u_long :9;
u_long : 9;
} fld; } fld;
} FIFO_TRIGGER_R; } FIFO_TRIGGER_R;
/**********************************
* xfer_mode_tag
*/
typedef union xfer_mode_tag { typedef union xfer_mode_tag {
u_long reg; u_long reg;
struct struct {
{ u_long :2;
u_long : 2; u_long FIELD_TOGGLE:1;
u_long FIELD_TOGGLE : 1; u_long :5;
u_long : 5; u_long :2;
u_long : 2; u_long :22;
u_long : 22;
} fld; } fld;
} XFER_MODE_R; } XFER_MODE_R;
/**********************************
* csr1_tag
*/
typedef union csr1_tag { typedef union csr1_tag {
u_long reg; u_long reg;
struct struct {
{ u_long CAP_CONT_EVE:1;
u_long CAP_CONT_EVE : 1; u_long CAP_CONT_ODD:1;
u_long CAP_CONT_ODD : 1; u_long CAP_SNGL_EVE:1;
u_long CAP_SNGL_EVE : 1; u_long CAP_SNGL_ODD:1;
u_long CAP_SNGL_ODD : 1; u_long FLD_DN_EVE :1;
u_long FLD_DN_EVE : 1; u_long FLD_DN_ODD :1;
u_long FLD_DN_ODD : 1; u_long SRST :1;
u_long SRST : 1; u_long FIFO_EN :1;
u_long FIFO_EN : 1; u_long FLD_CRPT_EVE:1;
u_long FLD_CRPT_EVE : 1; u_long FLD_CRPT_ODD:1;
u_long FLD_CRPT_ODD : 1; u_long ADDR_ERR_EVE:1;
u_long ADDR_ERR_EVE : 1; u_long ADDR_ERR_ODD:1;
u_long ADDR_ERR_ODD : 1; u_long CRPT_DIS :1;
u_long CRPT_DIS : 1; u_long RANGE_EN :1;
u_long RANGE_EN : 1; u_long :16;
u_long : 16;
} fld; } fld;
} CSR1_R; } CSR1_R;
/**********************************
* retry_wait_cnt_tag
*/
typedef union retry_wait_cnt_tag { typedef union retry_wait_cnt_tag {
u_long reg; u_long reg;
struct struct {
{ u_long RTRY_WAIT_CNT:8;
u_long RTRY_WAIT_CNT : 8; u_long :24;
u_long : 24;
} fld; } fld;
} RETRY_WAIT_CNT_R; } RETRY_WAIT_CNT_R;
/**********************************
* int_csr_tag
*/
typedef union int_csr_tag { typedef union int_csr_tag {
u_long reg; u_long reg;
struct struct {
{ u_long FLD_END_EVE :1;
u_long FLD_END_EVE : 1; u_long FLD_END_ODD :1;
u_long FLD_END_ODD : 1; u_long FLD_START :1;
u_long FLD_START : 1; u_long :5;
u_long : 5; u_long FLD_END_EVE_EN:1;
u_long FLD_END_EVE_EN : 1; u_long FLD_END_ODD_EN:1;
u_long FLD_END_ODD_EN : 1; u_long FLD_START_EN :1;
u_long FLD_START_EN : 1; u_long :21;
u_long : 21;
} fld; } fld;
} INT_CSR_R; } INT_CSR_R;
/**********************************
* mask_length_tag
*/
typedef union mask_length_tag { typedef union mask_length_tag {
u_long reg; u_long reg;
struct struct {
{ u_long MASK_LEN_EVE:5;
u_long MASK_LEN_EVE : 5; u_long :11;
u_long : 11; u_long MASK_LEN_ODD:5;
u_long MASK_LEN_ODD : 5; u_long :11;
u_long : 11;
} fld; } fld;
} MASK_LENGTH_R; } MASK_LENGTH_R;
/**********************************
* fifo_flag_cnt_tag
*/
typedef union fifo_flag_cnt_tag { typedef union fifo_flag_cnt_tag {
u_long reg; u_long reg;
struct struct {
{ u_long AF_COUNT:7;
u_long AF_COUNT : 7; u_long :9;
u_long : 9; u_long AE_COUNT:7;
u_long AE_COUNT : 7; u_long :9;
u_long : 9;
} fld; } fld;
} FIFO_FLAG_CNT_R; } FIFO_FLAG_CNT_R;
/**********************************
* iic_clk_dur
*/
typedef union iic_clk_dur { typedef union iic_clk_dur {
u_long reg; u_long reg;
struct struct {
{ u_long PHASE_1:8;
u_long PHASE_1 : 8; u_long PHASE_2:8;
u_long PHASE_2 : 8; u_long PHASE_3:8;
u_long PHASE_3 : 8; u_long PHASE_4:8;
u_long PHASE_4 : 8;
} fld; } fld;
} IIC_CLK_DUR_R; } IIC_CLK_DUR_R;
/**********************************
* iic_csr1_tag
*/
typedef union iic_csr1_tag { typedef union iic_csr1_tag {
u_long reg; u_long reg;
struct struct {
{ u_long AUTO_EN :1;
u_long AUTO_EN : 1; u_long BYPASS :1;
u_long BYPASS : 1; u_long SDA_OUT :1;
u_long SDA_OUT : 1; u_long SCL_OUT :1;
u_long SCL_OUT : 1; u_long :4;
u_long : 4; u_long AUTO_ABORT :1;
u_long AUTO_ABORT : 1; u_long DIRECT_ABORT:1;
u_long DIRECT_ABORT : 1; u_long SDA_IN :1;
u_long SDA_IN : 1; u_long SCL_IN :1;
u_long SCL_IN : 1; u_long :4;
u_long : 4; u_long AUTO_ADDR :8;
u_long AUTO_ADDR : 8; u_long RD_DATA :8;
u_long RD_DATA : 8;
} fld; } fld;
} IIC_CSR1_R; } IIC_CSR1_R;
...@@ -223,20 +187,19 @@ typedef union iic_csr1_tag { ...@@ -223,20 +187,19 @@ typedef union iic_csr1_tag {
*/ */
typedef union iic_csr2_tag { typedef union iic_csr2_tag {
u_long reg; u_long reg;
struct struct {
{ u_long DIR_WR_DATA :8;
u_long DIR_WR_DATA : 8; u_long DIR_SUB_ADDR:8;
u_long DIR_SUB_ADDR : 8; u_long DIR_RD :1;
u_long DIR_RD : 1; u_long DIR_ADDR :7;
u_long DIR_ADDR : 7; u_long NEW_CYCLE :1;
u_long NEW_CYCLE : 1; u_long :7;
u_long : 7;
} fld; } fld;
} IIC_CSR2_R; } IIC_CSR2_R;
/* use for both EVEN and ODD DMA UPPER LIMITS */ /* use for both EVEN and ODD DMA UPPER LIMITS */
/********************************** /*
* dma_upper_lmt_tag * dma_upper_lmt_tag
*/ */
typedef union dma_upper_lmt_tag { typedef union dma_upper_lmt_tag {
...@@ -248,10 +211,9 @@ typedef union dma_upper_lmt_tag { ...@@ -248,10 +211,9 @@ typedef union dma_upper_lmt_tag {
} DMA_UPPER_LMT_R; } DMA_UPPER_LMT_R;
/*************************************** /*
* Global declarations of local copies * Global declarations of local copies of boards' 32 bit registers
* of boards' 32 bit registers */
***************************************/
extern u_long even_dma_start_r; /* bit 0 should always be 0 */ extern u_long even_dma_start_r; /* bit 0 should always be 0 */
extern u_long odd_dma_start_r; /* .. */ extern u_long odd_dma_start_r; /* .. */
extern u_long even_dma_stride_r; /* bits 0&1 should always be 0 */ extern u_long even_dma_stride_r; /* bits 0&1 should always be 0 */
...@@ -279,7 +241,6 @@ extern DMA_UPPER_LMT_R odd_dma_upper_lmt_r; ...@@ -279,7 +241,6 @@ extern DMA_UPPER_LMT_R odd_dma_upper_lmt_r;
/***************** 8 bit I2C register globals ***********/ /***************** 8 bit I2C register globals ***********/
#define CSR2 0x010 /* indices of 8-bit I2C mapped reg's*/ #define CSR2 0x010 /* indices of 8-bit I2C mapped reg's*/
#define EVEN_CSR 0x011 #define EVEN_CSR 0x011
#define ODD_CSR 0x012 #define ODD_CSR 0x012
...@@ -315,8 +276,8 @@ typedef union i2c_csr2_tag { ...@@ -315,8 +276,8 @@ typedef union i2c_csr2_tag {
typedef union i2c_even_csr_tag { typedef union i2c_even_csr_tag {
u_char reg; u_char reg;
struct { struct {
u_char DONE_EVE:1; u_char DONE_EVE :1;
u_char SNGL_EVE:1; u_char SNGL_EVE :1;
u_char ERROR_EVE:1; u_char ERROR_EVE:1;
u_char :5; u_char :5;
} fld; } fld;
...@@ -324,49 +285,49 @@ typedef union i2c_even_csr_tag { ...@@ -324,49 +285,49 @@ typedef union i2c_even_csr_tag {
typedef union i2c_odd_csr_tag { typedef union i2c_odd_csr_tag {
u_char reg; u_char reg;
struct struct {
{ u_char DONE_ODD:1;
u_char DONE_ODD : 1; u_char SNGL_ODD:1;
u_char SNGL_ODD : 1; u_char ERROR_ODD:1;
u_char ERROR_ODD : 1; u_char :5;
u_char : 5;
} fld; } fld;
} I2C_ODD_CSR; } I2C_ODD_CSR;
typedef union i2c_config_tag { typedef union i2c_config_tag {
u_char reg; u_char reg;
struct struct {
{ u_char ACQ_MODE:2;
u_char ACQ_MODE : 2; u_char EXT_TRIG_EN:1;
u_char EXT_TRIG_EN : 1; u_char EXT_TRIG_POL:1;
u_char EXT_TRIG_POL : 1; u_char H_SCALE:1;
u_char H_SCALE : 1; u_char CLIP:1;
u_char CLIP : 1; u_char PM_LUT_SEL:1;
u_char PM_LUT_SEL : 1; u_char PM_LUT_PGM:1;
u_char PM_LUT_PGM : 1;
} fld; } fld;
} I2C_CONFIG; } I2C_CONFIG;
typedef union i2c_ad_cmd_tag { /* bits can have 3 different meanings typedef union i2c_ad_cmd_tag {
depending on value of AD_ADDR */ /* bits can have 3 different meanings depending on value of AD_ADDR */
u_char reg; u_char reg;
struct /* Bt252 Command Register if AD_ADDR = 00h */
{ struct {
u_char : 2; u_char :2;
u_char SYNC_LVL_SEL : 2; u_char SYNC_LVL_SEL:2;
u_char SYNC_CNL_SEL : 2; u_char SYNC_CNL_SEL:2;
u_char DIGITIZE_CNL_SEL1 : 2; u_char DIGITIZE_CNL_SEL1:2;
} bt252_command; /* Bt252 Command Register */ } bt252_command;
struct /* if AD_ADDR = 00h */
{ /* Bt252 IOUT0 register if AD_ADDR = 01h */
u_char IOUT_DATA : 8; struct {
} bt252_iout0; /* Bt252 IOUT0 register */ u_char IOUT_DATA:8;
struct /* if AD_ADDR = 01h */ } bt252_iout0;
{
u_char IOUT_DATA : 8; /* BT252 IOUT1 register if AD_ADDR = 02h */
} bt252_iout1; /* BT252 IOUT1 register */ struct {
} I2C_AD_CMD; /* if AD_ADDR = 02h */ u_char IOUT_DATA:8;
} bt252_iout1;
} I2C_AD_CMD;
/***** Global declarations of local copies of boards' 8 bit I2C registers ***/ /***** Global declarations of local copies of boards' 8 bit I2C registers ***/
......
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