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nexedi
linux
Commits
064e8af7
Commit
064e8af7
authored
Jun 15, 2020
by
Mark Brown
Browse files
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Plain Diff
Merge existing fixes from spi/for-5.8
parents
b3a9e3b9
27784a25
Changes
6
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6 changed files
with
52 additions
and
26 deletions
+52
-26
Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
...ation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
+17
-9
drivers/spi/spi-fsl-dspi.c
drivers/spi/spi-fsl-dspi.c
+4
-4
drivers/spi/spi-rspi.c
drivers/spi/spi-rspi.c
+21
-7
drivers/spi/spi-sprd-adi.c
drivers/spi/spi-sprd-adi.c
+1
-1
include/uapi/linux/spi/spidev.h
include/uapi/linux/spi/spidev.h
+4
-0
tools/spi/spidev_test.c
tools/spi/spidev_test.c
+5
-5
No files found.
Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
View file @
064e8af7
...
@@ -34,12 +34,15 @@ properties:
...
@@ -34,12 +34,15 @@ properties:
maxItems
:
1
maxItems
:
1
clocks
:
clocks
:
maxItems
:
1
minItems
:
1
maxItems
:
2
items
:
-
description
:
controller register bus clock
-
description
:
baud rate generator and delay control clock
clock-names
:
clock-names
:
description
:
input clock for the baud rate generator
minItems
:
1
items
:
maxItems
:
2
-
const
:
core
if
:
if
:
properties
:
properties
:
...
@@ -51,17 +54,22 @@ if:
...
@@ -51,17 +54,22 @@ if:
then
:
then
:
properties
:
properties
:
clocks
:
clocks
:
contains
:
minItems
:
2
items
:
-
description
:
controller register bus clock
-
description
:
baud rate generator and delay control clock
clock-names
:
clock-names
:
minItems
:
2
items
:
items
:
-
const
:
core
-
const
:
core
-
const
:
pclk
-
const
:
pclk
else
:
properties
:
clocks
:
maxItems
:
1
clock-names
:
items
:
-
const
:
core
required
:
required
:
-
compatible
-
compatible
-
reg
-
reg
...
...
drivers/spi/spi-fsl-dspi.c
View file @
064e8af7
...
@@ -588,14 +588,14 @@ static void dspi_release_dma(struct fsl_dspi *dspi)
...
@@ -588,14 +588,14 @@ static void dspi_release_dma(struct fsl_dspi *dspi)
return
;
return
;
if
(
dma
->
chan_tx
)
{
if
(
dma
->
chan_tx
)
{
dma_
unmap_single
(
dma
->
chan_tx
->
device
->
dev
,
dma
->
tx_dma_phys
,
dma_
free_coherent
(
dma
->
chan_tx
->
device
->
dev
,
dma_bufsize
,
dma_bufsize
,
DMA_TO_DEVICE
);
dma
->
tx_dma_buf
,
dma
->
tx_dma_phys
);
dma_release_channel
(
dma
->
chan_tx
);
dma_release_channel
(
dma
->
chan_tx
);
}
}
if
(
dma
->
chan_rx
)
{
if
(
dma
->
chan_rx
)
{
dma_
unmap_single
(
dma
->
chan_rx
->
device
->
dev
,
dma
->
rx_dma_phys
,
dma_
free_coherent
(
dma
->
chan_rx
->
device
->
dev
,
dma_bufsize
,
dma_bufsize
,
DMA_FROM_DEVICE
);
dma
->
rx_dma_buf
,
dma
->
rx_dma_phys
);
dma_release_channel
(
dma
->
chan_rx
);
dma_release_channel
(
dma
->
chan_rx
);
}
}
}
}
...
...
drivers/spi/spi-rspi.c
View file @
064e8af7
...
@@ -179,7 +179,7 @@
...
@@ -179,7 +179,7 @@
struct
rspi_data
{
struct
rspi_data
{
void
__iomem
*
addr
;
void
__iomem
*
addr
;
u32
max_
speed_hz
;
u32
speed_hz
;
struct
spi_controller
*
ctlr
;
struct
spi_controller
*
ctlr
;
struct
platform_device
*
pdev
;
struct
platform_device
*
pdev
;
wait_queue_head_t
wait
;
wait_queue_head_t
wait
;
...
@@ -258,8 +258,7 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
...
@@ -258,8 +258,7 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
rspi_write8
(
rspi
,
rspi
->
sppcr
,
RSPI_SPPCR
);
rspi_write8
(
rspi
,
rspi
->
sppcr
,
RSPI_SPPCR
);
/* Sets transfer bit rate */
/* Sets transfer bit rate */
spbr
=
DIV_ROUND_UP
(
clk_get_rate
(
rspi
->
clk
),
spbr
=
DIV_ROUND_UP
(
clk_get_rate
(
rspi
->
clk
),
2
*
rspi
->
speed_hz
)
-
1
;
2
*
rspi
->
max_speed_hz
)
-
1
;
rspi_write8
(
rspi
,
clamp
(
spbr
,
0
,
255
),
RSPI_SPBR
);
rspi_write8
(
rspi
,
clamp
(
spbr
,
0
,
255
),
RSPI_SPBR
);
/* Disable dummy transmission, set 16-bit word access, 1 frame */
/* Disable dummy transmission, set 16-bit word access, 1 frame */
...
@@ -299,14 +298,14 @@ static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
...
@@ -299,14 +298,14 @@ static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
clksrc
=
clk_get_rate
(
rspi
->
clk
);
clksrc
=
clk_get_rate
(
rspi
->
clk
);
while
(
div
<
3
)
{
while
(
div
<
3
)
{
if
(
rspi
->
max_
speed_hz
>=
clksrc
/
4
)
/* 4=(CLK/2)/2 */
if
(
rspi
->
speed_hz
>=
clksrc
/
4
)
/* 4=(CLK/2)/2 */
break
;
break
;
div
++
;
div
++
;
clksrc
/=
2
;
clksrc
/=
2
;
}
}
/* Sets transfer bit rate */
/* Sets transfer bit rate */
spbr
=
DIV_ROUND_UP
(
clksrc
,
2
*
rspi
->
max_
speed_hz
)
-
1
;
spbr
=
DIV_ROUND_UP
(
clksrc
,
2
*
rspi
->
speed_hz
)
-
1
;
rspi_write8
(
rspi
,
clamp
(
spbr
,
0
,
255
),
RSPI_SPBR
);
rspi_write8
(
rspi
,
clamp
(
spbr
,
0
,
255
),
RSPI_SPBR
);
rspi
->
spcmd
|=
div
<<
2
;
rspi
->
spcmd
|=
div
<<
2
;
...
@@ -341,7 +340,7 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
...
@@ -341,7 +340,7 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
rspi_write8
(
rspi
,
rspi
->
sppcr
,
RSPI_SPPCR
);
rspi_write8
(
rspi
,
rspi
->
sppcr
,
RSPI_SPPCR
);
/* Sets transfer bit rate */
/* Sets transfer bit rate */
spbr
=
DIV_ROUND_UP
(
clk_get_rate
(
rspi
->
clk
),
2
*
rspi
->
max_
speed_hz
);
spbr
=
DIV_ROUND_UP
(
clk_get_rate
(
rspi
->
clk
),
2
*
rspi
->
speed_hz
);
rspi_write8
(
rspi
,
clamp
(
spbr
,
0
,
255
),
RSPI_SPBR
);
rspi_write8
(
rspi
,
clamp
(
spbr
,
0
,
255
),
RSPI_SPBR
);
/* Disable dummy transmission, set byte access */
/* Disable dummy transmission, set byte access */
...
@@ -949,9 +948,24 @@ static int rspi_prepare_message(struct spi_controller *ctlr,
...
@@ -949,9 +948,24 @@ static int rspi_prepare_message(struct spi_controller *ctlr,
{
{
struct
rspi_data
*
rspi
=
spi_controller_get_devdata
(
ctlr
);
struct
rspi_data
*
rspi
=
spi_controller_get_devdata
(
ctlr
);
struct
spi_device
*
spi
=
msg
->
spi
;
struct
spi_device
*
spi
=
msg
->
spi
;
const
struct
spi_transfer
*
xfer
;
int
ret
;
int
ret
;
rspi
->
max_speed_hz
=
spi
->
max_speed_hz
;
/*
* As the Bit Rate Register must not be changed while the device is
* active, all transfers in a message must use the same bit rate.
* In theory, the sequencer could be enabled, and each Command Register
* could divide the base bit rate by a different value.
* However, most RSPI variants do not have Transfer Data Length
* Multiplier Setting Registers, so each sequence step would be limited
* to a single word, making this feature unsuitable for large
* transfers, which would gain most from it.
*/
rspi
->
speed_hz
=
spi
->
max_speed_hz
;
list_for_each_entry
(
xfer
,
&
msg
->
transfers
,
transfer_list
)
{
if
(
xfer
->
speed_hz
<
rspi
->
speed_hz
)
rspi
->
speed_hz
=
xfer
->
speed_hz
;
}
rspi
->
spcmd
=
SPCMD_SSLKP
;
rspi
->
spcmd
=
SPCMD_SSLKP
;
if
(
spi
->
mode
&
SPI_CPOL
)
if
(
spi
->
mode
&
SPI_CPOL
)
...
...
drivers/spi/spi-sprd-adi.c
View file @
064e8af7
...
@@ -389,9 +389,9 @@ static int sprd_adi_restart_handler(struct notifier_block *this,
...
@@ -389,9 +389,9 @@ static int sprd_adi_restart_handler(struct notifier_block *this,
sprd_adi_write
(
sadi
,
sadi
->
slave_pbase
+
REG_WDG_CTRL
,
val
);
sprd_adi_write
(
sadi
,
sadi
->
slave_pbase
+
REG_WDG_CTRL
,
val
);
/* Load the watchdog timeout value, 50ms is always enough. */
/* Load the watchdog timeout value, 50ms is always enough. */
sprd_adi_write
(
sadi
,
sadi
->
slave_pbase
+
REG_WDG_LOAD_HIGH
,
0
);
sprd_adi_write
(
sadi
,
sadi
->
slave_pbase
+
REG_WDG_LOAD_LOW
,
sprd_adi_write
(
sadi
,
sadi
->
slave_pbase
+
REG_WDG_LOAD_LOW
,
WDG_LOAD_VAL
&
WDG_LOAD_MASK
);
WDG_LOAD_VAL
&
WDG_LOAD_MASK
);
sprd_adi_write
(
sadi
,
sadi
->
slave_pbase
+
REG_WDG_LOAD_HIGH
,
0
);
/* Start the watchdog to reset system */
/* Start the watchdog to reset system */
sprd_adi_read
(
sadi
,
sadi
->
slave_pbase
+
REG_WDG_CTRL
,
&
val
);
sprd_adi_read
(
sadi
,
sadi
->
slave_pbase
+
REG_WDG_CTRL
,
&
val
);
...
...
include/uapi/linux/spi/spidev.h
View file @
064e8af7
...
@@ -48,6 +48,10 @@
...
@@ -48,6 +48,10 @@
#define SPI_TX_QUAD 0x200
#define SPI_TX_QUAD 0x200
#define SPI_RX_DUAL 0x400
#define SPI_RX_DUAL 0x400
#define SPI_RX_QUAD 0x800
#define SPI_RX_QUAD 0x800
#define SPI_CS_WORD 0x1000
#define SPI_TX_OCTAL 0x2000
#define SPI_RX_OCTAL 0x4000
#define SPI_3WIRE_HIZ 0x8000
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
...
...
tools/spi/spidev_test.c
View file @
064e8af7
...
@@ -47,7 +47,7 @@ static int transfer_size;
...
@@ -47,7 +47,7 @@ static int transfer_size;
static
int
iterations
;
static
int
iterations
;
static
int
interval
=
5
;
/* interval in seconds for showing transfer rate */
static
int
interval
=
5
;
/* interval in seconds for showing transfer rate */
uint8_t
default_tx
[]
=
{
static
uint8_t
default_tx
[]
=
{
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0x40
,
0x00
,
0x00
,
0x00
,
0x00
,
0x95
,
0x40
,
0x00
,
0x00
,
0x00
,
0x00
,
0x95
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
0xFF
,
...
@@ -56,8 +56,8 @@ uint8_t default_tx[] = {
...
@@ -56,8 +56,8 @@ uint8_t default_tx[] = {
0xF0
,
0x0D
,
0xF0
,
0x0D
,
};
};
uint8_t
default_rx
[
ARRAY_SIZE
(
default_tx
)]
=
{
0
,
};
static
uint8_t
default_rx
[
ARRAY_SIZE
(
default_tx
)]
=
{
0
,
};
char
*
input_tx
;
static
char
*
input_tx
;
static
void
hex_dump
(
const
void
*
src
,
size_t
length
,
size_t
line_size
,
static
void
hex_dump
(
const
void
*
src
,
size_t
length
,
size_t
line_size
,
char
*
prefix
)
char
*
prefix
)
...
@@ -461,8 +461,8 @@ int main(int argc, char *argv[])
...
@@ -461,8 +461,8 @@ int main(int argc, char *argv[])
pabort
(
"can't get max speed hz"
);
pabort
(
"can't get max speed hz"
);
printf
(
"spi mode: 0x%x
\n
"
,
mode
);
printf
(
"spi mode: 0x%x
\n
"
,
mode
);
printf
(
"bits per word: %
d
\n
"
,
bits
);
printf
(
"bits per word: %
u
\n
"
,
bits
);
printf
(
"max speed: %
d Hz (%d K
Hz)
\n
"
,
speed
,
speed
/
1000
);
printf
(
"max speed: %
u Hz (%u k
Hz)
\n
"
,
speed
,
speed
/
1000
);
if
(
input_tx
)
if
(
input_tx
)
transfer_escaped_string
(
fd
,
input_tx
);
transfer_escaped_string
(
fd
,
input_tx
);
...
...
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