Commit 0ff59f31 authored by Krzysztof Hałasa's avatar Krzysztof Hałasa Committed by Mauro Carvalho Chehab

[media] TW686x frame grabber driver

A driver for Intersil/Techwell TW686x-based PCIe frame grabbers.

[hans.verkuil@cisco.com: renamed staging tw686x to tw686x-kh to prevent naming conflicts]
[hans.verkuil@cisco.com: don't build tw686x-kh if tw686x is already selected to prevent conflicts]
[mchehab@osg.samsung.com: use "unsigned int" instead of just "unsigned"  and add some whitespaces to make checkpatch happier]
Signed-off-by: default avatarKrzysztof Halasa <khalasa@piap.pl>
Signed-off-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Tested-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@osg.samsung.com>
parent 5ed470fe
...@@ -37,6 +37,8 @@ source "drivers/staging/media/omap4iss/Kconfig" ...@@ -37,6 +37,8 @@ source "drivers/staging/media/omap4iss/Kconfig"
source "drivers/staging/media/timb/Kconfig" source "drivers/staging/media/timb/Kconfig"
source "drivers/staging/media/tw686x-kh/Kconfig"
# Keep LIRC at the end, as it has sub-menus # Keep LIRC at the end, as it has sub-menus
source "drivers/staging/media/lirc/Kconfig" source "drivers/staging/media/lirc/Kconfig"
......
...@@ -8,3 +8,4 @@ obj-$(CONFIG_VIDEO_OMAP1) += omap1/ ...@@ -8,3 +8,4 @@ obj-$(CONFIG_VIDEO_OMAP1) += omap1/
obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/ obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/
obj-$(CONFIG_DVB_MN88472) += mn88472/ obj-$(CONFIG_DVB_MN88472) += mn88472/
obj-$(CONFIG_VIDEO_TIMBERDALE) += timb/ obj-$(CONFIG_VIDEO_TIMBERDALE) += timb/
obj-$(CONFIG_VIDEO_TW686X_KH) += tw686x-kh/
config VIDEO_TW686X_KH
tristate "Intersil/Techwell TW686x Video For Linux"
depends on VIDEO_DEV && PCI && VIDEO_V4L2
depends on !(VIDEO_TW686X=y || VIDEO_TW686X=m) || COMPILE_TEST
select VIDEOBUF2_DMA_SG
help
Support for Intersil/Techwell TW686x-based frame grabber cards.
Currently supported chips:
- TW6864 (4 video channels),
- TW6865 (4 video channels, not tested, second generation chip),
- TW6868 (8 video channels but only 4 first channels using
built-in video decoder are supported, not tested),
- TW6869 (8 video channels, second generation chip).
To compile this driver as a module, choose M here: the module
will be named tw686x-kh.
tw686x-kh-objs := tw686x-kh-core.o tw686x-kh-video.o
obj-$(CONFIG_VIDEO_TW686X_KH) += tw686x-kh.o
TODO: implement V4L2_FIELD_INTERLACED* mode(s).
Please Cc: patches to Krzysztof Halasa <khalasa@piap.pl>.
/*
* Copyright (C) 2015 Industrial Research Institute for Automation
* and Measurements PIAP
*
* Written by Krzysztof Ha?asa.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License
* as published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include "tw686x-kh.h"
#include "tw686x-kh-regs.h"
static irqreturn_t tw686x_irq(int irq, void *dev_id)
{
struct tw686x_dev *dev = (struct tw686x_dev *)dev_id;
u32 int_status = reg_read(dev, INT_STATUS); /* cleared on read */
unsigned long flags;
unsigned int handled = 0;
if (int_status) {
spin_lock_irqsave(&dev->irq_lock, flags);
dev->dma_requests |= int_status;
spin_unlock_irqrestore(&dev->irq_lock, flags);
if (int_status & 0xFF0000FF)
handled = tw686x_video_irq(dev);
}
return IRQ_RETVAL(handled);
}
static int tw686x_probe(struct pci_dev *pci_dev,
const struct pci_device_id *pci_id)
{
struct tw686x_dev *dev;
int err;
dev = devm_kzalloc(&pci_dev->dev, sizeof(*dev) +
(pci_id->driver_data & TYPE_MAX_CHANNELS) *
sizeof(dev->video_channels[0]), GFP_KERNEL);
if (!dev)
return -ENOMEM;
sprintf(dev->name, "TW%04X", pci_dev->device);
dev->type = pci_id->driver_data;
pr_info("%s: PCI %s, IRQ %d, MMIO 0x%lx\n", dev->name,
pci_name(pci_dev), pci_dev->irq,
(unsigned long)pci_resource_start(pci_dev, 0));
dev->pci_dev = pci_dev;
if (pcim_enable_device(pci_dev))
return -EIO;
pci_set_master(pci_dev);
if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32))) {
pr_err("%s: 32-bit PCI DMA not supported\n", dev->name);
return -EIO;
}
err = pci_request_regions(pci_dev, dev->name);
if (err < 0) {
pr_err("%s: Unable to get MMIO region\n", dev->name);
return err;
}
dev->mmio = pci_ioremap_bar(pci_dev, 0);
if (!dev->mmio) {
pr_err("%s: Unable to remap MMIO region\n", dev->name);
return -EIO;
}
reg_write(dev, SYS_SOFT_RST, 0x0F); /* Reset all subsystems */
mdelay(1);
reg_write(dev, SRST[0], 0x3F);
if (max_channels(dev) > 4)
reg_write(dev, SRST[1], 0x3F);
reg_write(dev, DMA_CMD, 0);
reg_write(dev, DMA_CHANNEL_ENABLE, 0);
reg_write(dev, DMA_CHANNEL_TIMEOUT, 0x3EFF0FF0);
reg_write(dev, DMA_TIMER_INTERVAL, 0x38000);
reg_write(dev, DMA_CONFIG, 0xFFFFFF04);
spin_lock_init(&dev->irq_lock);
err = devm_request_irq(&pci_dev->dev, pci_dev->irq, tw686x_irq,
IRQF_SHARED, dev->name, dev);
if (err < 0) {
pr_err("%s: Unable to get IRQ\n", dev->name);
return err;
}
err = tw686x_video_init(dev);
if (err)
return err;
pci_set_drvdata(pci_dev, dev);
return 0;
}
static void tw686x_remove(struct pci_dev *pci_dev)
{
struct tw686x_dev *dev = pci_get_drvdata(pci_dev);
tw686x_video_free(dev);
}
/* driver_data is number of A/V channels */
static const struct pci_device_id tw686x_pci_tbl[] = {
{PCI_DEVICE(0x1797, 0x6864), .driver_data = 4},
/* not tested */
{PCI_DEVICE(0x1797, 0x6865), .driver_data = 4 | TYPE_SECOND_GEN},
/* TW6868 supports 8 A/V channels with an external TW2865 chip -
not supported by the driver */
{PCI_DEVICE(0x1797, 0x6868), .driver_data = 4}, /* not tested */
{PCI_DEVICE(0x1797, 0x6869), .driver_data = 8 | TYPE_SECOND_GEN},
{}
};
static struct pci_driver tw686x_pci_driver = {
.name = "tw686x-kh",
.id_table = tw686x_pci_tbl,
.probe = tw686x_probe,
.remove = tw686x_remove,
};
MODULE_DESCRIPTION("Driver for video frame grabber cards based on Intersil/Techwell TW686[4589]");
MODULE_AUTHOR("Krzysztof Halasa");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(pci, tw686x_pci_tbl);
module_pci_driver(tw686x_pci_driver);
/* DMA controller registers */
#define REG8_1(a0) ((const u16[8]) {a0, a0 + 1, a0 + 2, a0 + 3, \
a0 + 4, a0 + 5, a0 + 6, a0 + 7})
#define REG8_2(a0) ((const u16[8]) {a0, a0 + 2, a0 + 4, a0 + 6, \
a0 + 8, a0 + 0xA, a0 + 0xC, a0 + 0xE})
#define REG8_8(a0) ((const u16[8]) {a0, a0 + 8, a0 + 0x10, a0 + 0x18, \
a0 + 0x20, a0 + 0x28, a0 + 0x30, a0 + 0x38})
#define INT_STATUS 0x00
#define PB_STATUS 0x01
#define DMA_CMD 0x02
#define VIDEO_FIFO_STATUS 0x03
#define VIDEO_CHANNEL_ID 0x04
#define VIDEO_PARSER_STATUS 0x05
#define SYS_SOFT_RST 0x06
#define DMA_PAGE_TABLE0_ADDR ((const u16[8]) {0x08, 0xD0, 0xD2, 0xD4, \
0xD6, 0xD8, 0xDA, 0xDC})
#define DMA_PAGE_TABLE1_ADDR ((const u16[8]) {0x09, 0xD1, 0xD3, 0xD5, \
0xD7, 0xD9, 0xDB, 0xDD})
#define DMA_CHANNEL_ENABLE 0x0A
#define DMA_CONFIG 0x0B
#define DMA_TIMER_INTERVAL 0x0C
#define DMA_CHANNEL_TIMEOUT 0x0D
#define VDMA_CHANNEL_CONFIG REG8_1(0x10)
#define ADMA_P_ADDR REG8_2(0x18)
#define ADMA_B_ADDR REG8_2(0x19)
#define DMA10_P_ADDR 0x28 /* ??? */
#define DMA10_B_ADDR 0x29
#define VIDEO_CONTROL1 0x2A
#define VIDEO_CONTROL2 0x2B
#define AUDIO_CONTROL1 0x2C
#define AUDIO_CONTROL2 0x2D
#define PHASE_REF 0x2E
#define GPIO_REG 0x2F
#define INTL_HBAR_CTRL REG8_1(0x30)
#define AUDIO_CONTROL3 0x38
#define VIDEO_FIELD_CTRL REG8_1(0x39)
#define HSCALER_CTRL REG8_1(0x42)
#define VIDEO_SIZE REG8_1(0x4A)
#define VIDEO_SIZE_F2 REG8_1(0x52)
#define MD_CONF REG8_1(0x60)
#define MD_INIT REG8_1(0x68)
#define MD_MAP0 REG8_1(0x70)
#define VDMA_P_ADDR REG8_8(0x80) /* not used in DMA SG mode */
#define VDMA_WHP REG8_8(0x81)
#define VDMA_B_ADDR REG8_8(0x82)
#define VDMA_F2_P_ADDR REG8_8(0x84)
#define VDMA_F2_WHP REG8_8(0x85)
#define VDMA_F2_B_ADDR REG8_8(0x86)
#define EP_REG_ADDR 0xFE
#define EP_REG_DATA 0xFF
/* Video decoder registers */
#define VDREG8(a0) ((const u16[8]) { \
a0 + 0x000, a0 + 0x010, a0 + 0x020, a0 + 0x030, \
a0 + 0x100, a0 + 0x110, a0 + 0x120, a0 + 0x130})
#define VIDSTAT VDREG8(0x100)
#define BRIGHT VDREG8(0x101)
#define CONTRAST VDREG8(0x102)
#define SHARPNESS VDREG8(0x103)
#define SAT_U VDREG8(0x104)
#define SAT_V VDREG8(0x105)
#define HUE VDREG8(0x106)
#define CROP_HI VDREG8(0x107)
#define VDELAY_LO VDREG8(0x108)
#define VACTIVE_LO VDREG8(0x109)
#define HDELAY_LO VDREG8(0x10A)
#define HACTIVE_LO VDREG8(0x10B)
#define MVSN VDREG8(0x10C)
#define STATUS2 VDREG8(0x10C)
#define SDT VDREG8(0x10E)
#define SDT_EN VDREG8(0x10F)
#define VSCALE_LO VDREG8(0x144)
#define SCALE_HI VDREG8(0x145)
#define HSCALE_LO VDREG8(0x146)
#define F2CROP_HI VDREG8(0x147)
#define F2VDELAY_LO VDREG8(0x148)
#define F2VACTIVE_LO VDREG8(0x149)
#define F2HDELAY_LO VDREG8(0x14A)
#define F2HACTIVE_LO VDREG8(0x14B)
#define F2VSCALE_LO VDREG8(0x14C)
#define F2SCALE_HI VDREG8(0x14D)
#define F2HSCALE_LO VDREG8(0x14E)
#define F2CNT VDREG8(0x14F)
#define VDREG2(a0) ((const u16[2]) {a0, a0 + 0x100})
#define SRST VDREG2(0x180)
#define ACNTL VDREG2(0x181)
#define ACNTL2 VDREG2(0x182)
#define CNTRL1 VDREG2(0x183)
#define CKHY VDREG2(0x184)
#define SHCOR VDREG2(0x185)
#define CORING VDREG2(0x186)
#define CLMPG VDREG2(0x187)
#define IAGC VDREG2(0x188)
#define VCTRL1 VDREG2(0x18F)
#define MISC1 VDREG2(0x194)
#define LOOP VDREG2(0x195)
#define MISC2 VDREG2(0x196)
#define CLMD VDREG2(0x197)
#define AIGAIN ((const u16[8]) {0x1D0, 0x1D1, 0x1D2, 0x1D3, \
0x2D0, 0x2D1, 0x2D2, 0x2D3})
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/*
* Copyright (C) 2015 Industrial Research Institute for Automation
* and Measurements PIAP
*
* Written by Krzysztof Ha?asa.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License
* as published by the Free Software Foundation.
*/
#include <linux/delay.h>
#include <linux/freezer.h>
#include <linux/interrupt.h>
#include <linux/kthread.h>
#include <linux/mutex.h>
#include <linux/pci.h>
#include <media/videobuf2-dma-sg.h>
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ioctl.h>
#define TYPE_MAX_CHANNELS 0x0F
#define TYPE_SECOND_GEN 0x10
struct tw686x_format {
char *name;
unsigned int fourcc;
unsigned int depth;
unsigned int mode;
};
struct dma_desc {
dma_addr_t phys;
void *virt;
unsigned int size;
};
struct vdma_desc {
__le32 flags_length; /* 3 MSBits for flags, 13 LSBits for length */
__le32 phys;
};
struct tw686x_vb2_buf {
struct vb2_v4l2_buffer vb;
struct list_head list;
};
struct tw686x_video_channel {
struct tw686x_dev *dev;
struct vb2_queue vidq;
struct list_head vidq_queued;
struct video_device *device;
struct dma_desc sg_tables[2];
struct tw686x_vb2_buf *curr_bufs[2];
void *alloc_ctx;
struct vdma_desc *sg_descs[2];
struct v4l2_ctrl_handler ctrl_handler;
const struct tw686x_format *format;
struct mutex vb_mutex;
spinlock_t qlock;
v4l2_std_id video_standard;
unsigned int width, height;
enum v4l2_field field; /* supported TOP, BOTTOM, SEQ_TB and SEQ_BT */
unsigned int seq; /* video field or frame counter */
unsigned int ch;
};
/* global device status */
struct tw686x_dev {
spinlock_t irq_lock;
struct v4l2_device v4l2_dev;
struct snd_card *card; /* sound card */
unsigned int video_active; /* active video channel mask */
char name[32];
unsigned int type;
struct pci_dev *pci_dev;
__u32 __iomem *mmio;
struct task_struct *video_thread;
wait_queue_head_t video_thread_wait;
u32 dma_requests;
struct tw686x_video_channel video_channels[0];
};
static inline uint32_t reg_read(struct tw686x_dev *dev, unsigned int reg)
{
return readl(dev->mmio + reg);
}
static inline void reg_write(struct tw686x_dev *dev, unsigned int reg,
uint32_t value)
{
writel(value, dev->mmio + reg);
}
static inline unsigned int max_channels(struct tw686x_dev *dev)
{
return dev->type & TYPE_MAX_CHANNELS; /* 4 or 8 channels */
}
static inline unsigned int is_second_gen(struct tw686x_dev *dev)
{
/* each channel has its own DMA SG table */
return dev->type & TYPE_SECOND_GEN;
}
int tw686x_video_irq(struct tw686x_dev *dev);
int tw686x_video_init(struct tw686x_dev *dev);
void tw686x_video_free(struct tw686x_dev *dev);
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