Commit 127a2628 authored by David Zhang's avatar David Zhang Committed by Alex Deucher

drm/amdgpu: Add Fiji support to the GMC 8.5 IP module

Signed-off-by: default avatarDavid Zhang <david1.zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
parent 48299f95
...@@ -44,6 +44,7 @@ static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); ...@@ -44,6 +44,7 @@ static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
MODULE_FIRMWARE("amdgpu/topaz_mc.bin"); MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
MODULE_FIRMWARE("amdgpu/fiji_mc.bin");
static const u32 golden_settings_tonga_a11[] = static const u32 golden_settings_tonga_a11[] =
{ {
...@@ -61,6 +62,19 @@ static const u32 tonga_mgcg_cgcg_init[] = ...@@ -61,6 +62,19 @@ static const u32 tonga_mgcg_cgcg_init[] =
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
}; };
static const u32 golden_settings_fiji_a10[] =
{
mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
};
static const u32 fiji_mgcg_cgcg_init[] =
{
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
};
static const u32 golden_settings_iceland_a11[] = static const u32 golden_settings_iceland_a11[] =
{ {
mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
...@@ -90,6 +104,14 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -90,6 +104,14 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_iceland_a11, golden_settings_iceland_a11,
(const u32)ARRAY_SIZE(golden_settings_iceland_a11)); (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
break; break;
case CHIP_FIJI:
amdgpu_program_register_sequence(adev,
fiji_mgcg_cgcg_init,
(const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_fiji_a10,
(const u32)ARRAY_SIZE(golden_settings_fiji_a10));
break;
case CHIP_TONGA: case CHIP_TONGA:
amdgpu_program_register_sequence(adev, amdgpu_program_register_sequence(adev,
tonga_mgcg_cgcg_init, tonga_mgcg_cgcg_init,
...@@ -202,6 +224,9 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) ...@@ -202,6 +224,9 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
case CHIP_TONGA: case CHIP_TONGA:
chip_name = "tonga"; chip_name = "tonga";
break; break;
case CHIP_FIJI:
chip_name = "fiji";
break;
case CHIP_CARRIZO: case CHIP_CARRIZO:
return 0; return 0;
default: BUG(); default: BUG();
......
...@@ -1173,7 +1173,14 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] = ...@@ -1173,7 +1173,14 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
.minor = 0, .minor = 0,
.rev = 0, .rev = 0,
.funcs = &vi_common_ip_funcs, .funcs = &vi_common_ip_funcs,
} },
{
.type = AMD_IP_BLOCK_TYPE_GMC,
.major = 8,
.minor = 5,
.rev = 0,
.funcs = &gmc_v8_0_ip_funcs,
},
}; };
static const struct amdgpu_ip_block_version cz_ip_blocks[] = static const struct amdgpu_ip_block_version cz_ip_blocks[] =
......
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