Skip to content

L
linux
Commit 167327d6 authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
Browse files
Options

drm/amd/amdgpu: Clean up GFX6 tilemode programming 

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f5f3b16a
Hide whitespace changes
Inline Side-by-side
Showing with 676 additions and 880 deletions
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
View file @ 167327d6
...@@ -393,8 +393,11 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) ...@@ -393,8 +393,11 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
{ {
const u32 num_tile_mode_states = 32; const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
u32 reg_offset, gb_tile_moden, split_equal_to_row_size; u32 reg_offset, split_equal_to_row_size, *tilemode;
memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
tilemode = adev->gfx.config.tile_mode_array;
switch (adev->gfx.config.mem_row_size_in_kb) { switch (adev->gfx.config.mem_row_size_in_kb) {
case 1: case 1:
...@@ -410,887 +413,680 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) ...@@ -410,887 +413,680 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
} }
if (adev->asic_type == CHIP_VERDE) { if (adev->asic_type == CHIP_VERDE) {
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
switch (reg_offset) { ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 0: PIPE_CONFIG(ADDR_SURF_P4_8x16) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | NUM_BANKS(ADDR_SURF_16_BANK);
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_16_BANK)); PIPE_CONFIG(ADDR_SURF_P4_8x16) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
case 1: BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | NUM_BANKS(ADDR_SURF_16_BANK);
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
case 2: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | NUM_BANKS(ADDR_SURF_16_BANK);
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_8_BANK) |
break; TILE_SPLIT(split_equal_to_row_size);
case 3: tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_8x16);
PIPE_CONFIG(ADDR_SURF_P4_8x16) | tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
NUM_BANKS(ADDR_SURF_8_BANK) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
TILE_SPLIT(split_equal_to_row_size)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
case 4: NUM_BANKS(ADDR_SURF_4_BANK);
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
ARRAY_MODE(ARRAY_1D_TILED_THIN1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16)); PIPE_CONFIG(ADDR_SURF_P4_8x16) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
case 5: BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | NUM_BANKS(ADDR_SURF_4_BANK);
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
NUM_BANKS(ADDR_SURF_4_BANK)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
case 6: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | NUM_BANKS(ADDR_SURF_2_BANK);
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
PIPE_CONFIG(ADDR_SURF_P4_8x16) | tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P4_8x16);
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_4_BANK)); PIPE_CONFIG(ADDR_SURF_P4_8x16) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
case 7: BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | NUM_BANKS(ADDR_SURF_16_BANK);
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_2_BANK)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
case 8: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); NUM_BANKS(ADDR_SURF_16_BANK);
break; tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
case 9: ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
ARRAY_MODE(ARRAY_1D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
PIPE_CONFIG(ADDR_SURF_P4_8x16)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
case 10: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | NUM_BANKS(ADDR_SURF_16_BANK);
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | PIPE_CONFIG(ADDR_SURF_P4_8x16);
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
NUM_BANKS(ADDR_SURF_16_BANK)); TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
break; BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 11: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | NUM_BANKS(ADDR_SURF_16_BANK);
PIPE_CONFIG(ADDR_SURF_P4_8x16) | tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
case 12: NUM_BANKS(ADDR_SURF_16_BANK);
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK);
break; tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
case 13: ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
ARRAY_MODE(ARRAY_1D_TILED_THIN1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
case 14: NUM_BANKS(ADDR_SURF_16_BANK) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | TILE_SPLIT(split_equal_to_row_size);
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | ARRAY_MODE(ARRAY_1D_TILED_THICK) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | PIPE_CONFIG(ADDR_SURF_P4_8x16);
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
NUM_BANKS(ADDR_SURF_16_BANK)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
case 15: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | NUM_BANKS(ADDR_SURF_16_BANK) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(split_equal_to_row_size);
PIPE_CONFIG(ADDR_SURF_P4_8x16) | tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ARRAY_MODE(ARRAY_2D_TILED_THICK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
break; NUM_BANKS(ADDR_SURF_16_BANK) |
case 16: TILE_SPLIT(split_equal_to_row_size);
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_8_BANK);
break; tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
case 17: ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | NUM_BANKS(ADDR_SURF_8_BANK);
NUM_BANKS(ADDR_SURF_16_BANK) | tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
TILE_SPLIT(split_equal_to_row_size)); ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; PIPE_CONFIG(ADDR_SURF_P4_8x16) |
case 18: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
ARRAY_MODE(ARRAY_1D_TILED_THICK) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
PIPE_CONFIG(ADDR_SURF_P4_8x16)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
break; NUM_BANKS(ADDR_SURF_4_BANK);
case 19: tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK) | NUM_BANKS(ADDR_SURF_4_BANK);
TILE_SPLIT(split_equal_to_row_size)); tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
break; ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 20: PIPE_CONFIG(ADDR_SURF_P4_8x16) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
ARRAY_MODE(ARRAY_2D_TILED_THICK) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | NUM_BANKS(ADDR_SURF_2_BANK);
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
NUM_BANKS(ADDR_SURF_16_BANK) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(split_equal_to_row_size)); PIPE_CONFIG(ADDR_SURF_P4_8x16) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
case 21: BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | NUM_BANKS(ADDR_SURF_2_BANK);
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
NUM_BANKS(ADDR_SURF_8_BANK)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
case 22: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | NUM_BANKS(ADDR_SURF_2_BANK);
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
NUM_BANKS(ADDR_SURF_8_BANK)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
break; NUM_BANKS(ADDR_SURF_2_BANK);
case 23: tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | NUM_BANKS(ADDR_SURF_2_BANK);
NUM_BANKS(ADDR_SURF_4_BANK)); tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
break; ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 24: PIPE_CONFIG(ADDR_SURF_P4_8x16) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | NUM_BANKS(ADDR_SURF_2_BANK);
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
NUM_BANKS(ADDR_SURF_4_BANK)); } else if (adev->asic_type == CHIP_OLAND || adev->asic_type == CHIP_HAINAN) {
break; tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
case 25: ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P2) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | NUM_BANKS(ADDR_SURF_16_BANK);
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
NUM_BANKS(ADDR_SURF_2_BANK)); ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; PIPE_CONFIG(ADDR_SURF_P2) |
case 26: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | NUM_BANKS(ADDR_SURF_16_BANK);
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | PIPE_CONFIG(ADDR_SURF_P2) |
NUM_BANKS(ADDR_SURF_2_BANK)); TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
break; BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 27: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | NUM_BANKS(ADDR_SURF_16_BANK);
PIPE_CONFIG(ADDR_SURF_P4_8x16) | tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
NUM_BANKS(ADDR_SURF_2_BANK)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
break; NUM_BANKS(ADDR_SURF_8_BANK) |
case 28: TILE_SPLIT(split_equal_to_row_size);
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | PIPE_CONFIG(ADDR_SURF_P2);
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | PIPE_CONFIG(ADDR_SURF_P2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
NUM_BANKS(ADDR_SURF_2_BANK)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
case 29: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | NUM_BANKS(ADDR_SURF_8_BANK);
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | PIPE_CONFIG(ADDR_SURF_P2) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
NUM_BANKS(ADDR_SURF_2_BANK)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
break; NUM_BANKS(ADDR_SURF_8_BANK);
case 30: tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P2) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | NUM_BANKS(ADDR_SURF_4_BANK);
NUM_BANKS(ADDR_SURF_2_BANK)); tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
break; tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
default: ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
continue; PIPE_CONFIG(ADDR_SURF_P2);
} tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); PIPE_CONFIG(ADDR_SURF_P2) |
} TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
} else if (adev->asic_type == CHIP_OLAND || BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
adev->asic_type == CHIP_HAINAN) { BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
switch (reg_offset) { NUM_BANKS(ADDR_SURF_16_BANK);
case 0: tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P2) |
PIPE_CONFIG(ADDR_SURF_P2) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | NUM_BANKS(ADDR_SURF_16_BANK);
NUM_BANKS(ADDR_SURF_16_BANK)); tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
break; ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 1: PIPE_CONFIG(ADDR_SURF_P2) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | NUM_BANKS(ADDR_SURF_16_BANK);
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_16_BANK)); PIPE_CONFIG(ADDR_SURF_P2);
break; tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
case 2: ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P2) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
PIPE_CONFIG(ADDR_SURF_P2) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | NUM_BANKS(ADDR_SURF_16_BANK);
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
NUM_BANKS(ADDR_SURF_16_BANK)); ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; PIPE_CONFIG(ADDR_SURF_P2) |
case 3: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
PIPE_CONFIG(ADDR_SURF_P2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | NUM_BANKS(ADDR_SURF_16_BANK);
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_8_BANK) | PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(split_equal_to_row_size)); TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
break; BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 4: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
ARRAY_MODE(ARRAY_1D_TILED_THIN1) | NUM_BANKS(ADDR_SURF_16_BANK);
PIPE_CONFIG(ADDR_SURF_P2)); tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
break; ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 5: PIPE_CONFIG(ADDR_SURF_P2) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
PIPE_CONFIG(ADDR_SURF_P2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | TILE_SPLIT(split_equal_to_row_size);
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | ARRAY_MODE(ARRAY_1D_TILED_THICK) |
NUM_BANKS(ADDR_SURF_8_BANK)); PIPE_CONFIG(ADDR_SURF_P2);
break; tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
case 6: ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P2) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | TILE_SPLIT(split_equal_to_row_size);
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
NUM_BANKS(ADDR_SURF_8_BANK)); ARRAY_MODE(ARRAY_2D_TILED_THICK) |
break; PIPE_CONFIG(ADDR_SURF_P2) |
case 7: BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
PIPE_CONFIG(ADDR_SURF_P2) | NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | TILE_SPLIT(split_equal_to_row_size);
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | PIPE_CONFIG(ADDR_SURF_P2) |
NUM_BANKS(ADDR_SURF_4_BANK)); TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
break; BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
case 8: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
break; NUM_BANKS(ADDR_SURF_8_BANK);
case 9: tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
ARRAY_MODE(ARRAY_1D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P2) |
PIPE_CONFIG(ADDR_SURF_P2)); TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
break; BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
case 10: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | NUM_BANKS(ADDR_SURF_8_BANK);
PIPE_CONFIG(ADDR_SURF_P2) | tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
case 11: NUM_BANKS(ADDR_SURF_8_BANK);
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_8_BANK);
break; tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
case 12: ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P2) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
PIPE_CONFIG(ADDR_SURF_P2) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | NUM_BANKS(ADDR_SURF_4_BANK);
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
NUM_BANKS(ADDR_SURF_16_BANK)); ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; PIPE_CONFIG(ADDR_SURF_P2) |
case 13: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
ARRAY_MODE(ARRAY_1D_TILED_THIN1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
PIPE_CONFIG(ADDR_SURF_P2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
break; NUM_BANKS(ADDR_SURF_4_BANK);
case 14: tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P2) |
PIPE_CONFIG(ADDR_SURF_P2) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | NUM_BANKS(ADDR_SURF_4_BANK);
NUM_BANKS(ADDR_SURF_16_BANK)); tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
break; ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 15: PIPE_CONFIG(ADDR_SURF_P2) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | NUM_BANKS(ADDR_SURF_4_BANK);
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_16_BANK)); PIPE_CONFIG(ADDR_SURF_P2) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
case 16: BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
PIPE_CONFIG(ADDR_SURF_P2) | NUM_BANKS(ADDR_SURF_4_BANK);
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | PIPE_CONFIG(ADDR_SURF_P2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
NUM_BANKS(ADDR_SURF_16_BANK)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
case 17: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | NUM_BANKS(ADDR_SURF_4_BANK);
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
PIPE_CONFIG(ADDR_SURF_P2) | WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(split_equal_to_row_size));
break;
case 18:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_1D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P2));
break;
case 19:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
PIPE_CONFIG(ADDR_SURF_P2) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(split_equal_to_row_size));
break;
case 20:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P2) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK) |
TILE_SPLIT(split_equal_to_row_size));
break;
case 21:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 22:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 23:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 24:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 25:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 26:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 27:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 28:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 29:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 30:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
default:
continue;
}
adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
}
} else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
switch (reg_offset) { ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 0: PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | NUM_BANKS(ADDR_SURF_16_BANK);
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_16_BANK)); PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
case 1: BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | NUM_BANKS(ADDR_SURF_16_BANK);
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_16_BANK)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
case 2: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | NUM_BANKS(ADDR_SURF_16_BANK);
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_4_BANK) |
break; TILE_SPLIT(split_equal_to_row_size);
case 3: tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
NUM_BANKS(ADDR_SURF_4_BANK) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
TILE_SPLIT(split_equal_to_row_size)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
case 4: NUM_BANKS(ADDR_SURF_2_BANK);
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
ARRAY_MODE(ARRAY_1D_TILED_THIN1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
case 5: BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | NUM_BANKS(ADDR_SURF_2_BANK);
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
NUM_BANKS(ADDR_SURF_2_BANK)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
case 6: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | NUM_BANKS(ADDR_SURF_2_BANK);
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
NUM_BANKS(ADDR_SURF_2_BANK)); PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
case 7: BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) | NUM_BANKS(ADDR_SURF_16_BANK);
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
NUM_BANKS(ADDR_SURF_2_BANK)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
case 8: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); NUM_BANKS(ADDR_SURF_16_BANK);
break; tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
case 9: ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
ARRAY_MODE(ARRAY_1D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
case 10: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | NUM_BANKS(ADDR_SURF_16_BANK);
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
NUM_BANKS(ADDR_SURF_16_BANK)); TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
break; BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 11: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | NUM_BANKS(ADDR_SURF_16_BANK);
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
case 12: NUM_BANKS(ADDR_SURF_16_BANK);
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK);
break; tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
case 13: ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
ARRAY_MODE(ARRAY_1D_TILED_THIN1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
case 14: NUM_BANKS(ADDR_SURF_16_BANK) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | TILE_SPLIT(split_equal_to_row_size);
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | ARRAY_MODE(ARRAY_1D_TILED_THICK) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
NUM_BANKS(ADDR_SURF_16_BANK)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
case 15: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | NUM_BANKS(ADDR_SURF_16_BANK) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(split_equal_to_row_size);
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | ARRAY_MODE(ARRAY_2D_TILED_THICK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
break; NUM_BANKS(ADDR_SURF_16_BANK) |
case 16: TILE_SPLIT(split_equal_to_row_size);
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_4_BANK);
break; tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
case 17: ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | NUM_BANKS(ADDR_SURF_4_BANK);
NUM_BANKS(ADDR_SURF_16_BANK) | tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
TILE_SPLIT(split_equal_to_row_size)); ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
case 18: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
ARRAY_MODE(ARRAY_1D_TILED_THICK) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
break; NUM_BANKS(ADDR_SURF_2_BANK);
case 19: tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK) | NUM_BANKS(ADDR_SURF_2_BANK);
TILE_SPLIT(split_equal_to_row_size)); tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
break; ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 20: PIPE_CONFIG(ADDR_SURF_P4_8x16) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
ARRAY_MODE(ARRAY_2D_TILED_THICK) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | NUM_BANKS(ADDR_SURF_2_BANK);
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
NUM_BANKS(ADDR_SURF_16_BANK) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(split_equal_to_row_size)); PIPE_CONFIG(ADDR_SURF_P4_8x16) |
break; TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
case 21: BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | NUM_BANKS(ADDR_SURF_2_BANK);
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
NUM_BANKS(ADDR_SURF_4_BANK)); BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
case 22: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | NUM_BANKS(ADDR_SURF_2_BANK);
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
NUM_BANKS(ADDR_SURF_4_BANK)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
break; NUM_BANKS(ADDR_SURF_2_BANK);
case 23: tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_8x16) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | NUM_BANKS(ADDR_SURF_2_BANK);
NUM_BANKS(ADDR_SURF_2_BANK)); tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
break; ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 24: PIPE_CONFIG(ADDR_SURF_P4_8x16) |
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | NUM_BANKS(ADDR_SURF_2_BANK);
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
NUM_BANKS(ADDR_SURF_2_BANK)); } else {
break;
case 25:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
case 26:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
case 27:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
case 28:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
case 29:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
case 30:
gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_2_BANK));
break;
default:
continue;
}
adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
}
} else{
DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
} }
} }
static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7