[PATCH] Update Cobalt support

This adds back support for the MIPS-based Cobalt Raq 1/2 and Qube 1/2
systems.

arch/mips/cobalt/Makefile

+#
+# Makefile for the Cobalt micro systems family specific parts of the kernel
+#
+
+obj-y	 := irq.o int-handler.o reset.o setup.o via.o promcon.o
+
+EXTRA_AFLAGS := $(CFLAGS)

arch/mips/cobalt/int-handler.S

+/*
+ * Cobalt interrupt handler
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
+ */
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/cobalt/cobalt.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+/*
+ * cobalt_handle_int: Interrupt handler for Cobalt boards
+ */
+		.text
+		.set	noreorder
+		.set	noat
+		.align	5
+		NESTED(cobalt_handle_int, PT_SIZE, sp)
+		SAVE_ALL
+		CLI
+		.set	at
+
+		/*
+		 * Get pending Interrupts
+		 */
+		mfc0    s0,CP0_CAUSE    # get raw irq status
+		mfc0    a0,CP0_STATUS   # get irq mask
+		and     s0,s0,a0        # compute masked irq status
+
+		andi	a0,s0,CAUSEF_IP2	/* Check for Galileo timer */
+		beq	a0,zero,1f
+		 andi	a0,s0,CAUSEF_IP6	/* Check for Via chip */
+
+		/* Galileo interrupt */
+		jal	galileo_irq
+		 move	a0,sp
+		j	ret_from_irq
+		 nop
+
+1:
+		beq	a0,zero,1f		/* Check IP6 */
+		 andi	a0,s0,CAUSEF_IP3
+
+		/* Via interrupt */
+		jal	via_irq
+		 move	a0,sp
+		j	ret_from_irq
+		 nop
+
+1:
+		beq	a0,zero,1f		/* Check IP3 */
+		 andi	a0,s0,CAUSEF_IP4
+
+		/* Ethernet 0 interrupt */
+		li	a0,COBALT_ETH0_IRQ
+		jal     do_IRQ
+		 move	a1,sp
+
+		j	ret_from_irq
+		 nop
+
+1:
+		beq	a0,zero,1f		/* Check IP4 */
+		 andi	a0,s0,CAUSEF_IP5
+
+		/* Ethernet 1 interrupt */
+		li	a0,COBALT_ETH1_IRQ
+		jal     do_IRQ
+		 move	a1,sp
+
+		j	ret_from_irq
+		 nop
+1:
+		beq	a0,zero,1f		/* Check IP5 */
+		 andi	a0,s0,CAUSEF_IP7
+
+		/* Serial interrupt */
+		li	a0,COBALT_SERIAL_IRQ
+		jal     do_IRQ
+		 move	a1,sp
+
+		j	ret_from_irq
+		 nop
+1:
+		beq	a0,zero,1f		/* Check IP7 */
+		  nop
+
+		/* PCI interrupt */
+		li	a0,COBALT_QUBE_SLOT_IRQ
+		jal     do_IRQ
+		 move	a1,sp
+
+1:
+		j	ret_from_irq
+		 nop
+
+		END(cobalt_handle_int)
+

arch/mips/cobalt/irq.c

+/*
+ * IRQ vector handles
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+
+#include <asm/bootinfo.h>
+#include <asm/i8259.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+
+#include <asm/cobalt/cobalt.h>
+
+/* Cobalt Exception handler */
+extern void cobalt_handle_int(void);
+
+/* Via masking routines */
+extern void unmask_irq(unsigned int irqr);
+extern void mask_irq(unsigned int irq);
+
+
+/*
+ * We have two types of interrupts that we handle, ones that come
+ *  in through the CPU interrupt lines, and ones that come in on
+ *  the via chip. The CPU mappings are:
+ *    0,1 - S/W (ignored)
+ *    2   - Galileo chip (timer)
+ *    3   - Tulip 0 + NCR SCSI
+ *    4   - Tulip 1
+ *    5   - 16550 UART
+ *    6   - VIA southbridge PIC
+ *    7   - unused
+ *
+ * The VIA chip is a master/slave 8259 setup and has the
+ *  following interrupts
+ *    8   - RTC
+ *    9   - PCI
+ *    14  - IDE0
+ *    15  - IDE1
+ *
+ * In the table we use a 1 to indicate that we use a VIA interrupt
+ *  line, and IE_IRQx to indicate that we use a CPU interrupt line
+ *
+ * We map all of these onto linux IRQ #s 0-15 and forget the rest
+ */
+#define NOINT_LINE	0
+#define CPUINT_LINE(x)	IE_IRQ##x
+#define VIAINT_LINE	1
+
+#define COBALT_IRQS	16
+
+static unsigned short irqnr_to_type[COBALT_IRQS] =
+{ CPUINT_LINE(0),  NOINT_LINE,      VIAINT_LINE,  NOINT_LINE,
+  CPUINT_LINE(1),  NOINT_LINE,      NOINT_LINE,   CPUINT_LINE(3),
+  VIAINT_LINE,     VIAINT_LINE,     NOINT_LINE,   NOINT_LINE,
+  NOINT_LINE,      CPUINT_LINE(2),  VIAINT_LINE,  VIAINT_LINE };
+
+/*
+ * Cobalt CPU irq
+ */
+
+static void enable_cpu_irq(unsigned int irq)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	change_c0_status(irqnr_to_type[irq], irqnr_to_type[irq]);
+	local_irq_restore(flags);
+}
+
+static unsigned startup_cpu_irq(unsigned int irq)
+{
+	enable_cpu_irq(irq);
+
+	return 0;
+}
+
+static void disable_cpu_irq(unsigned int irq)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	change_c0_status(irqnr_to_type[irq], ~(irqnr_to_type[irq]));
+	local_irq_restore(flags);
+}
+
+#define shutdown_cpu_irq	disable_cpu_irq
+#define mask_and_ack_cpu_irq	disable_cpu_irq
+
+static void end_cpu_irq(unsigned int irq)
+{
+	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+		enable_cpu_irq(irq);
+}
+
+static struct hw_interrupt_type cobalt_cpu_irq_type = {
+	"Cobalt CPU",
+	startup_cpu_irq,
+	shutdown_cpu_irq,
+	enable_cpu_irq,
+	disable_cpu_irq,
+	mask_and_ack_cpu_irq,
+	end_cpu_irq,
+	NULL
+};
+
+void __init init_IRQ(void)
+{
+	int i;
+
+	/* Initialise all of the IRQ descriptors */
+	init_i8259_irqs();
+
+	/* Map the irqnr to the type int we have */
+	for (i=0; i < COBALT_IRQS; i++) {
+		if (irqnr_to_type[i] >= CPUINT_LINE(0))
+			/* cobalt_cpu_irq_type */
+			irq_desc[i].handler = &cobalt_cpu_irq_type;
+	}
+
+	/* Mask all cpu interrupts
+	    (except IE4, we already masked those at VIA level) */
+	clear_c0_status(ST0_IM);
+	set_c0_status(IE_IRQ4);
+
+	cli();
+
+	set_except_vector(0, cobalt_handle_int);
+}

arch/mips/cobalt/promcon.c

+/*
+ * PROM console for Cobalt Raq2
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/serial_reg.h>
+
+#include <asm/delay.h>
+#include <asm/serial.h>
+#include <asm/io.h>
+
+static unsigned long port = 0xc800000;
+
+static __inline__ void ns16550_cons_put_char(char ch, unsigned long ioaddr)
+{
+	char lsr;
+
+	do {
+		lsr = inb(ioaddr + UART_LSR);
+	} while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
+	outb(ch, ioaddr + UART_TX);
+}
+
+static __inline__ char ns16550_cons_get_char(unsigned long ioaddr)
+{
+	while ((inb(ioaddr + UART_LSR) & UART_LSR_DR) == 0)
+		udelay(1);
+	return inb(ioaddr + UART_RX);
+}
+
+void ns16550_console_write(struct console *co, const char *s, unsigned count)
+{
+	char lsr, ier;
+	unsigned i;
+
+	ier = inb(port + UART_IER);
+	outb(0x00, port + UART_IER);
+	for (i=0; i < count; i++, s++) {
+
+		if(*s == '\n')
+			ns16550_cons_put_char('\r', port);
+		ns16550_cons_put_char(*s, port);
+	}
+
+	do {
+		lsr = inb(port + UART_LSR);
+   	} while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE));
+
+	outb(ier, port + UART_IER);
+}
+
+char getDebugChar(void)
+{
+	return ns16550_cons_get_char(port);
+}
+
+void putDebugChar(char kgdb_char)
+{
+	ns16550_cons_put_char(kgdb_char, port);
+}
+
+static kdev_t
+ns16550_console_dev(struct console *c)
+{
+	return mk_kdev(TTY_MAJOR, 64 + c->index);
+}
+
+static struct console ns16550_console = {
+    .name	= "prom",
+    .setup	= NULL,
+    .write	= ns16550_console_write,
+    .device	= ns16550_console_dev,
+    .flags	= CON_PRINTBUFFER,
+    .index	= -1,
+};
+
+void __init ns16550_setup_console(void)
+{
+	register_console(&ns16550_console);
+}

arch/mips/cobalt/reset.c

+/*
+ * Cobalt Reset operations
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+#include <asm/mipsregs.h>
+
+void cobalt_machine_restart(char *command)
+{
+	*(volatile char *)0xbc000000 = 0x0f;
+
+	/*
+	 * Ouch, we're still alive ... This time we take the silver bullet ...
+	 * ... and find that we leave the hardware in a state in which the
+	 * kernel in the flush locks up somewhen during of after the PCI
+	 * detection stuff.
+	 */
+	set_c0_status(ST0_BEV | ST0_ERL);
+	change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+	flush_cache_all();
+	write_c0_wired(0);
+	__asm__ __volatile__(
+		"jr\t%0"
+		:
+		: "r" (0xbfc00000));
+}
+
+extern int led_state;
+#define kLED            0xBC000000
+#define LEDSet(x)       (*(volatile unsigned char *) kLED) = (( unsigned char)x)
+
+void cobalt_machine_halt(void)
+{
+	int mark;
+
+	/* Blink our cute? little LED (number 3)... */
+	while (1) {
+		led_state = led_state | ( 1 << 3 );
+		LEDSet(led_state);
+		mark = jiffies;
+		while (jiffies<(mark+HZ));
+		led_state = led_state & ~( 1 << 3 );
+		LEDSet(led_state);
+		mark = jiffies;
+		while (jiffies<(mark+HZ));
+	}
+}
+
+/*
+ * This triggers the luser mode device driver for the power switch ;-)
+ */
+void cobalt_machine_power_off(void)
+{
+	printk("You can switch the machine off now.\n");
+	cobalt_machine_halt();
+}

arch/mips/cobalt/setup.c

+/*
+ * Setup pointers to hardware dependent routines.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/mc146818rtc.h>
+#include <linux/init.h>
+#include <linux/ide.h>
+
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/gt64120.h>
+
+#include <asm/cobalt/cobalt.h>
+
+extern void cobalt_machine_restart(char *command);
+extern void cobalt_machine_halt(void);
+extern void cobalt_machine_power_off(void);
+
+extern struct rtc_ops std_rtc_ops;
+extern struct ide_ops std_ide_ops;
+
+
+char arcs_cmdline[CL_SIZE] = {
+ "console=ttyS0,115200 "
+#ifdef CONFIG_IP_PNP
+ "ip=on "
+#endif
+#ifdef CONFIG_ROOT_NFS
+ "root=/dev/nfs "
+#else
+ "root=/dev/hda1 "
+#endif
+ };
+
+const char *get_system_type(void)
+{
+	return "MIPS Cobalt";
+}
+
+
+static void __init cobalt_time_init(void)
+{
+	rtc_ops = &std_rtc_ops;
+}
+
+static void __init cobalt_timer_setup(struct irqaction *irq)
+{
+	/* Load timer value for 150 Hz */
+	GALILEO_OUTL(500000, GT_TC0_OFS);
+
+	/* Register our timer interrupt */
+	setup_irq(COBALT_TIMER_IRQ, irq);
+
+	/* Enable timer ints */
+	GALILEO_OUTL((GALILEO_ENTC0 | GALILEO_SELTC0), GT_TC_CONTROL_OFS);
+	/* Unmask timer int */
+	GALILEO_OUTL(0x100, GT_INTRMASK_OFS);
+}
+
+
+void __init cobalt_setup(void)
+{
+
+	_machine_restart = cobalt_machine_restart;
+	_machine_halt = cobalt_machine_halt;
+	_machine_power_off = cobalt_machine_power_off;
+
+	board_time_init = cobalt_time_init;
+	board_timer_setup = cobalt_timer_setup;
+
+#ifdef CONFIG_BLK_DEV_IDE
+	ide_ops = &std_ide_ops;
+#endif
+
+        set_io_port_base(KSEG1ADDR(0x10000000));
+
+	/*
+	 * This is a prom style console. We just poke at the
+	 *  UART to make it talk.
+	 * Only use this console if you really screw up and can't
+	 *  get to the stage of setting up a real serial console.
+	 */
+	/*ns16550_setup_console();*/
+}
+
+/* Prom init. We read our one and only communication with the
+    firmware. Grab the amount of installed memory */
+void __init prom_init(int argc)
+{
+	mips_machgroup = MACH_GROUP_COBALT;
+
+	add_memory_region(0x0, argc & 0x7fffffff, BOOT_MEM_RAM);
+}
+
+void __init prom_free_prom_memory(void)
+{
+	/* Nothing to do! */
+}

arch/mips/cobalt/via.c

+/*
+ * VIA chipset irq handling
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997 by Ralf Baechle
+ * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
+ *
+ */
+
+#include <linux/irq.h>
+#include <linux/kernel.h>
+
+#include <asm/gt64120.h>
+#include <asm/ptrace.h>
+#include <asm/io.h>
+
+#include <asm/cobalt/cobalt.h>
+
+asmlinkage void via_irq(struct pt_regs *regs)
+{
+	char mstat, sstat;
+
+	/* Read Master Status */
+	outb(0x0C, 0x20);
+	mstat = inb(0x20);
+
+	if (mstat < 0) {
+		mstat &= 0x7f;
+		if (mstat != 2) {
+			do_IRQ(mstat, regs);
+			outb(mstat | 0x20, 0x20);
+		} else {
+			sstat = inb(0xA0);
+
+			/* Slave interrupt */
+			outb(0x0C, 0xA0);
+			sstat = inb(0xA0);
+
+			if (sstat < 0) {
+				do_IRQ((sstat + 8) & 0x7f, regs);
+				outb(0x22, 0x20);
+				outb((sstat & 0x7f) | 0x20, 0xA0);
+			} else {
+				printk("Spurious slave interrupt...\n");
+			}
+		}
+	} else
+		printk("Spurious master interrupt...");
+}
+
+asmlinkage void galileo_irq(struct pt_regs *regs)
+{
+	unsigned long irq_src;
+
+	irq_src = GALILEO_INL(GT_INTRCAUSE_OFS);
+
+	/* Check for timer irq ... */
+	if (irq_src & GALILEO_T0EXP) {
+		/* Clear the int line */
+		GALILEO_OUTL(0, GT_INTRCAUSE_OFS);
+		do_IRQ(COBALT_TIMER_IRQ, regs);
+	} else
+		printk("Spurious Galileo interrupt...\n");
+}

arch/mips/defconfig-cobalt

+#
+# Automatically generated make config: don't edit
+#
+CONFIG_MIPS=y
+CONFIG_MIPS32=y
+# CONFIG_MIPS64 is not set
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# General setup
+#
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_EMBEDDED is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# Machine selection
+#
+# CONFIG_ACER_PICA_61 is not set
+# CONFIG_BAGET_MIPS is not set
+# CONFIG_CASIO_E55 is not set
+CONFIG_MIPS_COBALT=y
+# CONFIG_DECSTATION is not set
+# CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
+# CONFIG_MIPS_IVR is not set
+# CONFIG_LASAT is not set
+# CONFIG_HP_LASERJET is not set
+# CONFIG_IBM_WORKPAD is not set
+# CONFIG_MIPS_ITE8172 is not set
+# CONFIG_MIPS_ATLAS is not set
+# CONFIG_MIPS_MAGNUM_4000 is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SEAD is not set
+# CONFIG_MOMENCO_OCELOT is not set
+# CONFIG_MOMENCO_OCELOT_G is not set
+# CONFIG_MOMENCO_OCELOT_C is not set
+# CONFIG_DDB5074 is not set
+# CONFIG_DDB5476 is not set
+# CONFIG_DDB5477 is not set
+# CONFIG_NEC_OSPREY is not set
+# CONFIG_NEC_EAGLE is not set
+# CONFIG_OLIVETTI_M700 is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SOC_AU1X00 is not set
+# CONFIG_SIBYTE_SB1xxx_SOC is not set
+# CONFIG_SNI_RM200_PCI is not set
+# CONFIG_TANBAC_TB0226 is not set
+# CONFIG_TANBAC_TB0229 is not set
+# CONFIG_TOSHIBA_JMR3927 is not set
+# CONFIG_TOSHIBA_RBTX4927 is not set
+# CONFIG_VICTOR_MPC30X is not set
+# CONFIG_ZAO_CAPCELLA is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_I8259=y
+CONFIG_NONCOHERENT_IO=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_COBALT_LCD=y
+# CONFIG_FB is not set
+
+#
+# CPU selection
+#
+# CONFIG_CPU_MIPS32 is not set
+# CONFIG_CPU_MIPS64 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R6000 is not set
+CONFIG_CPU_NEVADA=y
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_ADVANCED is not set
+CONFIG_CPU_HAS_LLSC=y
+CONFIG_CPU_HAS_LLDSCD=y
+CONFIG_CPU_HAS_SYNC=y
+# CONFIG_PREEMPT is not set
+CONFIG_KALLSYMS=y
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_PCI=y
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_PCI_NAMES=y
+CONFIG_MMU=y
+# CONFIG_HOTPLUG is not set
+
+#
+# Executable file formats
+#
+CONFIG_KCORE_ELF=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+# CONFIG_PNP is not set
+
+#
+# Generic Driver Options
+#
+# CONFIG_FW_LOADER is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_IDEDISK_STROKE is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_TASKFILE_IO=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_IDEPCI is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK_DEV=y
+# CONFIG_NETFILTER is not set
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_XFRM_USER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+CONFIG_IPV6_SCTP__=y
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_LLC is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_PCI is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices (depends on LLC=y)
+#
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# IrDA (infrared) support
+#
+# CONFIG_IRDA is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN_BOOL is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+# CONFIG_SERIO_PCIPS2 is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=16
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# I2C Hardware Sensors Mainboard support
+#
+
+#
+# I2C Hardware Sensors Chip support
+#
+# CONFIG_I2C_SENSOR is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_QIC02_TAPE is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+CONFIG_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+CONFIG_HANGCHECK_TIMER=y
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_FAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_DEVPTS_FS=y
+CONFIG_DEVPTS_FS_XATTR=y
+CONFIG_DEVPTS_FS_SECURITY=y
+# CONFIG_TMPFS is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+# CONFIG_EXPORTFS is not set
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_GSS is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Graphics support
+#
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BT is not set
+
+#
+# Kernel hacking
+#
+CONFIG_CROSSCOMPILE=y
+# CONFIG_DEBUG_KERNEL is not set
+
+#
+# Security options
+#
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC32 is not set

drivers/char/lcd.c

+/*
+ * LCD, LED and Button interface for Cobalt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997 by Andrew Bose
+ *
+ * Linux kernel version history:
+ *       March 2001: Ported from 2.0.34  by Liam Davies
+ *
+ */
+
+#define RTC_IO_EXTENT	0x10    /*Only really two ports, but...	*/
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/miscdevice.h>
+#include <linux/slab.h>
+#include <linux/ioport.h>
+#include <linux/fcntl.h>
+#include <linux/mc146818rtc.h>
+#include <linux/netdevice.h>
+#include <linux/sched.h>
+
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <linux/delay.h>
+
+#include "lcd.h"
+
+static int lcd_ioctl(struct inode *inode, struct file *file, unsigned int cmd, 
+                     unsigned long arg);
+
+static int lcd_present = 1;
+
+int led_state = 0;
+
+#if defined(CONFIG_TULIP) && 0
+
+#define MAX_INTERFACES	8
+static linkcheck_func_t linkcheck_callbacks[MAX_INTERFACES];
+static void *linkcheck_cookies[MAX_INTERFACES];
+
+int lcd_register_linkcheck_func(int iface_num, void *func, void *cookie)
+{
+	if (iface_num < 0 ||
+	    iface_num >= MAX_INTERFACES ||
+	    linkcheck_callbacks[iface_num] != NULL)
+		return -1;
+	linkcheck_callbacks[iface_num] = (linkcheck_func_t) func;
+	linkcheck_cookies[iface_num] = cookie;
+	return 0;
+}
+#endif
+
+static int lcd_ioctl(struct inode *inode, struct file *file, unsigned int cmd, 
+			unsigned long arg)
+{
+	struct lcd_display button_display;
+	unsigned long address, a;
+	int index;
+
+	switch (cmd) {
+	case LCD_On:
+		udelay(150);
+		BusyCheck();
+		LCDWriteInst(0x0F);
+		break;		
+
+	case LCD_Off:
+		udelay(150);
+		BusyCheck();
+		LCDWriteInst(0x08);
+		break;
+
+	case LCD_Reset:
+		udelay(150);
+		LCDWriteInst(0x3F);
+		udelay(150);
+		LCDWriteInst(0x3F);
+		udelay(150);
+		LCDWriteInst(0x3F);
+		udelay(150);
+		LCDWriteInst(0x3F);
+		udelay(150);
+		LCDWriteInst(0x01);
+		udelay(150);
+		LCDWriteInst(0x06);
+		break;
+
+	case LCD_Clear:
+		udelay(150);
+		BusyCheck();
+       		LCDWriteInst(0x01);     
+		break;
+
+	case LCD_Cursor_Left:
+		udelay(150);
+		BusyCheck();
+		LCDWriteInst(0x10);
+		break;
+
+	case LCD_Cursor_Right:
+		udelay(150);
+		BusyCheck();
+		LCDWriteInst(0x14);
+		break;	
+
+	case LCD_Cursor_Off:
+		udelay(150);
+                BusyCheck();
+                LCDWriteInst(0x0C);
+	        break;
+
+        case LCD_Cursor_On:
+                udelay(150);
+                BusyCheck();
+                LCDWriteInst(0x0F);
+                break;
+
+        case LCD_Blink_Off:
+                udelay(150);
+                BusyCheck();
+                LCDWriteInst(0x0E);
+                break;
+
+	case LCD_Get_Cursor_Pos:{
+                struct lcd_display display;
+
+		udelay(150);
+                BusyCheck();
+		display.cursor_address = ( LCDReadInst ); 
+		display.cursor_address = ( display.cursor_address & 0x07F );
+		if(copy_to_user((struct lcd_display*)arg, &display, sizeof(struct lcd_display)))
+		  return -EFAULT;
+
+		break;
+		}
+
+
+	case LCD_Set_Cursor_Pos: {
+                struct lcd_display display;
+
+                if(copy_from_user(&display, (struct lcd_display*)arg, sizeof(struct lcd_display)))
+		  return -EFAULT;
+
+		a = (display.cursor_address | kLCD_Addr ); 
+
+                udelay(150);
+                BusyCheck();    
+                LCDWriteInst( a );
+
+                break;
+		}
+	
+	case LCD_Get_Cursor: {
+                struct lcd_display display;
+
+                udelay(150);
+                BusyCheck();    
+		display.character = LCDReadData;	
+
+		if(copy_to_user((struct lcd_display*)arg, &display, sizeof(struct lcd_display)))
+		  return -EFAULT;
+                udelay(150);
+                BusyCheck();
+                LCDWriteInst(0x10);
+
+		break;
+		}
+
+	case LCD_Set_Cursor:{
+                struct lcd_display display;
+   
+                if(copy_from_user(&display, (struct lcd_display*)arg, sizeof(struct lcd_display)))
+		  return -EFAULT;
+
+                udelay(150);
+		BusyCheck();    
+                LCDWriteData( display.character );
+                udelay(150);
+                BusyCheck();
+                LCDWriteInst(0x10);
+
+                break;
+                }
+
+
+	case LCD_Disp_Left:
+		udelay(150);
+		BusyCheck();
+		LCDWriteInst(0x18);
+		break;
+
+	case LCD_Disp_Right:
+		udelay(150);
+		BusyCheck();
+		LCDWriteInst(0x1C);
+		break;
+
+	case LCD_Home:
+		udelay(150);
+		BusyCheck();
+		LCDWriteInst(0x02);
+		break;
+
+	case LCD_Write: {
+		struct lcd_display display;
+   
+
+                if(copy_from_user(&display, (struct lcd_display*)arg, sizeof(struct lcd_display)))
+		  return -EFAULT;
+ 
+		udelay(150);
+                BusyCheck();    
+                LCDWriteInst(0x80);
+		udelay(150);
+		BusyCheck();
+	
+		for (index = 0; index < (display.size1); index++) {
+			udelay(150);
+			BusyCheck();	
+			LCDWriteData( display.line1[index]);
+			BusyCheck();	
+		}		
+		
+		udelay(150);
+		BusyCheck();	
+		LCDWriteInst(0xC0);	
+		udelay(150);
+		BusyCheck();	
+                for (index = 0; index < (display.size2); index++) {
+                        udelay(150);
+                        BusyCheck();    
+                        LCDWriteData( display.line2[index]);
+		}
+ 
+		break;	
+	}
+	
+	case LCD_Read: {	
+        	struct lcd_display display;
+
+		BusyCheck();
+		for (address = kDD_R00; address <= kDD_R01; address++) {
+			a = (address | kLCD_Addr );	
+
+			udelay(150);
+			BusyCheck();
+			LCDWriteInst( a );
+			udelay(150);
+			BusyCheck();
+			display.line1[address] = LCDReadData;
+		}
+
+		display.line1[ 0x27 ] = '\0';
+	
+		for (address = kDD_R10; address <= kDD_R11; address++) {
+			a = (address | kLCD_Addr );     
+        
+			udelay(150);
+	 		BusyCheck();
+        		LCDWriteInst( a );
+       
+        		udelay(150);
+	 		BusyCheck();
+        		display.line2[address - 0x40 ] = LCDReadData;
+		 }
+
+		display.line2[ 0x27 ] = '\0';
+
+		if(copy_to_user((struct lcd_display*)arg, &display,
+				sizeof(struct lcd_display)))
+		  return -EFAULT;
+		break;
+	}
+
+//  set all GPIO leds to led_display.leds 
+
+	case LED_Set: {	
+		struct lcd_display led_display;
+	
+
+	        if(copy_from_user(&led_display, (struct lcd_display*)arg,
+				  sizeof(struct lcd_display)))
+		  return -EFAULT;
+
+		led_state = led_display.leds;
+		LEDSet(led_state);
+
+        	break;
+	}
+
+
+//  set only bit led_display.leds
+
+        case LED_Bit_Set: {
+                int i;
+		int bit=1;
+                struct lcd_display led_display;
+
+
+                if(copy_from_user(&led_display, (struct lcd_display*)arg,
+				  sizeof(struct lcd_display)))
+		  return -EFAULT;
+
+		for (i=0;i<(int)led_display.leds;i++)
+			{
+				bit = 2*bit;	
+			}
+
+		led_state = led_state | bit;
+                LEDSet(led_state);
+                break;
+        }
+
+//  clear only bit led_display.leds
+
+        case LED_Bit_Clear: {
+                int i;
+		int bit=1;
+                struct lcd_display led_display;
+
+
+                if(copy_from_user(&led_display, (struct lcd_display*)arg,
+				  sizeof(struct lcd_display)))
+		  return -EFAULT;
+
+                for (i=0;i<(int)led_display.leds;i++)
+                        {
+                                bit = 2*bit;
+                        }
+
+		led_state = led_state &  ~bit;
+                LEDSet(led_state);
+                break;
+        }
+
+
+	case BUTTON_Read: {
+		button_display.buttons = GPIRead;
+                if(copy_to_user((struct lcd_display*)arg, &button_display, sizeof(struct lcd_display)))
+		  return -EFAULT;
+		break;
+	}
+
+        case LINK_Check: {
+                button_display.buttons = *((volatile unsigned long *) (0xB0100060) );
+                if(copy_to_user((struct lcd_display*)arg, &button_display, sizeof(struct lcd_display)))
+		  return -EFAULT;
+                break;
+        }
+
+	case LINK_Check_2: {
+		int iface_num;
+
+		/* panel-utils should pass in the desired interface status is wanted for
+		 * in "buttons" of the structure.  We will set this to non-zero if the
+		 * link is in fact up for the requested interface.  --DaveM
+		 */
+		if(copy_from_user(&button_display, (struct lcd_display *)arg, sizeof(button_display)))
+		  return -EFAULT;
+		iface_num = button_display.buttons;
+#if defined(CONFIG_TULIP) && 0
+		if (iface_num >= 0 &&
+		    iface_num < MAX_INTERFACES &&
+		    linkcheck_callbacks[iface_num] != NULL) {
+			button_display.buttons =
+				linkcheck_callbacks[iface_num](linkcheck_cookies[iface_num]);
+		} else
+#endif
+			button_display.buttons = 0;
+
+                if(__copy_to_user((struct lcd_display*)arg, &button_display, sizeof(struct lcd_display)))
+		  return -EFAULT;
+                break;
+	}
+
+//  Erase the flash
+
+	case FLASH_Erase: {
+
+		int ctr=0;
+
+		    // Chip Erase Sequence
+		WRITE_FLASH( kFlash_Addr1, kFlash_Data1 );
+		WRITE_FLASH( kFlash_Addr2, kFlash_Data2 );
+		WRITE_FLASH( kFlash_Addr1, kFlash_Erase3 );
+		WRITE_FLASH( kFlash_Addr1, kFlash_Data1 );
+		WRITE_FLASH( kFlash_Addr2, kFlash_Data2 );
+		WRITE_FLASH( kFlash_Addr1, kFlash_Erase6 );
+
+		printk( "Erasing Flash.\n");
+
+		while ( (!dqpoll(0x00000000,0xFF)) && (!timeout(0x00000000)) ) {
+		    ctr++;
+		}
+
+		printk("\n");
+		printk("\n");
+		printk("\n");
+
+		if (READ_FLASH(0x07FFF0)==0xFF) { printk("Erase Successful\r\n"); }
+		else if (timeout) { printk("Erase Timed Out\r\n"); }
+
+	break;
+	}
+
+// burn the flash 
+
+	case FLASH_Burn: {
+
+		volatile unsigned long burn_addr;
+		unsigned long flags;
+		int i;
+		unsigned char *rom;
+		
+
+                struct lcd_display display;
+
+                if(copy_from_user(&display, (struct lcd_display*)arg, sizeof(struct lcd_display)))
+		  return -EFAULT;
+		rom = (unsigned char *) kmalloc((128),GFP_ATOMIC);
+                if ( rom == NULL ) {
+                       printk ("broken\n");
+                       return 1;
+                   }
+
+		printk("Churning and Burning -");
+		save_flags(flags);
+		for (i=0; i<FLASH_SIZE; i=i+128) {
+
+		        if(copy_from_user(rom, display.RomImage + i, 128))
+			   return -EFAULT;
+			burn_addr = kFlashBase + i;
+			cli();
+			for ( index = 0; index < ( 128 ) ; index++ ) 
+		  	  {
+
+				WRITE_FLASH( kFlash_Addr1, kFlash_Data1 );
+		 	    	WRITE_FLASH( kFlash_Addr2, kFlash_Data2 );
+		 	    	WRITE_FLASH( kFlash_Addr1, kFlash_Prog );
+		 	    	*((volatile unsigned char *)burn_addr) = (volatile unsigned char) rom[index];
+
+		   	 	 while ( (!dqpoll(burn_addr,(volatile unsigned char) rom[index])) && (!timeout(burn_addr)) ) {
+		  	   		}
+		  	   	burn_addr++;
+		  	  }
+			restore_flags(flags);
+                	if ( *((volatile unsigned char *)(burn_addr-1)) == (volatile unsigned char) rom[index-1]  ) {
+               		 } else if (timeout) {
+                	    printk("Program timed out\r\n");
+               		 }
+
+
+		}
+		kfree(rom);
+
+	break;
+	}
+
+//  read the flash all at once 
+	
+	case FLASH_Read: {
+
+		unsigned char *user_bytes;
+                volatile unsigned long read_addr;
+                int i;
+
+		user_bytes = &(((struct lcd_display *)arg)->RomImage[0]);
+
+		if(!access_ok(VERIFY_WRITE, user_bytes, FLASH_SIZE))
+                         return -EFAULT;
+
+		printk("Reading Flash");
+		for (i=0; i<FLASH_SIZE; i++) {
+			unsigned char tmp_byte;
+			read_addr = kFlashBase + i;
+			tmp_byte = *((volatile unsigned char *)read_addr);
+			if(__put_user (tmp_byte, &user_bytes[i]))
+			  return -EFAULT;
+		}
+
+
+	break;
+	}
+
+
+
+
+
+	default:
+		return 0;
+	break;
+
+	}
+
+	return 0;
+
+}
+
+static int lcd_open(struct inode *inode, struct file *file)
+{
+	if (!lcd_present)
+		return -ENXIO;
+	else
+		return 0;
+}
+
+/* Only RESET or NEXT counts as button pressed */
+
+static inline int button_pressed(void)
+{
+	unsigned long buttons = GPIRead;
+
+	if ( (buttons == BUTTON_Next) || (buttons == BUTTON_Next_B) || (buttons == BUTTON_Reset_B) )
+		return buttons;
+	return 0;
+}
+
+/* LED daemon sits on this and we wake him up once a key is pressed. */
+
+static int lcd_waiters = 0;
+
+static long lcd_read(struct inode *inode, struct file *file, char *buf, unsigned long count)
+{
+	long buttons_now;
+
+	if(lcd_waiters > 0)
+		return -EINVAL;
+
+	lcd_waiters++;
+	while(((buttons_now = (long)button_pressed()) == 0) &&
+	      !(signal_pending(current))) {
+		current->state = TASK_INTERRUPTIBLE;
+		schedule_timeout(2 * HZ);
+	}
+	lcd_waiters--;
+
+	if(signal_pending(current))
+		return -ERESTARTSYS;
+	return buttons_now;
+}
+
+/*
+ *	The various file operations we support.
+ */
+
+static struct file_operations lcd_fops = {
+	read:		lcd_read,
+	ioctl:		lcd_ioctl,
+	open:		lcd_open,
+};
+
+static struct miscdevice lcd_dev=
+{
+	LCD_MINOR,
+	"lcd",
+	&lcd_fops
+};
+
+int lcd_init(void)
+{
+unsigned long data;
+
+	printk("%s\n", LCD_DRIVER);
+	misc_register(&lcd_dev);
+
+	/* Check region? Naaah! Just snarf it up. */
+/*	request_region(RTC_PORT(0), RTC_IO_EXTENT, "lcd");*/
+
+	udelay(150);
+	data = LCDReadData;
+	if ( (data & 0x000000FF) == (0x00) ) {
+		lcd_present = 0;
+		printk("LCD Not Present\n");
+	        }
+	else {
+		lcd_present = 1;
+		WRITE_GAL( kGal_DevBank2PReg, kGal_DevBank2Cfg );
+		WRITE_GAL( kGal_DevBank3PReg, kGal_DevBank3Cfg );
+		}
+
+	return 0;
+}
+
+
+//
+// Function: dqpoll
+//
+// Description:  Polls the data lines to see if the flash is busy
+//
+// In: address, byte data
+//
+// Out: 0 = busy, 1 = write or erase complete
+//
+//
+
+int dqpoll( volatile unsigned long address, volatile unsigned char data ) {
+
+volatile unsigned char dq7;
+
+dq7 = data & 0x80;
+
+return ( (READ_FLASH(address) & 0x80) == dq7  );
+
+}
+
+
+//
+// Function: timeout
+//
+// Description: Checks to see if erase or write has timed out
+//              By polling dq5
+//
+// In: address
+//
+//
+// Out: 0 = not timed out, 1 = timed out
+
+int timeout( volatile unsigned long address ) {
+
+
+return (  (READ_FLASH(address) & 0x20) ==  0x20 );
+
+}
+
+
+

include/asm-mips/cobalt/cobalt.h

+/*
+ * Lowlevel hardware stuff for the MIPS based Cobalt microservers.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997 Cobalt Microserver
+ * Copyright (C) 1997 Ralf Baechle
+ * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv)
+ *
+ */
+#ifndef __ASM_MIPS_COBALT_H
+#define __ASM_MIPS_COBALT_H
+
+/*
+ * COBALT interrupt enable bits
+ */
+#define COBALT_IE_PCI          (1 << 0)
+#define COBALT_IE_FLOPPY       (1 << 1)
+#define COBALT_IE_KEYBOARD     (1 << 2)
+#define COBALT_IE_SERIAL1      (1 << 3)
+#define COBALT_IE_SERIAL2      (1 << 4)
+#define COBALT_IE_PARALLEL     (1 << 5)
+#define COBALT_IE_GPIO         (1 << 6)
+#define COBALT_IE_RTC          (1 << 7)
+
+/*
+ * PCI defines
+ */
+#define COBALT_IE_ETHERNET     (1 << 7)
+#define COBALT_IE_SCSI         (1 << 7)
+
+/*
+ * COBALT Interrupt Level definitions.
+ * These should match the request IRQ id's.
+ */
+#define COBALT_TIMER_IRQ       0
+#define COBALT_KEYBOARD_IRQ    1
+#define COBALT_QUBE_SLOT_IRQ   9
+#define COBALT_ETH0_IRQ        4
+#define COBALT_ETH1_IRQ        13
+#define COBALT_SCC_IRQ         4
+#define COBALT_SERIAL2_IRQ     4
+#define COBALT_PARALLEL_IRQ    5
+#define COBALT_FLOPPY_IRQ      6 /* needs to be consistent with floppy driver! */
+#define COBALT_SCSI_IRQ        7
+#define COBALT_SERIAL_IRQ      7
+#define COBALT_RAQ_SCSI_IRQ    4
+
+/*
+ * PCI configuration space manifest constants.  These are wired into
+ * the board layout according to the PCI spec to enable the software
+ * to probe the hardware configuration space in a well defined manner.
+ *
+ * The PCI_DEVSHFT() macro transforms these values into numbers
+ * suitable for passing as the dev parameter to the various
+ * pcibios_read/write_config routines.
+ */
+#define COBALT_PCICONF_CPU      0x06
+#define COBALT_PCICONF_ETH0     0x07
+#define COBALT_PCICONF_RAQSCSI  0x08
+#define COBALT_PCICONF_VIA      0x09
+#define COBALT_PCICONF_PCISLOT  0x0A
+#define COBALT_PCICONF_ETH1     0x0C
+
+
+/*
+ * The Cobalt board id information.  The boards have an ID number wired
+ * into the VIA that is available in the high nibble of register 94.
+ * This register is available in the VIA configuration space through the
+ * interface routines qube_pcibios_read/write_config. See cobalt/pci.c
+ */
+#define VIA_COBALT_BRD_ID_REG  0x94
+#define VIA_COBALT_BRD_REG_to_ID(reg)  ((unsigned char) (reg) >> 4)
+#define COBALT_BRD_ID_QUBE1    0x3
+#define COBALT_BRD_ID_RAQ1     0x4
+#define COBALT_BRD_ID_QUBE2    0x5
+#define COBALT_BRD_ID_RAQ2     0x6
+
+
+/*
+ * Galileo chipset access macros for the Cobalt. The base address for
+ * the GT64111 chip is 0x14000000
+ */
+#define GT64111_BASE		0x04000000
+#define GALILEO_REG(ofs)	(GT64111_BASE + (ofs))
+
+#define GALILEO_INL(port)	(inl(GALILEO_REG(port)))
+#define GALILEO_OUTL(val, port)	outl(val, GALILEO_REG(port))
+
+#define GALILEO_T0EXP		0x0100
+#define GALILEO_ENTC0		0x01
+#define GALILEO_SELTC0		0x02
+
+
+#endif /* __ASM_MIPS_COBALT_H */
+