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Commit 17ec8d17 authored by Linus Torvalds's avatar Linus Torvalds
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Merge bk://bk.arm.linux.org.uk:14691/linux-2.5-pci/ 

into home.transmeta.com:/home/torvalds/v2.5/linux
parents a2cf79d1 18e35894
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Showing with 258 additions and 718 deletions
arch/alpha/kernel/pci.c
View file @ 17ec8d17
......@@ -12,7 +12,7 @@
* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
* PCI-PCI bridges cleanup
*/
#include <linux/config.h>
#include <linux/string.h>
#include <linux/pci.h>
#include <linux/init.h>
......@@ -264,45 +264,6 @@ pcibios_fixup_bus(struct pci_bus *bus)
}
}
void
pcibios_update_resource(struct pci_dev *dev, struct resource *parent,
struct resource *res, int resource)
{
struct pci_controller *hose = dev->sysdata;
struct resource *root;
int where;
u32 reg;
if (resource < PCI_ROM_RESOURCE)
where = PCI_BASE_ADDRESS_0 + (resource * 4);
else if (resource == PCI_ROM_RESOURCE)
where = dev->rom_base_reg;
else {
return; /* Don't update non-standard resources here. */
}
/* Point root at the hose root. */
if (res->flags & IORESOURCE_IO)
root = hose->io_space;
else if (res->flags & IORESOURCE_MEM)
root = hose->mem_space;
else {
return; /* Don't update non-standard resources here. */
}
reg = (res->start - root->start) | (res->flags & 0xf);
pci_write_config_dword(dev, where, reg);
if ((res->flags & (PCI_BASE_ADDRESS_SPACE
| PCI_BASE_ADDRESS_MEM_TYPE_MASK))
== (PCI_BASE_ADDRESS_SPACE_MEMORY
| PCI_BASE_ADDRESS_MEM_TYPE_64)) {
pci_write_config_dword(dev, where+4, 0);
printk(KERN_WARNING "PCI: dev %s type 64-bit\n", dev->dev.name);
}
/* ??? FIXME -- record old value for shutdown. */
}
void __init
pcibios_update_irq(struct pci_dev *dev, int irq)
{
......@@ -334,21 +295,25 @@ common_swizzle(struct pci_dev *dev, u8 *pinp)
}
void __devinit
pcibios_fixup_pbus_ranges(struct pci_bus * bus,
struct pbus_set_ranges_data * ranges)
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res)
{
struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
unsigned long offset = 0;
ranges->io_start -= hose->io_space->start;
ranges->io_end -= hose->io_space->start;
ranges->mem_start -= hose->mem_space->start;
ranges->mem_end -= hose->mem_space->start;
/* FIXME: On older alphas we could use dense memory space
to access prefetchable resources. */
ranges->prefetch_start -= hose->mem_space->start;
ranges->prefetch_end -= hose->mem_space->start;
if (res->flags & IORESOURCE_IO)
offset = hose->io_space->start;
else if (res->flags & IORESOURCE_MEM)
offset = hose->mem_space->start;
region->start = res->start - offset;
region->end = res->end - offset;
}
#ifdef CONFIG_HOTPLUG
EXPORT_SYMBOL(pcibios_resource_to_bus);
#endif
int
pcibios_enable_device(struct pci_dev *dev, int mask)
{
......
arch/arm/kernel/bios32.c
View file @ 17ec8d17
......@@ -259,47 +259,6 @@ struct pci_fixup pcibios_fixups[] = {
}, { 0 }
};
void __devinit
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
struct pci_sys_data *sys = dev->sysdata;
u32 val, check;
int reg;
if (debug_pci)
printk("PCI: Assigning %3s %08lx to %s\n",
res->flags & IORESOURCE_IO ? "IO" : "MEM",
res->start, dev->dev.name);
if (resource < 6) {
reg = PCI_BASE_ADDRESS_0 + 4*resource;
} else if (resource == PCI_ROM_RESOURCE) {
reg = dev->rom_base_reg;
} else {
/* Somebody might have asked allocation of a
* non-standard resource.
*/
return;
}
val = res->start;
if (res->flags & IORESOURCE_MEM)
val -= sys->mem_offset;
else
val -= sys->io_offset;
val |= res->flags & PCI_REGION_FLAG_MASK;
pci_write_config_dword(dev, reg, val);
pci_read_config_dword(dev, reg, &check);
if ((val ^ check) & ((val & PCI_BASE_ADDRESS_SPACE_IO) ?
PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
printk(KERN_ERR "PCI: Error while updating region "
"%s/%d (%08x != %08x)\n", dev->slot_name,
resource, val, check);
}
}
void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
{
if (debug_pci)
......@@ -439,18 +398,26 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
* Convert from Linux-centric to bus-centric addresses for bridge devices.
*/
void __devinit
pcibios_fixup_pbus_ranges(struct pci_bus *bus, struct pbus_set_ranges_data *ranges)
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res)
{
struct pci_sys_data *root = bus->sysdata;
struct pci_sys_data *root = dev->sysdata;
unsigned long offset = 0;
ranges->io_start -= root->io_offset;
ranges->io_end -= root->io_offset;
ranges->mem_start -= root->mem_offset;
ranges->mem_end -= root->mem_offset;
ranges->prefetch_start -= root->mem_offset;
ranges->prefetch_end -= root->mem_offset;
if (res->flags & IORESOURCE_IO)
offset = root->io_offset;
if (res->flags & IORESOURCE_MEM)
offset = root->mem_offset;
region->start = res->start - offset;
region->end = res->end - offset;
}
#ifdef CONFIG_HOTPLUG
EXPORT_SYMBOL(pcibios_fixup_bus);
EXPORT_SYMBOL(pcibios_resource_to_bus);
#endif
/*
* This is the standard PCI-PCI bridge swizzling algorithm:
*
......
arch/i386/pci/common.c
View file @ 17ec8d17
......@@ -90,11 +90,6 @@ static void __devinit pcibios_fixup_ghosts(struct pci_bus *b)
}
}
void __devinit
pcibios_fixup_pbus_ranges (struct pci_bus *bus, struct pbus_set_ranges_data *ranges)
{
}
/*
* Called after each bus is probed, but before its children
* are examined.
......
arch/i386/pci/i386.c
View file @ 17ec8d17
......@@ -33,34 +33,6 @@
#include "pci.h"
void
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
u32 new, check;
int reg;
new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
if (resource < 6) {
reg = PCI_BASE_ADDRESS_0 + 4*resource;
} else if (resource == PCI_ROM_RESOURCE) {
res->flags |= PCI_ROM_ADDRESS_ENABLE;
new |= PCI_ROM_ADDRESS_ENABLE;
reg = dev->rom_base_reg;
} else {
/* Somebody might have asked allocation of a non-standard resource */
return;
}
pci_write_config_dword(dev, reg, new);
pci_read_config_dword(dev, reg, &check);
if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
printk(KERN_ERR "PCI: Error while updating region "
"%s/%d (%08x != %08x)\n", dev->slot_name, resource,
new, check);
}
}
/*
* We need to avoid collisions with `mirrored' VGA ports
* and other strange ISA hardware, so we always want the
......
arch/ia64/pci/pci.c
View file @ 17ec8d17
......@@ -143,21 +143,7 @@ pcibios_fixup_bus (struct pci_bus *b)
return;
}
void __devinit
pcibios_update_resource (struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
unsigned long where, size;
u32 reg;
where = PCI_BASE_ADDRESS_0 + (resource * 4);
size = res->end - res->start;
pci_read_config_dword(dev, where, &reg);
reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
pci_write_config_dword(dev, where, reg);
/* ??? FIXME -- record old value for shutdown. */
}
#warning pcibios_update_resource() is now a generic implementation - please check
void __devinit
pcibios_update_irq (struct pci_dev *dev, int irq)
......@@ -167,11 +153,6 @@ pcibios_update_irq (struct pci_dev *dev, int irq)
/* ??? FIXME -- record old value for shutdown. */
}
void __devinit
pcibios_fixup_pbus_ranges (struct pci_bus * bus, struct pbus_set_ranges_data * ranges)
{
}
static inline int
pcibios_enable_resources (struct pci_dev *dev, int mask)
{
......
arch/mips/ddb5074/pci.c
View file @ 17ec8d17
......@@ -297,11 +297,6 @@ void __init pcibios_update_irq(struct pci_dev *dev, int irq)
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}
void __devinit pcibios_fixup_pbus_ranges(struct pci_bus *bus,
struct pbus_set_ranges_data *ranges)
{
}
int pcibios_enable_resources(struct pci_dev *dev)
{
u16 cmd, old_cmd;
......@@ -341,37 +336,6 @@ int pcibios_enable_device(struct pci_dev *dev)
return pcibios_enable_resources(dev);
}
void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
u32 new, check;
int reg;
new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
if (resource < 6) {
reg = PCI_BASE_ADDRESS_0 + 4 * resource;
} else if (resource == PCI_ROM_RESOURCE) {
res->flags |= PCI_ROM_ADDRESS_ENABLE;
reg = dev->rom_base_reg;
} else {
/*
* Somebody might have asked allocation of a non-standard
* resource
*/
return;
}
pci_write_config_dword(dev, reg, new);
pci_read_config_dword(dev, reg, &check);
if ((new ^ check) &
((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK :
PCI_BASE_ADDRESS_MEM_MASK)) {
printk(KERN_ERR "PCI: Error while updating region "
"%s/%d (%08x != %08x)\n", dev->slot_name, resource,
new, check);
}
}
void pcibios_align_resource(void *data, struct resource *res,
unsigned long size, unsigned long align)
{
......
arch/mips/ddb5476/pci.c
View file @ 17ec8d17
......@@ -341,8 +341,10 @@ void __init pcibios_update_irq(struct pci_dev *dev, int irq)
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}
void __devinit pcibios_fixup_pbus_ranges(struct pci_bus *bus,
struct pbus_set_ranges_data *ranges)
#if 0 /* original DDB5074 code */
void __devinit
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res)
{
/*
* our caller figure out range by going through the dev structures.
......@@ -350,15 +352,14 @@ void __devinit pcibios_fixup_pbus_ranges(struct pci_bus *bus,
* different view of the addressing space.
*/
#if 0 /* original DDB5074 code */
if (bus->number == 0) {
ranges->io_start -= bus->resource[0]->start;
ranges->io_end -= bus->resource[0]->start;
ranges->mem_start -= bus->resource[1]->start;
ranges->mem_end -= bus->resource[1]->start;
}
#endif
}
#endif
int pcibios_enable_resources(struct pci_dev *dev)
{
......@@ -399,37 +400,6 @@ int pcibios_enable_device(struct pci_dev *dev)
return pcibios_enable_resources(dev);
}
void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
u32 new, check;
int reg;
new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
if (resource < 6) {
reg = PCI_BASE_ADDRESS_0 + 4 * resource;
} else if (resource == PCI_ROM_RESOURCE) {
res->flags |= PCI_ROM_ADDRESS_ENABLE;
reg = dev->rom_base_reg;
} else {
/*
* Somebody might have asked allocation of a non-standard
* resource
*/
return;
}
pci_write_config_dword(dev, reg, new);
pci_read_config_dword(dev, reg, &check);
if ((new ^ check) &
((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK :
PCI_BASE_ADDRESS_MEM_MASK)) {
printk(KERN_ERR "PCI: Error while updating region "
"%s/%d (%08x != %08x)\n", dev->slot_name, resource,
new, check);
}
}
void pcibios_align_resource(void *data, struct resource *res,
unsigned long size, unsigned long align)
{
......
arch/mips/ddb5xxx/common/pci.c
View file @ 17ec8d17
......@@ -170,11 +170,3 @@ pcibios_align_resource(void *data, struct resource *res,
/* this should not be called */
MIPS_ASSERT(1 == 0);
}
void
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
/* this should not be called */
MIPS_ASSERT(1 == 0);
}
arch/mips/gt64120/common/pci.c
View file @ 17ec8d17
......@@ -785,39 +785,6 @@ int pcibios_enable_device(struct pci_dev *dev)
return pcibios_enable_resources(dev);
}
void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
u32 new, check;
int reg;
return;
new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
if (resource < 6) {
reg = PCI_BASE_ADDRESS_0 + 4 * resource;
} else if (resource == PCI_ROM_RESOURCE) {
res->flags |= PCI_ROM_ADDRESS_ENABLE;
reg = dev->rom_base_reg;
} else {
/*
* Somebody might have asked allocation of a non-standard
* resource
*/
return;
}
pci_write_config_dword(dev, reg, new);
pci_read_config_dword(dev, reg, &check);
if ((new ^ check) &
((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK :
PCI_BASE_ADDRESS_MEM_MASK)) {
printk(KERN_ERR "PCI: Error while updating region "
"%s/%d (%08x != %08x)\n", dev->slot_name, resource,
new, check);
}
}
void pcibios_align_resource(void *data, struct resource *res,
unsigned long size, unsigned long align)
{
......
arch/mips/ite-boards/generic/it8172_pci.c
View file @ 17ec8d17
......@@ -196,19 +196,7 @@ pcibios_setup(char *str)
return str;
}
void __init
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
unsigned long where, size;
u32 reg;
where = PCI_BASE_ADDRESS_0 + (resource * 4);
size = res->end - res->start;
pci_read_config_dword(dev, where, &reg);
reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
pci_write_config_dword(dev, where, reg);
}
#warning pcibios_update_resource() is now a generic implementation - please check
void __init pcibios_fixup_bus(struct pci_bus *b)
{
......
arch/mips/kernel/pci.c
View file @ 17ec8d17
......@@ -166,10 +166,3 @@ pcibios_align_resource(void *data, struct resource *res,
{
/* this should not be called */
}
void
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
/* this should not be called */
}
arch/mips/mips-boards/generic/pci.c
View file @ 17ec8d17
......@@ -248,19 +248,7 @@ struct pci_fixup pcibios_fixups[] = {
{ 0 }
};
void __init
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
unsigned long where, size;
u32 reg;
where = PCI_BASE_ADDRESS_0 + (resource * 4);
size = res->end - res->start;
pci_read_config_dword(dev, where, &reg);
reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
pci_write_config_dword(dev, where, reg);
}
#warning pcibios_update_resource() is now a generic implementation - please check
/*
* Called after each bus is probed, but before its children
......
arch/mips/sni/pci.c
View file @ 17ec8d17
......@@ -137,34 +137,6 @@ pcibios_fixup_bus(struct pci_bus *b)
{
}
void
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
u32 new, check;
int reg;
new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
if (resource < 6) {
reg = PCI_BASE_ADDRESS_0 + 4*resource;
} else if (resource == PCI_ROM_RESOURCE) {
res->flags |= PCI_ROM_ADDRESS_ENABLE;
new |= PCI_ROM_ADDRESS_ENABLE;
reg = dev->rom_base_reg;
} else {
/* Somebody might have asked allocation of a non-standard resource */
return;
}
pci_write_config_dword(dev, reg, new);
pci_read_config_dword(dev, reg, &check);
if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
printk(KERN_ERR "PCI: Error while updating region "
"%s/%d (%08x != %08x)\n", dev->slot_name, resource,
new, check);
}
}
void __init pcibios_init(void)
{
struct pci_ops *ops = &sni_pci_ops;
......
arch/mips64/mips-boards/generic/pci.c
View file @ 17ec8d17
......@@ -307,19 +307,7 @@ struct pci_fixup pcibios_fixups[] = {
{ 0 }
};
void __init
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
unsigned long where, size;
u32 reg;
where = PCI_BASE_ADDRESS_0 + (resource * 4);
size = res->end - res->start;
pci_read_config_dword(dev, where, &reg);
reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
pci_write_config_dword(dev, where, reg);
}
#warning pcibios_update_resource() is now a generic implementation - please check
unsigned __init int pcibios_assign_all_busses(void)
{
......
arch/mips64/sgi-ip27/ip27-pci.c
View file @ 17ec8d17
......@@ -214,19 +214,7 @@ pcibios_update_irq(struct pci_dev *dev, int irq)
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}
void __init
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
unsigned long where, size;
u32 reg;
where = PCI_BASE_ADDRESS_0 + (resource * 4);
size = res->end - res->start;
pci_read_config_dword(dev, where, &reg);
reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
pci_write_config_dword(dev, where, reg);
}
#warning pcibios_update_resource() is now a generic implementation - please check
void __init
pcibios_fixup_bus(struct pci_bus *b)
......@@ -234,12 +222,6 @@ pcibios_fixup_bus(struct pci_bus *b)
pci_fixup_irqs(pci_swizzle, pci_map_irq);
}
void __devinit
pcibios_fixup_pbus_ranges(struct pci_bus * bus,
struct pbus_set_ranges_data * ranges)
{
}
int __init
pcibios_enable_device(struct pci_dev *dev)
{
......
arch/mips64/sgi-ip32/ip32-pci.c
View file @ 17ec8d17
......@@ -333,11 +333,6 @@ void __init pcibios_align_resource (void *data, struct resource *res,
{
}
void __init pcibios_update_resource (struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
}
void __init pcibios_update_irq (struct pci_dev *dev, int irq)
{
pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
......@@ -348,12 +343,6 @@ void __init pcibios_fixup_bus (struct pci_bus *b)
pci_fixup_irqs (macepci_swizzle, macepci_map_irq);
}
/* XXX anybody know what this is supposed to do? */
void __devinit pcibios_fixup_pbus_ranges(struct pci_bus * bus,
struct pbus_set_ranges_data * ranges)
{
}
/*
* Handle errors from the bridge. This includes master and target aborts,
* various command and address errors, and the interrupt test. This gets
......
arch/parisc/kernel/pci.c
View file @ 17ec8d17
......@@ -192,74 +192,6 @@ void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
}
/* ------------------------------------
**
** Program one BAR in PCI config space.
**
** ------------------------------------
** PAT PDC systems need this routine. PA legacy PDC does not.
**
** When BAR's are configured by linux, this routine will update
** configuration space with the "normalized" address. "root" indicates
** where the range starts and res is some portion of that range.
**
** VCLASS: For all PA-RISC systems except V-class, root->start would be zero.
**
** PAT PDC can tell us which MMIO ranges are available or already in use.
** I/O port space and such are not memory mapped anyway for PA-Risc.
*/
void __devinit
pcibios_update_resource(
struct pci_dev *dev,
struct resource *root,
struct resource *res,
int barnum
)
{
int where;
u32 barval = 0;
DBG_RES("pcibios_update_resource(%s, ..., %d) [%lx,%lx]/%x\n",
dev->slot_name,
barnum, res->start, res->end, (int) res->flags);
if (barnum >= PCI_BRIDGE_RESOURCES) {
/* handled in PCI-PCI bridge specific support */
return;
}
if (barnum == PCI_ROM_RESOURCE) {
where = PCI_ROM_ADDRESS;
} else {
/* 0-5 standard PCI "regions" */
where = PCI_BASE_ADDRESS_0 + (barnum * 4);
}
if (res->flags & IORESOURCE_IO) {
barval = PCI_PORT_ADDR(res->start);
} else if (res->flags & IORESOURCE_MEM) {
barval = PCI_BUS_ADDR(HBA_DATA(dev->bus->dev->platform_data), res->start);
} else {
panic("pcibios_update_resource() WTF? flags not IO or MEM");
}
pci_write_config_dword(dev, where, barval);
/* XXX FIXME - Elroy does support 64-bit (dual cycle) addressing.
** But at least one device (Symbios 53c896) which has 64-bit BAR
** doesn't actually work right with dual cycle addresses.
** So ignore the whole mess for now.
*/
if ((res->flags & (PCI_BASE_ADDRESS_SPACE
| PCI_BASE_ADDRESS_MEM_TYPE_MASK))
== (PCI_BASE_ADDRESS_SPACE_MEMORY
| PCI_BASE_ADDRESS_MEM_TYPE_64)) {
pci_write_config_dword(dev, where+4, 0);
DBGC("PCIBIOS: dev %s type 64-bit\n", dev->name);
}
}
/*
** Called by pci_set_master() - a driver interface.
**
......@@ -345,13 +277,16 @@ pcibios_link_hba_resources( struct resource *hba_res, struct resource *r)
/*
** called by drivers/pci/setup-res.c:pci_setup_bridge().
*/
void __devinit pcibios_fixup_pbus_ranges(
struct pci_bus *bus,
struct pbus_set_ranges_data *ranges
void __devinit pcibios_resource_to_bus(
struct pci_dev *dev,
struct pci_bus_region *region,
struct resource *res
)
{
struct pci_bus *bus = dev->bus;
struct pci_hba_data *hba = HBA_DATA(bus->dev->platform_data);
if (res->flags & IORESOURCE_IO) {
/*
** I/O space may see busnumbers here. Something
** in the form of 0xbbxxxx where bb is the bus num
......@@ -359,16 +294,17 @@ void __devinit pcibios_fixup_pbus_ranges(
** Remaining address translation are done in the
** PCI Host adapter specific code - ie dino_out8.
*/
ranges->io_start = PCI_PORT_ADDR(ranges->io_start);
ranges->io_end = PCI_PORT_ADDR(ranges->io_end);
region->start = PCI_PORT_ADDR(res->start);
region->end = PCI_PORT_ADDR(res->end);
} else if (res->flags & IORESOURCE_MEM) {
/* Convert MMIO addr to PCI addr (undo global virtualization) */
ranges->mem_start = PCI_BUS_ADDR(hba, ranges->mem_start);
ranges->mem_end = PCI_BUS_ADDR(hba, ranges->mem_end);
region->start = PCI_BUS_ADDR(hba, res->start);
region->end = PCI_BUS_ADDR(hba, res->end);
}
DBG_RES("pcibios_fixup_pbus_ranges(%02x, [%lx,%lx %lx,%lx])\n", bus->number,
ranges->io_start, ranges->io_end,
ranges->mem_start, ranges->mem_end);
DBG_RES("pcibios_resource_to_bus(%02x %s [%lx,%lx])\n",
bus->number, res->flags & IORESOURCE_IO ? "IO" : "MEM",
region->start, region->end);
/* KLUGE ALERT
** if this resource isn't linked to a "parent", then it seems
......@@ -378,6 +314,10 @@ void __devinit pcibios_fixup_pbus_ranges(
pcibios_link_hba_resources(&hba->lmmio_space, bus->resource[1]);
}
#ifdef CONFIG_HOTPLUG
EXPORT_SYMBOL(pcibios_resource_to_bus);
#endif
#define MAX(val1, val2) ((val1) > (val2) ? (val1) : (val2))
......
arch/ppc/kernel/pci.c
View file @ 17ec8d17
......@@ -93,46 +93,6 @@ fixup_broken_pcnet32(struct pci_dev* dev)
}
}
void
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
u32 new, check;
int reg;
struct pci_controller* hose = dev->sysdata;
unsigned long io_offset;
new = res->start;
res->flags &= ~IORESOURCE_UNSET;
if (hose && res->flags & IORESOURCE_IO) {
io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
new -= io_offset;
}
if (hose && res->flags & IORESOURCE_MEM)
new -= hose->pci_mem_offset;
new |= (res->flags & PCI_REGION_FLAG_MASK);
if (resource < 6) {
reg = PCI_BASE_ADDRESS_0 + 4*resource;
} else if (resource == PCI_ROM_RESOURCE) {
res->flags |= PCI_ROM_ADDRESS_ENABLE;
reg = dev->rom_base_reg;
} else {
/* Somebody might have asked allocation of a non-standard resource */
return;
}
pci_write_config_dword(dev, reg, new);
pci_read_config_dword(dev, reg, &check);
if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
printk(KERN_ERR "PCI: Error while updating region "
"%s/%d (%08x != %08x)\n", dev->slot_name, resource,
new, check);
}
printk(KERN_INFO "PCI: moved device %s resource %d (%lx) to %x\n",
dev->slot_name, resource, res->flags,
new & ~PCI_REGION_FLAG_MASK);
}
static void
pcibios_fixup_resources(struct pci_dev *dev)
{
......@@ -1107,11 +1067,6 @@ common_swizzle(struct pci_dev *dev, unsigned char *pinp)
return PCI_SLOT(dev->devfn);
}
void __devinit
pcibios_fixup_pbus_ranges(struct pci_bus * bus, struct pbus_set_ranges_data * ranges)
{
}
unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
unsigned long start, unsigned long size)
{
......
arch/ppc64/kernel/pci.c
View file @ 17ec8d17
......@@ -127,42 +127,6 @@ struct pci_dev *pci_find_dev_by_addr(unsigned long addr)
return NULL;
}
void __devinit pcibios_fixup_pbus_ranges(struct pci_bus *pbus,
struct pbus_set_ranges_data *pranges)
{
}
void
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
u32 new, check;
int reg;
struct pci_controller* hose = PCI_GET_PHB_PTR(dev);
new = res->start;
if (hose && res->flags & IORESOURCE_MEM)
new -= hose->pci_mem_offset;
new |= (res->flags & PCI_REGION_FLAG_MASK);
if (resource < 6) {
reg = PCI_BASE_ADDRESS_0 + 4*resource;
} else if (resource == PCI_ROM_RESOURCE) {
res->flags |= PCI_ROM_ADDRESS_ENABLE;
reg = dev->rom_base_reg;
} else {
/* Somebody might have asked allocation of a non-standard resource */
return;
}
pci_write_config_dword(dev, reg, new);
pci_read_config_dword(dev, reg, &check);
if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
printk(KERN_ERR "PCI: Error while updating region "
"%s/%d (%08x != %08x)\n", dev->slot_name, resource,
new, check);
}
}
static void
pcibios_fixup_resources(struct pci_dev* dev)
{
......
arch/sh/kernel/pci-dc.c
View file @ 17ec8d17
......@@ -113,10 +113,6 @@ void pci_free_consistent(struct pci_dev *hwdev, size_t size,
}
void __devinit pcibios_fixup_pbus_ranges(struct pci_bus *bus, struct pbus_set_ranges_data *ranges)
{
}
void __init pcibios_fixup_bus(struct pci_bus *bus)
{
struct list_head *ln;
......
arch/sh/kernel/pci-sh7751.c
View file @ 17ec8d17
......@@ -250,12 +250,6 @@ struct pci_fixup pcibios_fixups[] = {
{ 0 }
};
void __devinit pcibios_fixup_pbus_ranges(struct pci_bus *b,
struct pbus_set_ranges_data *range)
{
/* No fixups needed */
}
/*
* Called after each bus is probed, but before its children
* are examined.
......
arch/sh/kernel/pci_st40.c
View file @ 17ec8d17
......@@ -380,12 +380,6 @@ static int __init map_harp_irq(struct pci_dev *dev, u8 slot, u8 pin)
}
void __devinit
pcibios_fixup_pbus_ranges(struct pci_bus *bus,
struct pbus_set_ranges_data *ranges)
{
}
void __init pcibios_init(void)
{
extern unsigned long memory_start, memory_end;
......
arch/sh/kernel/pcibios.c
View file @ 17ec8d17
......@@ -6,7 +6,6 @@
* This is GPL'd.
*
* Provided here are generic versions of:
* pcibios_update_resource()
* pcibios_align_resource()
* pcibios_enable_device()
* pcibios_set_master()
......@@ -19,41 +18,12 @@
* pcibios_fixup_bus()
* pcibios_init()
* pcibios_setup()
* pcibios_fixup_pbus_ranges()
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
void
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
u32 new, check;
int reg;
new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
if (resource < 6) {
reg = PCI_BASE_ADDRESS_0 + 4*resource;
} else if (resource == PCI_ROM_RESOURCE) {
res->flags |= PCI_ROM_ADDRESS_ENABLE;
new |= PCI_ROM_ADDRESS_ENABLE;
reg = dev->rom_base_reg;
} else {
/* Somebody might have asked allocation of a non-standard resource */
return;
}
pci_write_config_dword(dev, reg, new);
pci_read_config_dword(dev, reg, &check);
if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
printk(KERN_ERR "PCI: Error while updating region "
"%s/%d (%08x != %08x)\n", dev->slot_name, resource,
new, check);
}
}
/*
* We need to avoid collisions with `mirrored' VGA ports
* and other strange ISA hardware, so we always want the
......
arch/sparc/kernel/pcic.c
View file @ 17ec8d17
......@@ -854,13 +854,6 @@ char * __init pcibios_setup(char *str)
return str;
}
/*
*/
void pcibios_update_resource(struct pci_dev *pdev, struct resource *res1,
struct resource *res2, int index)
{
}
void pcibios_align_resource(void *data, struct resource *res,
unsigned long size, unsigned long align)
{
......
arch/sparc64/kernel/pci.c
View file @ 17ec8d17
......@@ -470,20 +470,10 @@ int pci_assign_resource(struct pci_dev *pdev, int resource)
return err;
}
void pcibios_update_resource(struct pci_dev *pdev, struct resource *res1,
struct resource *res2, int index)
{
}
void pcibios_update_irq(struct pci_dev *pdev, int irq)
{
}
void __devinit pcibios_fixup_pbus_ranges(struct pci_bus *pbus,
struct pbus_set_ranges_data *pranges)
{
}
void pcibios_align_resource(void *data, struct resource *res,
unsigned long size, unsigned long align)
{
......
arch/v850/kernel/rte_mb_a_pci.c
View file @ 17ec8d17
......@@ -287,44 +287,20 @@ void __devinit pcibios_update_irq (struct pci_dev *dev, int irq)
pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
}
void __nomods_init
pcibios_update_resource (struct pci_dev *dev, struct resource *root,
struct resource *r, int resource)
void __devinit
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res)
{
u32 new, check;
int reg;
unsigned long offset = 0;
if (r->flags & IORESOURCE_IO)
new = (((r->start - MB_A_PCI_IO_ADDR)
& PCI_BASE_ADDRESS_IO_MASK)
| PCI_BASE_ADDRESS_SPACE_IO);
else if (r->flags & IORESOURCE_MEM)
new = (((r->start - MB_A_PCI_MEM_ADDR)
& PCI_BASE_ADDRESS_MEM_MASK)
| PCI_BASE_ADDRESS_MEM_TYPE_32
| ((r->flags & IORESOURCE_PREFETCH)
? PCI_BASE_ADDRESS_MEM_PREFETCH
: 0)
| PCI_BASE_ADDRESS_SPACE_MEMORY);
else
panic ("pcibios_update_resource: unknown resource type");
if (resource < 6)
reg = PCI_BASE_ADDRESS_0 + 4*resource;
else if (resource == PCI_ROM_RESOURCE) {
r->flags |= PCI_ROM_ADDRESS_ENABLE;
new |= PCI_ROM_ADDRESS_ENABLE;
reg = dev->rom_base_reg;
} else
return;
pci_write_config_dword(dev, reg, new);
pci_read_config_dword(dev, reg, &check);
if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
printk (KERN_ERR "PCI: Error while updating region "
"%s/%d (%08x != %08x)\n", dev->slot_name, resource,
new, check);
if (res->flags & IORESOURCE_IO) {
offset = MB_A_PCI_IO_ADDR;
} else if (res->flags & IORESOURCE_MEM) {
offset = MB_A_PCI_MEM_ADDR;
}
region->start = res->start - offset;
region->end = res->end - offset;
}
......
arch/x86_64/pci/x86-64.c
View file @ 17ec8d17
......@@ -33,34 +33,6 @@
#include "pci.h"
void
pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
u32 new, check;
int reg;
new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
if (resource < 6) {
reg = PCI_BASE_ADDRESS_0 + 4*resource;
} else if (resource == PCI_ROM_RESOURCE) {
res->flags |= PCI_ROM_ADDRESS_ENABLE;
new |= PCI_ROM_ADDRESS_ENABLE;
reg = dev->rom_base_reg;
} else {
/* Somebody might have asked allocation of a non-standard resource */
return;
}
pci_write_config_dword(dev, reg, new);
pci_read_config_dword(dev, reg, &check);
if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
printk(KERN_ERR "PCI: Error while updating region "
"%s/%d (%08x != %08x)\n", dev->slot_name, resource,
new, check);
}
}
/*
* We need to avoid collisions with `mirrored' VGA ports
* and other strange ISA hardware, so we always want the
......
drivers/pci/pci.ids
View file @ 17ec8d17
......@@ -5440,6 +5440,11 @@
14f1 2004 Dynalink 56PMi
8234 RS8234 ATM SAR Controller [ServiceSAR Plus]
14f2 MOBILITY Electronics
0120 EV1000 bridge
0121 EV1000 Parallel port
0122 EV1000 Serial port
0123 EV1000 Keyboard controller
0124 EV1000 Mouse controller
14f3 BROADLOGIC
14f4 TOKYO Electronic Industry CO Ltd
14f5 SOPAC Ltd
......
drivers/pci/probe.c
View file @ 17ec8d17
......@@ -15,6 +15,9 @@
#define DBG(x...)
#endif
#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
#define CARDBUS_RESERVE_BUSNR 3
LIST_HEAD(pci_root_buses);
LIST_HEAD(pci_devices);
......@@ -291,12 +294,15 @@ static unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
*/
int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
{
unsigned int buses;
struct pci_bus *child;
int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
u32 buses;
pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n", dev->slot_name, buses & 0xffffff, pass);
DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n",
dev->slot_name, buses & 0xffffff, pass);
if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
unsigned int cmax;
/*
......@@ -333,8 +339,10 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max
* yenta.c forces a secondary latency timer of 176.
* Copy that behaviour here.
*/
if (is_cardbus)
buses = (buses & 0x00ffffff) | (176 << 24);
if (is_cardbus) {
buses &= ~0xff000000;
buses |= CARDBUS_LATENCY_TIMER << 24;
}
/*
* We need to blast all three values with a single write.
......@@ -350,7 +358,7 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max
* as cards with a PCI-to-PCI bridge can be
* inserted later.
*/
max += 3;
max += CARDBUS_RESERVE_BUSNR;
}
/*
* Set the subordinate bus number to its real value.
......@@ -358,6 +366,7 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max
child->subordinate = max;
pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
}
sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
return max;
......@@ -391,8 +400,11 @@ int pci_setup_device(struct pci_dev * dev)
{
u32 class;
sprintf(dev->slot_name, "%02x:%02x.%d", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
sprintf(dev->dev.name, "PCI device %04x:%04x", dev->vendor, dev->device);
sprintf(dev->slot_name, "%02x:%02x.%d", dev->bus->number,
PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
sprintf(dev->dev.name, "PCI device %04x:%04x",
dev->vendor, dev->device);
INIT_LIST_HEAD(&dev->pools);
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
......@@ -400,8 +412,8 @@ int pci_setup_device(struct pci_dev * dev)
dev->class = class;
class >>= 8;
DBG("Found %02x:%02x [%04x/%04x] %06x %02x\n", dev->bus->number, dev->devfn,
dev->vendor, dev->device, class, dev->hdr_type);
DBG("Found %02x:%02x [%04x/%04x] %06x %02x\n", dev->bus->number,
dev->devfn, dev->vendor, dev->device, class, dev->hdr_type);
/* "Unknown power state" */
dev->current_state = 4;
......@@ -468,7 +480,8 @@ pci_scan_device(struct pci_bus *bus, int devfn)
return NULL;
/* some broken boards return 0 or ~0 if a slot is empty: */
if (l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff || l == 0xffff0000)
if (l == 0xffffffff || l == 0x00000000 ||
l == 0x0000ffff || l == 0xffff0000)
return NULL;
dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
......@@ -520,11 +533,14 @@ int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
struct pci_dev *dev;
dev = pci_scan_device(bus, devfn);
if (func == 0) {
if (!dev)
break;
} else {
if (!dev)
continue;
if (func != 0)
dev->multifunction = 1;
}
/* Fix up broken headers */
pci_fixup_device(PCI_FIXUP_HEADER, dev);
......@@ -647,7 +663,8 @@ struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, int bus,
if (b) {
b->sysdata = sysdata;
b->ops = ops;
b->subordinate = pci_do_scan_bus(b);
b->subordinate = pci_scan_child_bus(b);
pci_bus_add_devices(b);
}
return b;
}
......
drivers/pci/setup-bus.c
View file @ 17ec8d17
......@@ -72,40 +72,29 @@ pbus_assign_resources_sorted(struct pci_bus *bus)
requires that if there is no I/O ports or memory behind the
bridge, corresponding range must be turned off by writing base
value greater than limit to the bridge's base/limit registers. */
static void __devinit
pci_setup_bridge(struct pci_bus *bus)
static void __devinit pci_setup_bridge(struct pci_bus *bus)
{
struct pbus_set_ranges_data ranges;
struct pci_dev *bridge = bus->self;
struct pci_bus_region region;
u32 l;
if (!bridge || (bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
return;
ranges.io_start = bus->resource[0]->start;
ranges.io_end = bus->resource[0]->end;
ranges.mem_start = bus->resource[1]->start;
ranges.mem_end = bus->resource[1]->end;
ranges.prefetch_start = bus->resource[2]->start;
ranges.prefetch_end = bus->resource[2]->end;
pcibios_fixup_pbus_ranges(bus, &ranges);
DBGC((KERN_INFO "PCI: Bus %d, bridge: %s\n",
bus->number, bridge->dev.name));
/* Set up the top and bottom of the PCI I/O segment for this bus. */
pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
if (bus->resource[0]->flags & IORESOURCE_IO) {
pci_read_config_dword(bridge, PCI_IO_BASE, &l);
l &= 0xffff0000;
l |= (ranges.io_start >> 8) & 0x00f0;
l |= ranges.io_end & 0xf000;
l |= (region.start >> 8) & 0x00f0;
l |= region.end & 0xf000;
/* Set up upper 16 bits of I/O base/limit. */
pci_write_config_word(bridge, PCI_IO_BASE_UPPER16,
ranges.io_start >> 16);
region.start >> 16);
pci_write_config_word(bridge, PCI_IO_LIMIT_UPPER16,
ranges.io_end >> 16);
region.end >> 16);
DBGC((KERN_INFO " IO window: %04lx-%04lx\n",
ranges.io_start, ranges.io_end));
region.start, region.end));
}
else {
/* Clear upper 16 bits of I/O base/limit. */
......@@ -117,11 +106,12 @@ pci_setup_bridge(struct pci_bus *bus)
/* Set up the top and bottom of the PCI Memory segment
for this bus. */
pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
if (bus->resource[1]->flags & IORESOURCE_MEM) {
l = (ranges.mem_start >> 16) & 0xfff0;
l |= ranges.mem_end & 0xfff00000;
l = (region.start >> 16) & 0xfff0;
l |= region.end & 0xfff00000;
DBGC((KERN_INFO " MEM window: %08lx-%08lx\n",
ranges.mem_start, ranges.mem_end));
region.start, region.end));
}
else {
l = 0x0000fff0;
......@@ -134,11 +124,12 @@ pci_setup_bridge(struct pci_bus *bus)
pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
/* Set up PREF base/limit. */
pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
l = (ranges.prefetch_start >> 16) & 0xfff0;
l |= ranges.prefetch_end & 0xfff00000;
l = (region.start >> 16) & 0xfff0;
l |= region.end & 0xfff00000;
DBGC((KERN_INFO " PREFETCH window: %08lx-%08lx\n",
ranges.prefetch_start, ranges.prefetch_end));
region.start, region.end));
}
else {
l = 0x0000fff0;
......@@ -284,7 +275,7 @@ pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
order = 0;
/* Exclude ranges with size > align from
calculation of the alignment. */
if (size == align)
if (r_size == align)
aligns[order] += align;
if (order > max_order)
max_order = order;
......
drivers/pci/setup-res.c
View file @ 17ec8d17
......@@ -33,6 +33,59 @@
#endif
static void
pci_update_resource(struct pci_dev *dev, struct resource *res, int resno)
{
struct pci_bus_region region;
u32 new, check, mask;
int reg;
pcibios_resource_to_bus(dev, &region, res);
DBGC((KERN_ERR " got res [%lx:%lx] bus [%lx:%lx] for "
"resource %d of %s\n", res->start, res->end,
region.start, region.end, resno, dev->dev.name));
new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
if (res->flags & IORESOURCE_IO)
mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
else
mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
if (resno < 6) {
reg = PCI_BASE_ADDRESS_0 + 4 * resno;
} else if (resno == PCI_ROM_RESOURCE) {
new |= res->flags & PCI_ROM_ADDRESS_ENABLE;
reg = dev->rom_base_reg;
} else {
/* Hmm, non-standard resource. */
printk("PCI: trying to set non-standard region %s/%d\n",
dev->slot_name, resno);
return;
}
pci_write_config_dword(dev, reg, new);
pci_read_config_dword(dev, reg, &check);
if ((new ^ check) & mask) {
printk(KERN_ERR "PCI: Error while updating region "
"%s/%d (%08x != %08x)\n", dev->slot_name, resno,
new, check);
}
if ((new & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
(PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) {
new = 0; /* currently everyone zeros the high address */
pci_write_config_dword(dev, reg + 4, new);
pci_read_config_dword(dev, reg + 4, &check);
if (check != new) {
printk(KERN_ERR "PCI: Error updating region "
"%s/%d (high %08x != %08x)\n",
dev->slot_name, resno, new, check);
}
}
}
int __init
pci_claim_resource(struct pci_dev *dev, int resource)
{
......@@ -89,10 +142,7 @@ int pci_assign_resource(struct pci_dev *dev, int resno)
printk(KERN_ERR "PCI: Failed to allocate resource %d(%lx-%lx) for %s\n",
resno, res->start, res->end, dev->slot_name);
} else {
DBGC((KERN_ERR " got res[%lx:%lx] for resource %d of %s\n",
res->start, res->end, i, dev->dev.name));
/* Update PCI config space. */
pcibios_update_resource(dev, res->parent, res, resno);
pci_update_resource(dev, res, resno);
}
return ret;
......
include/asm-alpha/pci.h
View file @ 17ec8d17
......@@ -190,6 +190,11 @@ pci_dac_dma_sync_single(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len,
/* Return the index of the PCI controller for device PDEV. */
extern int pci_controller_num(struct pci_dev *pdev);
extern void
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res);
#endif /* __KERNEL__ */
/* Values for the `which' argument to sys_pciconfig_iobase. */
......
include/asm-arm/pci.h
View file @ 17ec8d17
......@@ -175,6 +175,10 @@ void pci_pool_free (struct pci_pool *pool, void *vaddr, dma_addr_t addr);
extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
enum pci_mmap_state mmap_state, int write_combine);
extern void
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res);
#endif /* __KERNEL__ */
#endif
include/asm-generic/pci.h 0 → 100644
View file @ 17ec8d17
/*
* linux/include/asm-generic/pci.h
*
* Copyright (C) 2003 Russell King
*/
#ifndef _ASM_GENERIC_PCI_H
#define _ASM_GENERIC_PCI_H
/**
* pcibios_resource_to_bus - convert resource to PCI bus address
* @dev: device which owns this resource
* @region: converted bus-centric region (start,end)
* @res: resource to convert
*
* Convert a resource to a PCI device bus address or bus window.
*/
static inline void
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res)
{
region->start = res->start;
region->end = res->end;
}
#endif
include/asm-i386/pci.h
View file @ 17ec8d17
......@@ -105,4 +105,7 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
/* implement the pci_ DMA API in terms of the generic device dma_ one */
#include <asm-generic/pci-dma-compat.h>
/* generic pci stuff */
#include <asm-generic/pci.h>
#endif /* __i386_PCI_H */
include/asm-ia64/pci.h
View file @ 17ec8d17
......@@ -97,4 +97,7 @@ extern int pcibios_prep_mwi (struct pci_dev *);
extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
enum pci_mmap_state mmap_state, int write_combine);
/* generic pci stuff */
#include <asm-generic/pci.h>
#endif /* _ASM_IA64_PCI_H */
include/asm-mips/pci.h
View file @ 17ec8d17
......@@ -252,4 +252,7 @@ extern inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
#endif /* __KERNEL__ */
/* generic pci stuff */
#include <asm-generic/pci.h>
#endif /* _ASM_PCI_H */
include/asm-mips64/pci.h
View file @ 17ec8d17
......@@ -272,4 +272,8 @@ static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
#endif /* __KERNEL__ */
/* generic pci stuff */
#include <asm-generic/pci.h>
#endif /* _ASM_PCI_H */
include/asm-parisc/pci.h
View file @ 17ec8d17
......@@ -186,4 +186,8 @@ extern inline void pcibios_register_hba(struct pci_hba_data *x)
/* export the pci_ DMA API in terms of the dma_ one */
#include <asm-generic/pci-dma-compat.h>
extern void
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res);
#endif /* __ASM_PARISC_PCI_H */
include/asm-ppc/pci.h
View file @ 17ec8d17
......@@ -273,4 +273,7 @@ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
#endif /* __KERNEL__ */
/* generic pci stuff */
#include <asm-generic/pci.h>
#endif /* __PPC_PCI_H */
include/asm-ppc64/pci.h
View file @ 17ec8d17
......@@ -124,4 +124,7 @@ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
#endif /* __KERNEL__ */
/* generic pci stuff */
#include <asm-generic/pci.h>
#endif /* __PPC64_PCI_H */
include/asm-sh/pci.h
View file @ 17ec8d17
......@@ -240,6 +240,8 @@ static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
#endif /* __KERNEL__ */
/* generic pci stuff */
#include <asm-generic/pci.h>
#endif /* __ASM_SH_PCI_H */
include/asm-sparc64/pci.h
View file @ 17ec8d17
......@@ -207,4 +207,7 @@ extern int pcibios_prep_mwi(struct pci_dev *dev);
#endif /* __KERNEL__ */
/* generic pci stuff */
#include <asm-generic/pci.h>
#endif /* __SPARC64_PCI_H */
include/asm-x86_64/pci.h
View file @ 17ec8d17
......@@ -279,4 +279,7 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
#endif /* __KERNEL__ */
/* generic pci stuff */
#include <asm-generic/pci.h>
#endif /* __x8664_PCI_H */
include/linux/pci.h
View file @ 17ec8d17
......@@ -485,11 +485,9 @@ struct pci_ops {
int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
};
struct pbus_set_ranges_data
{
unsigned long io_start, io_end;
unsigned long mem_start, mem_end;
unsigned long prefetch_start, prefetch_end;
struct pci_bus_region {
unsigned long start;
unsigned long end;
};
struct pci_driver {
......@@ -531,10 +529,7 @@ char *pcibios_setup (char *str);
/* Used only when drivers/pci/setup.c is used */
void pcibios_align_resource(void *, struct resource *,
unsigned long, unsigned long);
void pcibios_update_resource(struct pci_dev *, struct resource *,
struct resource *, int);
void pcibios_update_irq(struct pci_dev *, int irq);
void pcibios_fixup_pbus_ranges(struct pci_bus *, struct pbus_set_ranges_data *);
/* Generic PCI functions used internally */
......
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