Skip to content

L
linux
Commit 1afc0c89 authored by Yicong Yang's avatar Yicong Yang Committed by Vignesh Raghavendra
Browse files
Options

Revert "mtd: spi-nor: Add capability to disable flash quad mode" 

As the only user has been removed in previous patch, let's revert
this one together.

This reverts commit be192209.
Reported-by: default avatarMatthias Weisser <m.weisser.m@gmail.com>
Suggested-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: default avatarYicong Yang <yangyicong@hisilicon.com>
Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/1599205640-26690-2-git-send-email-yangyicong@hisilicon.com
parent 7d90a9b2
Show whitespace changes
Inline Side-by-side
Showing with 24 additions and 41 deletions
drivers/mtd/spi-nor/core.c
View file @ 1afc0c89
...@@ -1907,16 +1907,15 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) ...@@ -1907,16 +1907,15 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
} }
/** /**
* spi_nor_sr1_bit6_quad_enable() - Set/Unset the Quad Enable BIT(6) in the * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
* Status Register 1. * Register 1.
* @nor: pointer to a 'struct spi_nor' * @nor: pointer to a 'struct spi_nor'
* @enable: true to enable Quad mode, false to disable Quad mode.
* *
* Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
* *
* Return: 0 on success, -errno otherwise. * Return: 0 on success, -errno otherwise.
*/ */
int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor, bool enable) int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
{ {
int ret; int ret;
...@@ -1924,56 +1923,45 @@ int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor, bool enable) ...@@ -1924,56 +1923,45 @@ int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor, bool enable)
if (ret) if (ret)
return ret; return ret;
if ((enable && (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)) || if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
(!enable && !(nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)))
return 0; return 0;
if (enable)
nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
else
nor->bouncebuf[0] &= ~SR1_QUAD_EN_BIT6;
return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
} }
/** /**
* spi_nor_sr2_bit1_quad_enable() - set/unset the Quad Enable BIT(1) in the * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
* Status Register 2. * Register 2.
* @nor: pointer to a 'struct spi_nor'. * @nor: pointer to a 'struct spi_nor'.
* @enable: true to enable Quad mode, false to disable Quad mode.
* *
* Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories. * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
* *
* Return: 0 on success, -errno otherwise. * Return: 0 on success, -errno otherwise.
*/ */
int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor, bool enable) int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
{ {
int ret; int ret;
if (nor->flags & SNOR_F_NO_READ_CR) if (nor->flags & SNOR_F_NO_READ_CR)
return spi_nor_write_16bit_cr_and_check(nor, return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);
enable ? SR2_QUAD_EN_BIT1 : 0);
ret = spi_nor_read_cr(nor, nor->bouncebuf); ret = spi_nor_read_cr(nor, nor->bouncebuf);
if (ret) if (ret)
return ret; return ret;
if ((enable && (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)) || if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
(!enable && !(nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)))
return 0; return 0;
if (enable)
nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1; nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
else
nor->bouncebuf[0] &= ~SR2_QUAD_EN_BIT1;
return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]); return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
} }
/** /**
* spi_nor_sr2_bit7_quad_enable() - set/unset QE bit in Status Register 2. * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
* @nor: pointer to a 'struct spi_nor' * @nor: pointer to a 'struct spi_nor'
* @enable: true to enable Quad mode, false to disable Quad mode.
* *
* Set the Quad Enable (QE) bit in the Status Register 2. * Set the Quad Enable (QE) bit in the Status Register 2.
* *
...@@ -1983,7 +1971,7 @@ int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor, bool enable) ...@@ -1983,7 +1971,7 @@ int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor, bool enable)
* *
* Return: 0 on success, -errno otherwise. * Return: 0 on success, -errno otherwise.
*/ */
int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor, bool enable) int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
{ {
u8 *sr2 = nor->bouncebuf; u8 *sr2 = nor->bouncebuf;
int ret; int ret;
...@@ -1993,15 +1981,11 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor, bool enable) ...@@ -1993,15 +1981,11 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor, bool enable)
ret = spi_nor_read_sr2(nor, sr2); ret = spi_nor_read_sr2(nor, sr2);
if (ret) if (ret)
return ret; return ret;
if ((enable && (*sr2 & SR2_QUAD_EN_BIT7)) || if (*sr2 & SR2_QUAD_EN_BIT7)
(!enable && !(*sr2 & SR2_QUAD_EN_BIT7)))
return 0; return 0;
/* Update the Quad Enable bit. */ /* Update the Quad Enable bit. */
if (enable)
*sr2 |= SR2_QUAD_EN_BIT7; *sr2 |= SR2_QUAD_EN_BIT7;
else
*sr2 &= ~SR2_QUAD_EN_BIT7;
ret = spi_nor_write_sr2(nor, sr2); ret = spi_nor_write_sr2(nor, sr2);
if (ret) if (ret)
...@@ -2914,13 +2898,12 @@ static int spi_nor_init_params(struct spi_nor *nor) ...@@ -2914,13 +2898,12 @@ static int spi_nor_init_params(struct spi_nor *nor)
} }
/** /**
* spi_nor_quad_enable() - enable/disable Quad I/O if needed. * spi_nor_quad_enable() - enable Quad I/O if needed.
* @nor: pointer to a 'struct spi_nor' * @nor: pointer to a 'struct spi_nor'
* @enable: true to enable Quad mode. false to disable Quad mode.
* *
* Return: 0 on success, -errno otherwise. * Return: 0 on success, -errno otherwise.
*/ */
static int spi_nor_quad_enable(struct spi_nor *nor, bool enable) static int spi_nor_quad_enable(struct spi_nor *nor)
{ {
if (!nor->params->quad_enable) if (!nor->params->quad_enable)
return 0; return 0;
...@@ -2929,7 +2912,7 @@ static int spi_nor_quad_enable(struct spi_nor *nor, bool enable) ...@@ -2929,7 +2912,7 @@ static int spi_nor_quad_enable(struct spi_nor *nor, bool enable)
spi_nor_get_protocol_width(nor->write_proto) == 4)) spi_nor_get_protocol_width(nor->write_proto) == 4))
return 0; return 0;
return nor->params->quad_enable(nor, enable); return nor->params->quad_enable(nor);
} }
/** /**
...@@ -2953,7 +2936,7 @@ static int spi_nor_init(struct spi_nor *nor) ...@@ -2953,7 +2936,7 @@ static int spi_nor_init(struct spi_nor *nor)
{ {
int err; int err;
err = spi_nor_quad_enable(nor, true); err = spi_nor_quad_enable(nor);
if (err) { if (err) {
dev_dbg(nor->dev, "quad mode not supported\n"); dev_dbg(nor->dev, "quad mode not supported\n");
return err; return err;
......
drivers/mtd/spi-nor/core.h
View file @ 1afc0c89
...@@ -198,7 +198,7 @@ struct spi_nor_locking_ops { ...@@ -198,7 +198,7 @@ struct spi_nor_locking_ops {
* higher index in the array, the higher priority. * higher index in the array, the higher priority.
* @erase_map: the erase map parsed from the SFDP Sector Map Parameter * @erase_map: the erase map parsed from the SFDP Sector Map Parameter
* Table. * Table.
* @quad_enable: enables/disables SPI NOR Quad mode. * @quad_enable: enables SPI NOR quad mode.
* @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
* @convert_addr: converts an absolute address into something the flash * @convert_addr: converts an absolute address into something the flash
* will understand. Particularly useful when pagesize is * will understand. Particularly useful when pagesize is
...@@ -219,7 +219,7 @@ struct spi_nor_flash_parameter { ...@@ -219,7 +219,7 @@ struct spi_nor_flash_parameter {
struct spi_nor_erase_map erase_map; struct spi_nor_erase_map erase_map;
int (*quad_enable)(struct spi_nor *nor, bool enable); int (*quad_enable)(struct spi_nor *nor);
int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
u32 (*convert_addr)(struct spi_nor *nor, u32 addr); u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps); int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
...@@ -406,9 +406,9 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear); ...@@ -406,9 +406,9 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear);
int spi_nor_wait_till_ready(struct spi_nor *nor); int spi_nor_wait_till_ready(struct spi_nor *nor);
int spi_nor_lock_and_prep(struct spi_nor *nor); int spi_nor_lock_and_prep(struct spi_nor *nor);
void spi_nor_unlock_and_unprep(struct spi_nor *nor); void spi_nor_unlock_and_unprep(struct spi_nor *nor);
int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor, bool enable); int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor);
int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor, bool enable); int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);
int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor, bool enable); int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);
int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr); int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr);
ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7