Commit 237d5cc7 authored by Thierry Reding's avatar Thierry Reding

arm64: tegra: Add sor1_src clock

The sor1 IP block needs the sor1_src clock to configure the clock tree
depending on whether it's running in HDMI or DP mode.
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 241f02ba
...@@ -186,10 +186,11 @@ sor@54580000 { ...@@ -186,10 +186,11 @@ sor@54580000 {
reg = <0x0 0x54580000 0x0 0x00040000>; reg = <0x0 0x54580000 0x0 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SOR1>, clocks = <&tegra_car TEGRA210_CLK_SOR1>,
<&tegra_car TEGRA210_CLK_SOR1_SRC>,
<&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
<&tegra_car TEGRA210_CLK_PLL_DP>, <&tegra_car TEGRA210_CLK_PLL_DP>,
<&tegra_car TEGRA210_CLK_SOR_SAFE>; <&tegra_car TEGRA210_CLK_SOR_SAFE>;
clock-names = "sor", "parent", "dp", "safe"; clock-names = "sor", "source", "parent", "dp", "safe";
resets = <&tegra_car 183>; resets = <&tegra_car 183>;
reset-names = "sor"; reset-names = "sor";
pinctrl-0 = <&state_dpaux1_aux>; pinctrl-0 = <&state_dpaux1_aux>;
......
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