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Commit 241b2ec9 authored by Jerry (Fangzhi) Zuo's avatar Jerry (Fangzhi) Zuo Committed by Alex Deucher
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drm/amd/display: Add dcn30 Headers (v2) 

DCN 3.0 display controller registers

v2: squash in updates from Bhawan.
Signed-off-by: default avatarJerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: default avatarHersen Wu <hersenxs.wu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a5a25977
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drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h 0 → 100755
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drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h 0 → 100755
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drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_offset.h 0 → 100755
View file @ 241b2ec9
#ifndef _dpcs_3_0_0_OFFSET_HEADER
#define _dpcs_3_0_0_OFFSET_HEADER
// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
// base address: 0x0
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929
#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a
#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
// base address: 0x0
#define mmRDPCSTX0_RDPCSTX_CNTL 0x2930
#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935
#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936
#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2937
#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_SPARE 0x2938
#define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_CNTL2 0x2939
#define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953
#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2955
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0x2956
#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr0_dispdec
// base address: 0x0
#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
// base address: 0x360
#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x2a00
#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_TX_CNTL 0x2a01
#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x2a02
#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0x2a03
#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x2a04
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
// base address: 0x360
#define mmRDPCSTX1_RDPCSTX_CNTL 0x2a08
#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09
#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a
#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0x2a0b
#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c
#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d
#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e
#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_SCRATCH 0x2a0f
#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_SPARE 0x2a10
#define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_CNTL2 0x2a11
#define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26
#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a
#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b
#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2a2c
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2a2d
#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0x2a2e
#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr1_dispdec
// base address: 0x360
#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx2_dispdec
// base address: 0x6c0
#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL 0x2ad8
#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_TX_CNTL 0x2ad9
#define mmDPCSTX2_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_CBUS_CNTL 0x2ada
#define mmDPCSTX2_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL 0x2adb
#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR 0x2adc
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA 0x2add
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
// base address: 0x6c0
#define mmRDPCSTX2_RDPCSTX_CNTL 0x2ae0
#define mmRDPCSTX2_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL 0x2ae1
#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0x2ae2
#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA 0x2ae3
#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX2_RDPCS_TX_CR_ADDR 0x2ae4
#define mmRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX2_RDPCS_TX_CR_DATA 0x2ae5
#define mmRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL 0x2ae6
#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_SCRATCH 0x2ae7
#define mmRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_SPARE 0x2ae8
#define mmRDPCSTX2_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_CNTL2 0x2ae9
#define mmRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2aec
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2 0x2af2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3 0x2af3
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4 0x2af4
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5 0x2af5
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6 0x2af6
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7 0x2af7
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8 0x2af8
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9 0x2af9
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10 0x2afa
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11 0x2afb
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12 0x2afc
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13 0x2afd
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14 0x2afe
#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0 0x2aff
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1 0x2b00
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2 0x2b01
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3 0x2b02
#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0x2b03
#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2b04
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2b05
#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG 0x2b06
#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr2_dispdec
// base address: 0x6c0
#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx3_dispdec
// base address: 0xa20
#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL 0x2bb0
#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_TX_CNTL 0x2bb1
#define mmDPCSTX3_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_CBUS_CNTL 0x2bb2
#define mmDPCSTX3_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL 0x2bb3
#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR 0x2bb4
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA 0x2bb5
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
// base address: 0xa20
#define mmRDPCSTX3_RDPCSTX_CNTL 0x2bb8
#define mmRDPCSTX3_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL 0x2bb9
#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0x2bba
#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA 0x2bbb
#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX3_RDPCS_TX_CR_ADDR 0x2bbc
#define mmRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX3_RDPCS_TX_CR_DATA 0x2bbd
#define mmRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL 0x2bbe
#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_SCRATCH 0x2bbf
#define mmRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_SPARE 0x2bc0
#define mmRDPCSTX3_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_CNTL2 0x2bc1
#define mmRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2bc4
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2 0x2bca
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3 0x2bcb
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4 0x2bcc
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5 0x2bcd
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6 0x2bce
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7 0x2bcf
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8 0x2bd0
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9 0x2bd1
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10 0x2bd2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11 0x2bd3
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12 0x2bd4
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13 0x2bd5
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14 0x2bd6
#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0 0x2bd7
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1 0x2bd8
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2 0x2bd9
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3 0x2bda
#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0x2bdb
#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2bdc
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2bdd
#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG 0x2bde
#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr3_dispdec
// base address: 0xa20
#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR 0x2bbc
#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA 0x2bbd
#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx4_dispdec
// base address: 0xd80
#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL 0x2c88
#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_TX_CNTL 0x2c89
#define mmDPCSTX4_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_CBUS_CNTL 0x2c8a
#define mmDPCSTX4_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL 0x2c8b
#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR 0x2c8c
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA 0x2c8d
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
// base address: 0xd80
#define mmRDPCSTX4_RDPCSTX_CNTL 0x2c90
#define mmRDPCSTX4_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL 0x2c91
#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL 0x2c92
#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA 0x2c93
#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX4_RDPCS_TX_CR_ADDR 0x2c94
#define mmRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX4_RDPCS_TX_CR_DATA 0x2c95
#define mmRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL 0x2c96
#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_SCRATCH 0x2c97
#define mmRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_SPARE 0x2c98
#define mmRDPCSTX4_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_CNTL2 0x2c99
#define mmRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2c9c
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0 0x2ca0
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1 0x2ca1
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2 0x2ca2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3 0x2ca3
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4 0x2ca4
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5 0x2ca5
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6 0x2ca6
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7 0x2ca7
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8 0x2ca8
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9 0x2ca9
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10 0x2caa
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11 0x2cab
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12 0x2cac
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13 0x2cad
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14 0x2cae
#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0 0x2caf
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1 0x2cb0
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2 0x2cb1
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3 0x2cb2
#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL 0x2cb3
#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2cb4
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2cb5
#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG 0x2cb6
#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr4_dispdec
// base address: 0xd80
#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR 0x2c94
#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX 2
#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA 0x2c95
#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_dpcstx5_dispdec
// base address: 0x10e0
#define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL 0x2d60
#define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_TX_CNTL 0x2d61
#define mmDPCSTX5_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_CBUS_CNTL 0x2d62
#define mmDPCSTX5_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_INTERRUPT_CNTL 0x2d63
#define mmDPCSTX5_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR 0x2d64
#define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA 0x2d65
#define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx5_dispdec
// base address: 0x10e0
#define mmRDPCSTX5_RDPCSTX_CNTL 0x2d68
#define mmRDPCSTX5_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_CLOCK_CNTL 0x2d69
#define mmRDPCSTX5_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_INTERRUPT_CONTROL 0x2d6a
#define mmRDPCSTX5_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PLL_UPDATE_DATA 0x2d6b
#define mmRDPCSTX5_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX5_RDPCS_TX_CR_ADDR 0x2d6c
#define mmRDPCSTX5_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX5_RDPCS_TX_CR_DATA 0x2d6d
#define mmRDPCSTX5_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX5_RDPCS_TX_SRAM_CNTL 0x2d6e
#define mmRDPCSTX5_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_SCRATCH 0x2d6f
#define mmRDPCSTX5_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_SPARE 0x2d70
#define mmRDPCSTX5_RDPCSTX_SPARE_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_CNTL2 0x2d71
#define mmRDPCSTX5_RDPCSTX_CNTL2_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2d74
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL0 0x2d78
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL1 0x2d79
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL2 0x2d7a
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL3 0x2d7b
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL4 0x2d7c
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL5 0x2d7d
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL6 0x2d7e
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL7 0x2d7f
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL8 0x2d80
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL9 0x2d81
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL10 0x2d82
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL11 0x2d83
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL12 0x2d84
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL13 0x2d85
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL14 0x2d86
#define mmRDPCSTX5_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE0 0x2d87
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE1 0x2d88
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE2 0x2d89
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE3 0x2d8a
#define mmRDPCSTX5_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_PHY_RX_LD_VAL 0x2d8b
#define mmRDPCSTX5_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2d8c
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2d8d
#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX5_RDPCSTX_DPALT_CONTROL_REG 0x2d8e
#define mmRDPCSTX5_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
#endif
drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_sh_mask.h 0 → 100755
View file @ 241b2ec9
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