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Commit 265c60c2 authored by Russell King's avatar Russell King
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[ARM PATCH] 1404/1: basic Lubbock/PXA250 updates 

Patch from Nicolas Pitre
parent d5ebb498
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Inline Side-by-side
Showing with 389 additions and 187 deletions
arch/arm/common/sa1111.c
View file @ 265c60c2
......@@ -418,6 +418,7 @@ static void sa1111_wake(struct sa1111 *sachip)
spin_lock_irqsave(&sachip->lock, flags);
#if CONFIG_ARCH_SA1100
/*
* First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
* (SA-1110 Developer's Manual, section 9.1.2.1)
......@@ -425,6 +426,11 @@ static void sa1111_wake(struct sa1111 *sachip)
GAFR |= GPIO_32_768kHz;
GPDR |= GPIO_32_768kHz;
TUCR = TUCR_3_6864MHz;
#elif CONFIG_ARCH_PXA
pxa_gpio_mode(GPIO11_3_6MHz_MD);
#else
#error missing clock setup
#endif
/*
* Turn VCO on, and disable PLL Bypass.
......@@ -461,6 +467,8 @@ static void sa1111_wake(struct sa1111 *sachip)
spin_unlock_irqrestore(&sachip->lock, flags);
}
#ifdef CONFIG_ARCH_SA1100
/*
* Configure the SA1111 shared memory controller.
*/
......@@ -476,6 +484,8 @@ sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac,
sa1111_writel(smcr, sachip->base + SA1111_SMCR);
}
#endif
static void
sa1111_init_one_child(struct sa1111 *sachip, struct sa1111_dev *sadev, unsigned int offset)
{
......@@ -569,6 +579,7 @@ __sa1111_probe(struct device *me, unsigned long phys_addr, int irq)
*/
sa1111_wake(sachip);
#ifdef CONFIG_ARCH_SA1100
/*
* The SDRAM configuration of the SA1110 and the SA1111 must
* match. This is very important to ensure that SA1111 accesses
......@@ -592,6 +603,7 @@ __sa1111_probe(struct device *me, unsigned long phys_addr, int irq)
* Enable the SA1110 memory bus request and grant signals.
*/
sa1110_mb_enable();
#endif
/*
* The interrupt controller must be initialised before any
......
arch/arm/mach-pxa/Makefile
View file @ 265c60c2
......@@ -4,18 +4,17 @@
# Common support (must be linked before board specific support)
obj-y += generic.o irq.o dma.o
obj-$(CONFIG_SA1111) += sa1111.o
# Specific board support
obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
# Support for blinky lights
leds-y := leds.o
leds-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o
leds-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
led-y := leds.o
led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o
led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
obj-$(CONFIG_LEDS) += $(leds-y)
obj-$(CONFIG_LEDS) += $(led-y)
# Misc features
obj-$(CONFIG_PM) += pm.o sleep.o
arch/arm/mach-pxa/generic.c
View file @ 265c60c2
......@@ -38,7 +38,7 @@
static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
/* Memory Frequency to Run Mode Frequency Multiplier (M) */
static unsigned char M_clk_mult[4] = { 0, 1, 2, 0 };
static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
/* Note: we store the value N * 2 here. */
......@@ -47,11 +47,12 @@ static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
/* Crystal clock */
#define BASE_CLK 3686400
/*
* Display what we were booted with.
* Get the clock frequency as reflected by CCCR and the turbo flag.
* We assume these values have been applied via a fcs.
* If info is not 0 we also display the current settings.
*/
static int __init pxa_display_clocks(void)
unsigned int get_clk_frequency_khz(int info)
{
unsigned long cccr, turbo;
unsigned int l, L, m, M, n2, N;
......@@ -67,20 +68,24 @@ static int __init pxa_display_clocks(void)
M = m * L;
N = n2 * M / 2;
L += 5000;
printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
L / 1000000, (L % 1000000) / 10000, l );
M += 5000;
printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
M / 1000000, (M % 1000000) / 10000, m );
N += 5000;
printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
(turbo & 1) ? "" : "in" );
return 0;
if(info)
{
L += 5000;
printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
L / 1000000, (L % 1000000) / 10000, l );
M += 5000;
printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
M / 1000000, (M % 1000000) / 10000, m );
N += 5000;
printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
(turbo & 1) ? "" : "in" );
}
return (turbo & 1) ? (N/1000) : (M/1000);
}
EXPORT_SYMBOL(get_clk_frequency_khz);
/*
* Return the current lclk requency in units of 10kHz
......@@ -132,5 +137,5 @@ static struct map_desc standard_io_desc[] __initdata = {
void __init pxa_map_io(void)
{
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
pxa_display_clocks();
get_clk_frequency_khz(1);
}
arch/arm/mach-pxa/irq.c
View file @ 265c60c2
......@@ -241,10 +241,4 @@ void __init pxa_init_irq(void)
/* Install handler for GPIO 2-80 edge detect interrupts */
set_irq_chip(IRQ_GPIO_2_80, &pxa_internal_chip);
set_irq_chained_handler(IRQ_GPIO_2_80, pxa_gpio_demux_handler);
/*
* We generally don't want the LCD IRQ being
* enabled as soon as we request it.
*/
set_irq_flags(IRQ_LCD, IRQF_VALID | IRQF_NOAUTOEN);
}
arch/arm/mach-pxa/leds.c
View file @ 265c60c2
......@@ -27,4 +27,4 @@ pxa_leds_init(void)
return 0;
}
__initcall(pxa_leds_init);
core_initcall(pxa_leds_init);
arch/arm/mach-pxa/lubbock.c
View file @ 265c60c2
......@@ -13,6 +13,7 @@
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/major.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
......@@ -31,7 +32,6 @@
#include <asm/hardware/sa1111.h>
#include "generic.h"
#include "sa1111.h"
static void lubbock_ack_irq(unsigned int irq)
{
......@@ -106,24 +106,16 @@ static void __init lubbock_init_irq(void)
static int __init lubbock_init(void)
{
int ret;
ret = sa1111_probe(LUBBOCK_SA1111_BASE);
if (ret)
return ret;
sa1111_wake();
sa1111_init_irq(LUBBOCK_SA1111_IRQ);
return 0;
return sa1111_init(0x10000000, LUBBOCK_SA1111_IRQ);
}
__initcall(lubbock_init);
subsys_initcall(lubbock_init);
static struct map_desc lubbock_io_desc[] __initdata = {
/* virtual physical length type */
{ 0xf0000000, 0x08000000, 0x00100000, MT_DEVICE }, /* CPLD */
{ 0xf1000000, 0x0c000000, 0x00100000, MT_DEVICE }, /* LAN91C96 IO */
{ 0xf1100000, 0x0e000000, 0x00100000, MT_DEVICE }, /* LAN91C96 Attr */
{ 0xf4000000, 0x10000000, 0x00400000, MT_DEVICE } /* SA1111 */
};
static void __init lubbock_map_io(void)
......
include/asm-arm/arch-pxa/bitfield.h 0 → 100644
View file @ 265c60c2
/*
* FILE bitfield.h
*
* Version 1.1
* Author Copyright (c) Marc A. Viredaz, 1998
* DEC Western Research Laboratory, Palo Alto, CA
* Date April 1998 (April 1997)
* System Advanced RISC Machine (ARM)
* Language C or ARM Assembly
* Purpose Definition of macros to operate on bit fields.
*/
#ifndef __BITFIELD_H
#define __BITFIELD_H
#ifndef __ASSEMBLY__
#define UData(Data) ((unsigned long) (Data))
#else
#define UData(Data) (Data)
#endif
/*
* MACRO: Fld
*
* Purpose
* The macro "Fld" encodes a bit field, given its size and its shift value
* with respect to bit 0.
*
* Note
* A more intuitive way to encode bit fields would have been to use their
* mask. However, extracting size and shift value information from a bit
* field's mask is cumbersome and might break the assembler (255-character
* line-size limit).
*
* Input
* Size Size of the bit field, in number of bits.
* Shft Shift value of the bit field with respect to bit 0.
*
* Output
* Fld Encoded bit field.
*/
#define Fld(Size, Shft) (((Size) << 16) + (Shft))
/*
* MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
*
* Purpose
* The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
* the size, shift value, mask, aligned mask, and first bit of a
* bit field.
*
* Input
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FSize Size of the bit field, in number of bits.
* FShft Shift value of the bit field with respect to bit 0.
* FMsk Mask for the bit field.
* FAlnMsk Mask for the bit field, aligned on bit 0.
* F1stBit First bit of the bit field.
*/
#define FSize(Field) ((Field) >> 16)
#define FShft(Field) ((Field) & 0x0000FFFF)
#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
#define F1stBit(Field) (UData (1) << FShft (Field))
/*
* MACRO: FInsrt
*
* Purpose
* The macro "FInsrt" inserts a value into a bit field by shifting the
* former appropriately.
*
* Input
* Value Bit-field value.
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FInsrt Bit-field value positioned appropriately.
*/
#define FInsrt(Value, Field) \
(UData (Value) << FShft (Field))
/*
* MACRO: FExtr
*
* Purpose
* The macro "FExtr" extracts the value of a bit field by masking and
* shifting it appropriately.
*
* Input
* Data Data containing the bit-field to be extracted.
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FExtr Bit-field value.
*/
#define FExtr(Data, Field) \
((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
#endif /* __BITFIELD_H */
include/asm-arm/arch-pxa/hardware.h
View file @ 265c60c2
......@@ -103,6 +103,5 @@ extern unsigned int get_lclk_frequency_10khz(void);
#include "lubbock.h"
#include "idp.h"
#include "cerf.h"
#endif /* _ASM_ARCH_HARDWARE_H */
include/asm-arm/arch-pxa/irqs.h
View file @ 265c60c2
......@@ -44,78 +44,86 @@
((i) - PXA_IRQ(32) + 2)
#define IRQ_TO_GPIO(i) ((i) - (((i) > IRQ_GPIO1) ? IRQ_GPIO(2) : IRQ_GPIO(0)))
#define NR_IRQS (IRQ_GPIO(80) + 1)
#if defined(CONFIG_SA1111)
#define IRQ_SA1111_START (IRQ_GPIO(80) + 1)
#define SA1111_IRQ(x) (IRQ_SA1111_START + (x))
#define IRQ_GPAIN0 SA1111_IRQ(0)
#define IRQ_GPAIN1 SA1111_IRQ(1)
#define IRQ_GPAIN2 SA1111_IRQ(2)
#define IRQ_GPAIN3 SA1111_IRQ(3)
#define IRQ_GPBIN0 SA1111_IRQ(4)
#define IRQ_GPBIN1 SA1111_IRQ(5)
#define IRQ_GPBIN2 SA1111_IRQ(6)
#define IRQ_GPBIN3 SA1111_IRQ(7)
#define IRQ_GPBIN4 SA1111_IRQ(8)
#define IRQ_GPBIN5 SA1111_IRQ(9)
#define IRQ_GPCIN0 SA1111_IRQ(10)
#define IRQ_GPCIN1 SA1111_IRQ(11)
#define IRQ_GPCIN2 SA1111_IRQ(12)
#define IRQ_GPCIN3 SA1111_IRQ(13)
#define IRQ_GPCIN4 SA1111_IRQ(14)
#define IRQ_GPCIN5 SA1111_IRQ(15)
#define IRQ_GPCIN6 SA1111_IRQ(16)
#define IRQ_GPCIN7 SA1111_IRQ(17)
#define IRQ_MSTXINT SA1111_IRQ(18)
#define IRQ_MSRXINT SA1111_IRQ(19)
#define IRQ_MSSTOPERRINT SA1111_IRQ(20)
#define IRQ_TPTXINT SA1111_IRQ(21)
#define IRQ_TPRXINT SA1111_IRQ(22)
#define IRQ_TPSTOPERRINT SA1111_IRQ(23)
#define SSPXMTINT SA1111_IRQ(24)
#define SSPRCVINT SA1111_IRQ(25)
#define SSPROR SA1111_IRQ(26)
#define AUDXMTDMADONEA SA1111_IRQ(32)
#define AUDRCVDMADONEA SA1111_IRQ(33)
#define AUDXMTDMADONEB SA1111_IRQ(34)
#define AUDRCVDMADONEB SA1111_IRQ(35)
#define AUDTFSR SA1111_IRQ(36)
#define AUDRFSR SA1111_IRQ(37)
#define AUDTUR SA1111_IRQ(38)
#define AUDROR SA1111_IRQ(39)
#define AUDDTS SA1111_IRQ(40)
#define AUDRDD SA1111_IRQ(41)
#define AUDSTO SA1111_IRQ(42)
#define USBPWR SA1111_IRQ(43)
#define NIRQHCIM SA1111_IRQ(44)
#define HCIBUFFACC SA1111_IRQ(45)
#define HCIRMTWKP SA1111_IRQ(46)
#define NHCIMFCIR SA1111_IRQ(47)
#define PORT_RESUME SA1111_IRQ(48)
#define S0_READY_NINT SA1111_IRQ(49)
#define S1_READY_NINT SA1111_IRQ(50)
#define S0_CD_VALID SA1111_IRQ(51)
#define S1_CD_VALID SA1111_IRQ(52)
#define S0_BVD1_STSCHG SA1111_IRQ(53)
#define S1_BVD1_STSCHG SA1111_IRQ(54)
#define SA1111_IRQ_MAX SA1111_IRQ(54)
#undef NR_IRQS
#define NR_IRQS (SA1111_IRQ_MAX + 1)
#endif // defined(CONFIG_SA1111)
/*
* The next 16 interrupts are for board specific purposes. Since
* the kernel can only run on one machine at a time, we can re-use
* these. If you need more, increase IRQ_BOARD_END, but keep it
* within sensible limits.
*/
#define IRQ_BOARD_START (IRQ_GPIO(80) + 1)
#define IRQ_BOARD_END (IRQ_BOARD_START + 16)
#define IRQ_SA1111_START (IRQ_BOARD_END)
#define IRQ_GPAIN0 (IRQ_BOARD_END + 0)
#define IRQ_GPAIN1 (IRQ_BOARD_END + 1)
#define IRQ_GPAIN2 (IRQ_BOARD_END + 2)
#define IRQ_GPAIN3 (IRQ_BOARD_END + 3)
#define IRQ_GPBIN0 (IRQ_BOARD_END + 4)
#define IRQ_GPBIN1 (IRQ_BOARD_END + 5)
#define IRQ_GPBIN2 (IRQ_BOARD_END + 6)
#define IRQ_GPBIN3 (IRQ_BOARD_END + 7)
#define IRQ_GPBIN4 (IRQ_BOARD_END + 8)
#define IRQ_GPBIN5 (IRQ_BOARD_END + 9)
#define IRQ_GPCIN0 (IRQ_BOARD_END + 10)
#define IRQ_GPCIN1 (IRQ_BOARD_END + 11)
#define IRQ_GPCIN2 (IRQ_BOARD_END + 12)
#define IRQ_GPCIN3 (IRQ_BOARD_END + 13)
#define IRQ_GPCIN4 (IRQ_BOARD_END + 14)
#define IRQ_GPCIN5 (IRQ_BOARD_END + 15)
#define IRQ_GPCIN6 (IRQ_BOARD_END + 16)
#define IRQ_GPCIN7 (IRQ_BOARD_END + 17)
#define IRQ_MSTXINT (IRQ_BOARD_END + 18)
#define IRQ_MSRXINT (IRQ_BOARD_END + 19)
#define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20)
#define IRQ_TPTXINT (IRQ_BOARD_END + 21)
#define IRQ_TPRXINT (IRQ_BOARD_END + 22)
#define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23)
#define SSPXMTINT (IRQ_BOARD_END + 24)
#define SSPRCVINT (IRQ_BOARD_END + 25)
#define SSPROR (IRQ_BOARD_END + 26)
#define AUDXMTDMADONEA (IRQ_BOARD_END + 32)
#define AUDRCVDMADONEA (IRQ_BOARD_END + 33)
#define AUDXMTDMADONEB (IRQ_BOARD_END + 34)
#define AUDRCVDMADONEB (IRQ_BOARD_END + 35)
#define AUDTFSR (IRQ_BOARD_END + 36)
#define AUDRFSR (IRQ_BOARD_END + 37)
#define AUDTUR (IRQ_BOARD_END + 38)
#define AUDROR (IRQ_BOARD_END + 39)
#define AUDDTS (IRQ_BOARD_END + 40)
#define AUDRDD (IRQ_BOARD_END + 41)
#define AUDSTO (IRQ_BOARD_END + 42)
#define IRQ_USBPWR (IRQ_BOARD_END + 43)
#define IRQ_HCIM (IRQ_BOARD_END + 44)
#define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45)
#define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46)
#define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47)
#define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48)
#define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49)
#define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50)
#define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51)
#define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52)
#define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53)
#define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54)
#if defined(CONFIG_ARCH_LUBBOCK) || defined(CONFIG_ARCH_PXA_IDP)
#if CONFIG_SA1111
#define LUBBOCK_IRQ(x) (SA1111_IRQ_MAX + 1 + (x))
/*
* Figure out the MAX IRQ number.
*
* If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
* Otherwise, we have the standard IRQs only.
*/
#ifdef CONFIG_SA1111
#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1)
#elif defined(CONFIG_ARCH_LUBBOCK)
#define NR_IRQS (IRQ_BOARD_END)
#else
#define LUBBOCK_IRQ(x) (IRQ_GPIO(80) + 1 + (x))
#define NR_IRQS (IRQ_BOARD_START)
#endif
/*
* Board specific IRQs. Define them here.
* Do not surround them with ifdefs.
*/
#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x))
#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0)
#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1)
#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2)
......@@ -123,10 +131,3 @@
#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4)
#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5)
#undef NR_IRQS
#define NR_IRQS (LUBBOCK_IRQ(5) + 1)
#endif // CONFIG_ARCH_LUBBOCK
include/asm-arm/arch-pxa/lubbock.h
View file @ 265c60c2
......@@ -13,7 +13,6 @@
#define LUBBOCK_FPGA_PHYS PXA_CS2_PHYS
#define LUBBOCK_FPGA_VIRT (0xf0000000) /* phys 0x08000000 */
#define LUBBOCK_ETH_BASE (0xf1000000) /* phys 0x0c000000 */
#define LUBBOCK_SA1111_BASE (0xf4000000) /* phys 0x10000000 */
#define LUB_P2V(x) ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT)
#define LUB_V2P(x) ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS)
......
include/asm-arm/arch-pxa/pxa-regs.h
View file @ 265c60c2
......@@ -380,32 +380,12 @@ typedef void (*ExcpHndlr) (void) ;
/*
* IrSR (Infrared Selection Register)
*/
#define IrSR_OFFSET 0x20
#define IrSR_RXPL_NEG_IS_ZERO (1<<4)
#define IrSR_RXPL_POS_IS_ZERO 0x0
#define IrSR_TXPL_NEG_IS_ZERO (1<<3)
#define IrSR_TXPL_POS_IS_ZERO 0x0
#define IrSR_XMODE_PULSE_1_6 (1<<2)
#define IrSR_XMODE_PULSE_3_16 0x0
#define IrSR_RCVEIR_IR_MODE (1<<1)
#define IrSR_RCVEIR_UART_MODE 0x0
#define IrSR_XMITIR_IR_MODE (1<<0)
#define IrSR_XMITIR_UART_MODE 0x0
#define IrSR_IR_RECEIVE_ON (\
IrSR_RXPL_NEG_IS_ZERO | \
IrSR_TXPL_POS_IS_ZERO | \
IrSR_XMODE_PULSE_3_16 | \
IrSR_RCVEIR_IR_MODE | \
IrSR_XMITIR_UART_MODE)
#define IrSR_IR_TRANSMIT_ON (\
IrSR_RXPL_NEG_IS_ZERO | \
IrSR_TXPL_POS_IS_ZERO | \
IrSR_XMODE_PULSE_3_16 | \
IrSR_RCVEIR_UART_MODE | \
IrSR_XMITIR_IR_MODE)
#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
/*
* I2C registers
......@@ -417,53 +397,49 @@ typedef void (*ExcpHndlr) (void) ;
#define ISR __REG(0x40301698) /* I2C Status Register - ISR */
#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
/* ----- Control register bits ---------------------------------------- */
#define ICR_START 0x1 /* start bit */
#define ICR_STOP 0x2 /* stop bit */
#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
#define ICR_TB 0x8 /* transfer byte bit */
#define ICR_MA 0x10 /* master abort */
#define ICR_SCLE 0x20 /* master clock enable */
#define ICR_IUE 0x40 /* unit enable */
#define ICR_GCD 0x80 /* general call disable */
#define ICR_ITEIE 0x100 /* enable tx interrupts */
#define ICR_IRFIE 0x200 /* enable rx interrupts */
#define ICR_BEIE 0x400 /* enable bus error ints */
#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
#define ICR_SADIE 0x2000 /* slave address detected int enable */
#define ICR_UR 0x4000 /* unit reset */
/* ----- Status register bits ----------------------------------------- */
#define ISR_RWM 0x1 /* read/write mode */
#define ISR_ACKNAK 0x2 /* ack/nak status */
#define ISR_UB 0x4 /* unit busy */
#define ISR_IBB 0x8 /* bus busy */
#define ISR_SSD 0x10 /* slave stop detected */
#define ISR_ALD 0x20 /* arbitration loss detected */
#define ISR_ITE 0x40 /* tx buffer empty */
#define ISR_IRF 0x80 /* rx buffer full */
#define ISR_GCAD 0x100 /* general call address detected */
#define ISR_SAD 0x200 /* slave address detected */
#define ISR_BED 0x400 /* bus error no ACK/NAK */
#define ICR_START (1 << 0) /* start bit */
#define ICR_STOP (1 << 1) /* stop bit */
#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
#define ICR_TB (1 << 3) /* transfer byte bit */
#define ICR_MA (1 << 4) /* master abort */
#define ICR_SCLE (1 << 5) /* master clock enable */
#define ICR_IUE (1 << 6) /* unit enable */
#define ICR_GCD (1 << 7) /* general call disable */
#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
#define ICR_BEIE (1 << 10) /* enable bus error ints */
#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
#define ICR_SADIE (1 << 13) /* slave address detected int enable */
#define ICR_UR (1 << 14) /* unit reset */
#define ISR_RWM (1 << 0) /* read/write mode */
#define ISR_ACKNAK (1 << 1) /* ack/nak status */
#define ISR_UB (1 << 2) /* unit busy */
#define ISR_IBB (1 << 3) /* bus busy */
#define ISR_SSD (1 << 4) /* slave stop detected */
#define ISR_ALD (1 << 5) /* arbitration loss detected */
#define ISR_ITE (1 << 6) /* tx buffer empty */
#define ISR_IRF (1 << 7) /* rx buffer full */
#define ISR_GCAD (1 << 8) /* general call address detected */
#define ISR_SAD (1 << 9) /* slave address detected */
#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
/*
* Serial Audio Controller
*/
/* FIXME the audio defines collide w/ the SA1111 defines. I don't like these
* short defines because there is too much chance of namespace collision */
//#define SACR0 __REG(0x40400000) /* Global Control Register */
//#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
//#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
//#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
//#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
//#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
//#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
/* FIXME: This clash with SA1111 defines */
#ifndef CONFIG_SA1111
#define SACR0 __REG(0x40400000) /* Global Control Register */
#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
#endif
/*
......@@ -714,6 +690,30 @@ typedef void (*ExcpHndlr) (void) ;
#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
#define ICCR0_AME (1 << 7) /* Adress match enable */
#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
#define ICCR0_RXE (1 << 4) /* Receive enable */
#define ICCR0_TXE (1 << 3) /* Transmit enable */
#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
#define ICCR0_LBM (1 << 1) /* Loopback mode */
#define ICCR0_ITR (1 << 0) /* IrDA transmission */
#define ICSR0_FRE (1 << 5) /* Framing error */
#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
#define ICSR0_RAB (1 << 2) /* Receiver abort */
#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
#define ICSR1_CRE (1 << 5) /* CRC error */
#define ICSR1_EOF (1 << 4) /* End of frame */
#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
/*
* Real Time Clock
......@@ -1171,19 +1171,105 @@ typedef void (*ExcpHndlr) (void) ;
#define LCCR0_BM (1 << 20) /* Branch mask */
#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
(((Pixel) - 1) << FShft (LCCR1_PPL))
#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
/* pulse Width [1..64 Tpix] */ \
(((Tpix) - 1) << FShft (LCCR1_HSW))
#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
/* count - 1 [Tpix] */
#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
/* [1..256 Tpix] */ \
(((Tpix) - 1) << FShft (LCCR1_ELW))
#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
/* Wait count - 1 [Tpix] */
#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
/* [1..256 Tpix] */ \
(((Tpix) - 1) << FShft (LCCR1_BLW))
#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
(((Line) - 1) << FShft (LCCR2_LPP))
#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
/* Width - 1 [Tln] (L_FCLK) */
#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
/* Width [1..64 Tln] */ \
(((Tln) - 1) << FShft (LCCR2_VSW))
#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
/* count [Tln] */
#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
/* [0..255 Tln] */ \
((Tln) << FShft (LCCR2_EFW))
#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
/* Wait count [Tln] */
#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
/* [0..255 Tln] */ \
((Tln) << FShft (LCCR2_BFW))
#if 0
#define LCCR3_PCD (0xff) /* Pixel clock divisor */
#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */
#define LCCR3_ACB_S 8
#endif
#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
#define LCCR3_API_S 16
#define LCCR3_VSP (1 << 20) /* vertical sync polarity */
#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
#define LCCR3_PCP (1 << 22) /* pixel clock polarity */
#define LCCR3_OEP (1 << 23) /* output enable polarity */
#if 0
#define LCCR3_BPP (7 << 24) /* bits per pixel */
#define LCCR3_BPP_S 24
#endif
#define LCCR3_DPC (1 << 27) /* double pixel clock mode */
#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \
(((Div) << FShft (LCCR3_PCD)))
#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \
(((Bpp) << FShft (LCCR3_BPP)))
#define LCCR3_ACB Fld (8, 8) /* AC Bias */
#define LCCR3_Acb(Acb) /* BAC Bias */ \
(((Acb) << FShft (LCCR3_ACB)))
#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
/* pulse active High */
#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
/* active High */
#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
/* active Low */
#define LCSR_LDD (1 << 0) /* LCD Disable Done */
#define LCSR_SOF (1 << 1) /* Start of frame */
#define LCSR_BER (1 << 2) /* Bus error */
#define LCSR_ABC (1 << 3) /* AC Bias count */
#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
#define LCSR_OU (1 << 6) /* output FIFO underrun */
#define LCSR_QD (1 << 7) /* quick disable */
#define LCSR_EOF (1 << 8) /* end of frame */
#define LCSR_BS (1 << 9) /* branch status */
#define LCSR_SINT (1 << 10) /* subsequent interrupt */
#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
#define LCSR_LDD (1 << 0) /* LCD Disable Done */
#define LCSR_SOF (1 << 1) /* Start of frame */
#define LCSR_BER (1 << 2) /* Bus error */
......
include/asm-arm/arch-pxa/system.h
View file @ 265c60c2
......@@ -27,7 +27,7 @@ static inline void arch_reset(char mode)
/* Initialize the watchdog and let it fire */
OWER = OWER_WME;
OSSR = OSSR_M3;
OSMR3 = OSCR + 36864; /* ... in 10 ms */
OSMR3 = OSCR + 368640; /* ... in 100 ms */
}
}
include/asm-arm/arch-pxa/time.h
View file @ 265c60c2
......@@ -42,7 +42,7 @@ static unsigned long pxa_gettimeoffset (void)
elapsed = LATCH - ticks_to_match;
/* Now convert them to usec */
usec = (unsigned long)(elapsed*tick)/LATCH;
usec = (unsigned long)(elapsed * (tick_nsec / 1000))/LATCH;
return usec;
}
......@@ -52,6 +52,8 @@ static void pxa_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
long flags;
int next_match;
do_profile(regs);
/* Loop until we get ahead of the free running timer.
* This ensures an exact clock tick count and time accuracy.
* IRQs are disabled inside the loop to ensure coherence between
......
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