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Commit 26e34d2d authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'imx-drm-next-2016-09-19' of git://git.pengutronix.de/git/pza/linux into drm-next 

imx-drm active plane reconfiguration, cleanup, FSU/IC/IRT/VDIC support

- add active plane reconfiguration support (v4),
  use the atomic_disable callback
- stop calling disable_plane manually in the plane destroy path
- let mode cleanup destroy mode objects on driver unbind
- drop deprecated load/unload drm_driver ops
- add exclusive fence to plane state, so the atomic helper can
  wait on them, remove the open-coded fence wait from imx-drm
- add low level deinterlacer (VDIC) support
- add support for channel linking via the frame synchronisation unit (FSU)
- add queued image conversion support for memory-to-memory scaling, rotation,
  and color space conversion, using IC and IRT.

* tag 'imx-drm-next-2016-09-19' of git://git.pengutronix.de/git/pza/linux:
  gpu: ipu-v3: Add queued image conversion support
  gpu: ipu-v3: Add ipu_rot_mode_is_irt()
  gpu: ipu-v3: fix a possible NULL dereference
  drm/imx: parallel-display: detach bridge or panel on unbind
  drm/imx: imx-ldb: detach bridge on unbind
  drm/imx: imx-ldb: detach panel on unbind
  gpu: ipu-v3: Add FSU channel linking support
  gpu: ipu-v3: Add Video Deinterlacer unit
  drm/imx: add exclusive fence to plane state
  drm/imx: fold ipu_plane_disable into ipu_disable_plane
  drm/imx: don't destroy mode objects manually on driver unbind
  drm/imx: drop deprecated load/unload drm_driver ops
  drm/imx: don't call disable_plane in plane destroy path
  drm/imx: Add active plane reconfiguration support
  drm/imx: Use DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET flag
  drm/imx: ipuv3-crtc: Use the callback ->atomic_disable instead of ->disable
  gpu: ipu-v3: Do not wait for DMFC FIFO to clear when disabling DMFC channel
parents b81a6179 cd98e85a
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Showing with 2612 additions and 230 deletions
drivers/gpu/drm/bridge/dw-hdmi.c
View file @ 26e34d2d
......@@ -1813,9 +1813,6 @@ void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
/* Disable all interrupts */
hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
hdmi->connector.funcs->destroy(&hdmi->connector);
hdmi->encoder->funcs->destroy(hdmi->encoder);
clk_disable_unprepare(hdmi->iahb_clk);
clk_disable_unprepare(hdmi->isfr_clk);
i2c_put_adapter(hdmi->ddc);
......
drivers/gpu/drm/imx/imx-drm-core.c
View file @ 26e34d2d
......@@ -64,25 +64,6 @@ static void imx_drm_driver_lastclose(struct drm_device *drm)
drm_fbdev_cma_restore_mode(imxdrm->fbhelper);
}
static int imx_drm_driver_unload(struct drm_device *drm)
{
struct imx_drm_device *imxdrm = drm->dev_private;
drm_kms_helper_poll_fini(drm);
if (imxdrm->fbhelper)
drm_fbdev_cma_fini(imxdrm->fbhelper);
component_unbind_all(drm->dev, drm);
drm_vblank_cleanup(drm);
drm_mode_config_cleanup(drm);
platform_set_drvdata(drm->platformdev, NULL);
return 0;
}
static int imx_drm_enable_vblank(struct drm_device *drm, unsigned int pipe)
{
struct imx_drm_device *imxdrm = drm->dev_private;
......@@ -146,55 +127,73 @@ static void imx_drm_output_poll_changed(struct drm_device *drm)
drm_fbdev_cma_hotplug_event(imxdrm->fbhelper);
}
static int imx_drm_atomic_check(struct drm_device *dev,
struct drm_atomic_state *state)
{
int ret;
ret = drm_atomic_helper_check_modeset(dev, state);
if (ret)
return ret;
ret = drm_atomic_helper_check_planes(dev, state);
if (ret)
return ret;
/*
* Check modeset again in case crtc_state->mode_changed is
* updated in plane's ->atomic_check callback.
*/
ret = drm_atomic_helper_check_modeset(dev, state);
if (ret)
return ret;
return ret;
}
static int imx_drm_atomic_commit(struct drm_device *dev,
struct drm_atomic_state *state,
bool nonblock)
{
struct drm_plane_state *plane_state;
struct drm_plane *plane;
struct dma_buf *dma_buf;
int i;
/*
* If the plane fb has an dma-buf attached, fish out the exclusive
* fence for the atomic helper to wait on.
*/
for_each_plane_in_state(state, plane, plane_state, i) {
if ((plane->state->fb != plane_state->fb) && plane_state->fb) {
dma_buf = drm_fb_cma_get_gem_obj(plane_state->fb,
0)->base.dma_buf;
if (!dma_buf)
continue;
plane_state->fence =
reservation_object_get_excl_rcu(dma_buf->resv);
}
}
return drm_atomic_helper_commit(dev, state, nonblock);
}
static const struct drm_mode_config_funcs imx_drm_mode_config_funcs = {
.fb_create = drm_fb_cma_create,
.output_poll_changed = imx_drm_output_poll_changed,
.atomic_check = drm_atomic_helper_check,
.atomic_commit = drm_atomic_helper_commit,
.atomic_check = imx_drm_atomic_check,
.atomic_commit = imx_drm_atomic_commit,
};
static void imx_drm_atomic_commit_tail(struct drm_atomic_state *state)
{
struct drm_device *dev = state->dev;
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
struct drm_plane_state *plane_state;
struct drm_gem_cma_object *cma_obj;
struct fence *excl;
unsigned shared_count;
struct fence **shared;
unsigned int i, j;
int ret;
/* Wait for fences. */
for_each_crtc_in_state(state, crtc, crtc_state, i) {
plane_state = crtc->primary->state;
if (plane_state->fb) {
cma_obj = drm_fb_cma_get_gem_obj(plane_state->fb, 0);
if (cma_obj->base.dma_buf) {
ret = reservation_object_get_fences_rcu(
cma_obj->base.dma_buf->resv, &excl,
&shared_count, &shared);
if (unlikely(ret))
DRM_ERROR("failed to get fences "
"for buffer\n");
if (excl) {
fence_wait(excl, false);
fence_put(excl);
}
for (j = 0; j < shared_count; i++) {
fence_wait(shared[j], false);
fence_put(shared[j]);
}
}
}
}
drm_atomic_helper_commit_modeset_disables(dev, state);
drm_atomic_helper_commit_planes(dev, state,
DRM_PLANE_COMMIT_ACTIVE_ONLY);
DRM_PLANE_COMMIT_ACTIVE_ONLY |
DRM_PLANE_COMMIT_NO_DISABLE_AFTER_MODESET);
drm_atomic_helper_commit_modeset_enables(dev, state);
......@@ -209,111 +208,6 @@ static struct drm_mode_config_helper_funcs imx_drm_mode_config_helpers = {
.atomic_commit_tail = imx_drm_atomic_commit_tail,
};
/*
* Main DRM initialisation. This binds, initialises and registers
* with DRM the subcomponents of the driver.
*/
static int imx_drm_driver_load(struct drm_device *drm, unsigned long flags)
{
struct imx_drm_device *imxdrm;
struct drm_connector *connector;
int ret;
imxdrm = devm_kzalloc(drm->dev, sizeof(*imxdrm), GFP_KERNEL);
if (!imxdrm)
return -ENOMEM;
imxdrm->drm = drm;
drm->dev_private = imxdrm;
/*
* enable drm irq mode.
* - with irq_enabled = true, we can use the vblank feature.
*
* P.S. note that we wouldn't use drm irq handler but
* just specific driver own one instead because
* drm framework supports only one irq handler and
* drivers can well take care of their interrupts
*/
drm->irq_enabled = true;
/*
* set max width and height as default value(4096x4096).
* this value would be used to check framebuffer size limitation
* at drm_mode_addfb().
*/
drm->mode_config.min_width = 64;
drm->mode_config.min_height = 64;
drm->mode_config.max_width = 4096;
drm->mode_config.max_height = 4096;
drm->mode_config.funcs = &imx_drm_mode_config_funcs;
drm->mode_config.helper_private = &imx_drm_mode_config_helpers;
drm_mode_config_init(drm);
ret = drm_vblank_init(drm, MAX_CRTC);
if (ret)
goto err_kms;
platform_set_drvdata(drm->platformdev, drm);
/* Now try and bind all our sub-components */
ret = component_bind_all(drm->dev, drm);
if (ret)
goto err_vblank;
/*
* All components are now added, we can publish the connector sysfs
* entries to userspace. This will generate hotplug events and so
* userspace will expect to be able to access DRM at this point.
*/
list_for_each_entry(connector, &drm->mode_config.connector_list, head) {
ret = drm_connector_register(connector);
if (ret) {
dev_err(drm->dev,
"[CONNECTOR:%d:%s] drm_connector_register failed: %d\n",
connector->base.id,
connector->name, ret);
goto err_unbind;
}
}
drm_mode_config_reset(drm);
/*
* All components are now initialised, so setup the fb helper.
* The fb helper takes copies of key hardware information, so the
* crtcs/connectors/encoders must not change after this point.
*/
#if IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION)
if (legacyfb_depth != 16 && legacyfb_depth != 32) {
dev_warn(drm->dev, "Invalid legacyfb_depth. Defaulting to 16bpp\n");
legacyfb_depth = 16;
}
imxdrm->fbhelper = drm_fbdev_cma_init(drm, legacyfb_depth,
drm->mode_config.num_crtc, MAX_CRTC);
if (IS_ERR(imxdrm->fbhelper)) {
ret = PTR_ERR(imxdrm->fbhelper);
imxdrm->fbhelper = NULL;
goto err_unbind;
}
#endif
drm_kms_helper_poll_init(drm);
return 0;
err_unbind:
component_unbind_all(drm->dev, drm);
err_vblank:
drm_vblank_cleanup(drm);
err_kms:
drm_mode_config_cleanup(drm);
return ret;
}
/*
* imx_drm_add_crtc - add a new crtc
*/
......@@ -406,8 +300,6 @@ static const struct drm_ioctl_desc imx_drm_ioctls[] = {
static struct drm_driver imx_drm_driver = {
.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
DRIVER_ATOMIC,
.load = imx_drm_driver_load,
.unload = imx_drm_driver_unload,
.lastclose = imx_drm_driver_lastclose,
.gem_free_object_unlocked = drm_gem_cma_free_object,
.gem_vm_ops = &drm_gem_cma_vm_ops,
......@@ -460,12 +352,122 @@ static int compare_of(struct device *dev, void *data)
static int imx_drm_bind(struct device *dev)
{
return drm_platform_init(&imx_drm_driver, to_platform_device(dev));
struct drm_device *drm;
struct imx_drm_device *imxdrm;
int ret;
drm = drm_dev_alloc(&imx_drm_driver, dev);
if (!drm)
return -ENOMEM;
imxdrm = devm_kzalloc(dev, sizeof(*imxdrm), GFP_KERNEL);
if (!imxdrm) {
ret = -ENOMEM;
goto err_unref;
}
imxdrm->drm = drm;
drm->dev_private = imxdrm;
/*
* enable drm irq mode.
* - with irq_enabled = true, we can use the vblank feature.
*
* P.S. note that we wouldn't use drm irq handler but
* just specific driver own one instead because
* drm framework supports only one irq handler and
* drivers can well take care of their interrupts
*/
drm->irq_enabled = true;
/*
* set max width and height as default value(4096x4096).
* this value would be used to check framebuffer size limitation
* at drm_mode_addfb().
*/
drm->mode_config.min_width = 64;
drm->mode_config.min_height = 64;
drm->mode_config.max_width = 4096;
drm->mode_config.max_height = 4096;
drm->mode_config.funcs = &imx_drm_mode_config_funcs;
drm->mode_config.helper_private = &imx_drm_mode_config_helpers;
drm_mode_config_init(drm);
ret = drm_vblank_init(drm, MAX_CRTC);
if (ret)
goto err_kms;
dev_set_drvdata(dev, drm);
/* Now try and bind all our sub-components */
ret = component_bind_all(dev, drm);
if (ret)
goto err_vblank;
drm_mode_config_reset(drm);
/*
* All components are now initialised, so setup the fb helper.
* The fb helper takes copies of key hardware information, so the
* crtcs/connectors/encoders must not change after this point.
*/
#if IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION)
if (legacyfb_depth != 16 && legacyfb_depth != 32) {
dev_warn(dev, "Invalid legacyfb_depth. Defaulting to 16bpp\n");
legacyfb_depth = 16;
}
imxdrm->fbhelper = drm_fbdev_cma_init(drm, legacyfb_depth,
drm->mode_config.num_crtc, MAX_CRTC);
if (IS_ERR(imxdrm->fbhelper)) {
ret = PTR_ERR(imxdrm->fbhelper);
imxdrm->fbhelper = NULL;
goto err_unbind;
}
#endif
drm_kms_helper_poll_init(drm);
ret = drm_dev_register(drm, 0);
if (ret)
goto err_fbhelper;
return 0;
err_fbhelper:
drm_kms_helper_poll_fini(drm);
if (imxdrm->fbhelper)
drm_fbdev_cma_fini(imxdrm->fbhelper);
err_unbind:
component_unbind_all(drm->dev, drm);
err_vblank:
drm_vblank_cleanup(drm);
err_kms:
drm_mode_config_cleanup(drm);
err_unref:
drm_dev_unref(drm);
return ret;
}
static void imx_drm_unbind(struct device *dev)
{
drm_put_dev(dev_get_drvdata(dev));
struct drm_device *drm = dev_get_drvdata(dev);
struct imx_drm_device *imxdrm = drm->dev_private;
drm_dev_unregister(drm);
drm_kms_helper_poll_fini(drm);
if (imxdrm->fbhelper)
drm_fbdev_cma_fini(imxdrm->fbhelper);
drm_mode_config_cleanup(drm);
component_unbind_all(drm->dev, drm);
dev_set_drvdata(dev, NULL);
drm_dev_unref(drm);
}
static const struct component_master_ops imx_drm_ops = {
......
drivers/gpu/drm/imx/imx-ldb.c
View file @ 26e34d2d
......@@ -757,11 +757,10 @@ static void imx_ldb_unbind(struct device *dev, struct device *master,
for (i = 0; i < 2; i++) {
struct imx_ldb_channel *channel = &imx_ldb->channel[i];
if (!channel->connector.funcs)
continue;
channel->connector.funcs->destroy(&channel->connector);
channel->encoder.funcs->destroy(&channel->encoder);
if (channel->bridge)
drm_bridge_detach(channel->bridge);
if (channel->panel)
drm_panel_detach(channel->panel);
kfree(channel->edid);
i2c_put_adapter(channel->ddc);
......
drivers/gpu/drm/imx/imx-tve.c
View file @ 26e34d2d
......@@ -685,9 +685,6 @@ static void imx_tve_unbind(struct device *dev, struct device *master,
{
struct imx_tve *tve = dev_get_drvdata(dev);
tve->connector.funcs->destroy(&tve->connector);
tve->encoder.funcs->destroy(&tve->encoder);
if (!IS_ERR(tve->dac_reg))
regulator_disable(tve->dac_reg);
}
......
drivers/gpu/drm/imx/ipuv3-crtc.c
View file @ 26e34d2d
......@@ -60,7 +60,8 @@ static void ipu_crtc_enable(struct drm_crtc *crtc)
ipu_di_enable(ipu_crtc->di);
}
static void ipu_crtc_disable(struct drm_crtc *crtc)
static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
......@@ -75,6 +76,9 @@ static void ipu_crtc_disable(struct drm_crtc *crtc)
crtc->state->event = NULL;
}
spin_unlock_irq(&crtc->dev->event_lock);
/* always disable planes on the CRTC */
drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, true);
}
static void imx_drm_crtc_reset(struct drm_crtc *crtc)
......@@ -120,9 +124,14 @@ static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
kfree(to_imx_crtc_state(state));
}
static void imx_drm_crtc_destroy(struct drm_crtc *crtc)
{
imx_drm_remove_crtc(to_ipu_crtc(crtc)->imx_crtc);
}
static const struct drm_crtc_funcs ipu_crtc_funcs = {
.set_config = drm_atomic_helper_set_config,
.destroy = drm_crtc_cleanup,
.destroy = imx_drm_crtc_destroy,
.page_flip = drm_atomic_helper_page_flip,
.reset = imx_drm_crtc_reset,
.atomic_duplicate_state = imx_drm_crtc_duplicate_state,
......@@ -241,7 +250,7 @@ static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
.mode_set_nofb = ipu_crtc_mode_set_nofb,
.atomic_check = ipu_crtc_atomic_check,
.atomic_begin = ipu_crtc_atomic_begin,
.disable = ipu_crtc_disable,
.atomic_disable = ipu_crtc_atomic_disable,
.enable = ipu_crtc_enable,
};
......@@ -409,8 +418,6 @@ static void ipu_drm_unbind(struct device *dev, struct device *master,
{
struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
imx_drm_remove_crtc(ipu_crtc->imx_crtc);
ipu_put_resources(ipu_crtc);
if (ipu_crtc->plane[1])
ipu_plane_put_resources(ipu_crtc->plane[1]);
......
drivers/gpu/drm/imx/ipuv3-plane.c
View file @ 26e34d2d
......@@ -213,8 +213,12 @@ static void ipu_plane_enable(struct ipu_plane *ipu_plane)
ipu_dp_enable_channel(ipu_plane->dp);
}
static void ipu_plane_disable(struct ipu_plane *ipu_plane)
static int ipu_disable_plane(struct drm_plane *plane)
{
struct ipu_plane *ipu_plane = to_ipu_plane(plane);
DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
if (ipu_plane->dp)
......@@ -223,15 +227,6 @@ static void ipu_plane_disable(struct ipu_plane *ipu_plane)
ipu_dmfc_disable_channel(ipu_plane->dmfc);
if (ipu_plane->dp)
ipu_dp_disable(ipu_plane->ipu);
}
static int ipu_disable_plane(struct drm_plane *plane)
{
struct ipu_plane *ipu_plane = to_ipu_plane(plane);
DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
ipu_plane_disable(ipu_plane);
return 0;
}
......@@ -242,7 +237,6 @@ static void ipu_plane_destroy(struct drm_plane *plane)
DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
ipu_disable_plane(plane);
drm_plane_cleanup(plane);
kfree(ipu_plane);
}
......@@ -319,13 +313,16 @@ static int ipu_plane_atomic_check(struct drm_plane *plane,
return -EINVAL;
/*
* since we cannot touch active IDMAC channels, we do not support
* resizing the enabled plane or changing its format
* We support resizing active plane or changing its format by
* forcing CRTC mode change in plane's ->atomic_check callback
* and disabling all affected active planes in CRTC's ->atomic_disable
* callback. The planes will be reenabled in plane's ->atomic_update
* callback.
*/
if (old_fb && (state->src_w != old_state->src_w ||
state->src_h != old_state->src_h ||
fb->pixel_format != old_fb->pixel_format))
return -EINVAL;
crtc_state->mode_changed = true;
eba = drm_plane_state_to_eba(state);
......@@ -336,7 +333,7 @@ static int ipu_plane_atomic_check(struct drm_plane *plane,
return -EINVAL;
if (old_fb && fb->pitches[0] != old_fb->pitches[0])
return -EINVAL;
crtc_state->mode_changed = true;
switch (fb->pixel_format) {
case DRM_FORMAT_YUV420:
......@@ -372,7 +369,7 @@ static int ipu_plane_atomic_check(struct drm_plane *plane,
return -EINVAL;
if (old_fb && old_fb->pitches[1] != fb->pitches[1])
return -EINVAL;
crtc_state->mode_changed = true;
}
return 0;
......@@ -392,9 +389,13 @@ static void ipu_plane_atomic_update(struct drm_plane *plane,
enum ipu_color_space ics;
if (old_state->fb) {
struct drm_crtc_state *crtc_state = state->crtc->state;
if (!drm_atomic_crtc_needs_modeset(crtc_state)) {
ipu_plane_atomic_set_base(ipu_plane, old_state);
return;
}
}
switch (ipu_plane->dp_flow) {
case IPU_DP_FLOW_SYNC_BG:
......
drivers/gpu/drm/imx/parallel-display.c
View file @ 26e34d2d
......@@ -293,8 +293,10 @@ static void imx_pd_unbind(struct device *dev, struct device *master,
{
struct imx_parallel_display *imxpd = dev_get_drvdata(dev);
imxpd->encoder.funcs->destroy(&imxpd->encoder);
imxpd->connector.funcs->destroy(&imxpd->connector);
if (imxpd->bridge)
drm_bridge_detach(imxpd->bridge);
if (imxpd->panel)
drm_panel_detach(imxpd->panel);
kfree(imxpd->edid);
}
......
drivers/gpu/ipu-v3/Makefile
View file @ 26e34d2d
obj-$(CONFIG_IMX_IPUV3_CORE) += imx-ipu-v3.o
imx-ipu-v3-objs := ipu-common.o ipu-cpmem.o ipu-csi.o ipu-dc.o ipu-di.o \
ipu-dp.o ipu-dmfc.o ipu-ic.o ipu-smfc.o
ipu-dp.o ipu-dmfc.o ipu-ic.o ipu-image-convert.o \
ipu-smfc.o ipu-vdi.o
drivers/gpu/ipu-v3/ipu-common.c
View file @ 26e34d2d
......@@ -730,6 +730,137 @@ void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
}
EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
/* Frame Synchronization Unit Channel Linking */
struct fsu_link_reg_info {
int chno;
u32 reg;
u32 mask;
u32 val;
};
struct fsu_link_info {
struct fsu_link_reg_info src;
struct fsu_link_reg_info sink;
};
static const struct fsu_link_info fsu_link_info[] = {
{
.src = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2,
FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC },
.sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1,
FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC },
}, {
.src = { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2,
FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF },
.sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1,
FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF },
}, {
.src = { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2,
FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP },
.sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1,
FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP },
}, {
.src = { IPUV3_CHANNEL_CSI_DIRECT, 0 },
.sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1,
FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT },
},
};
static const struct fsu_link_info *find_fsu_link_info(int src, int sink)
{
int i;
for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) {
if (src == fsu_link_info[i].src.chno &&
sink == fsu_link_info[i].sink.chno)
return &fsu_link_info[i];
}
return NULL;
}
/*
* Links a source channel to a sink channel in the FSU.
*/
int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch)
{
const struct fsu_link_info *link;
u32 src_reg, sink_reg;
unsigned long flags;
link = find_fsu_link_info(src_ch, sink_ch);
if (!link)
return -EINVAL;
spin_lock_irqsave(&ipu->lock, flags);
if (link->src.mask) {
src_reg = ipu_cm_read(ipu, link->src.reg);
src_reg &= ~link->src.mask;
src_reg |= link->src.val;
ipu_cm_write(ipu, src_reg, link->src.reg);
}
if (link->sink.mask) {
sink_reg = ipu_cm_read(ipu, link->sink.reg);
sink_reg &= ~link->sink.mask;
sink_reg |= link->sink.val;
ipu_cm_write(ipu, sink_reg, link->sink.reg);
}
spin_unlock_irqrestore(&ipu->lock, flags);
return 0;
}
EXPORT_SYMBOL_GPL(ipu_fsu_link);
/*
* Unlinks source and sink channels in the FSU.
*/
int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch)
{
const struct fsu_link_info *link;
u32 src_reg, sink_reg;
unsigned long flags;
link = find_fsu_link_info(src_ch, sink_ch);
if (!link)
return -EINVAL;
spin_lock_irqsave(&ipu->lock, flags);
if (link->src.mask) {
src_reg = ipu_cm_read(ipu, link->src.reg);
src_reg &= ~link->src.mask;
ipu_cm_write(ipu, src_reg, link->src.reg);
}
if (link->sink.mask) {
sink_reg = ipu_cm_read(ipu, link->sink.reg);
sink_reg &= ~link->sink.mask;
ipu_cm_write(ipu, sink_reg, link->sink.reg);
}
spin_unlock_irqrestore(&ipu->lock, flags);
return 0;
}
EXPORT_SYMBOL_GPL(ipu_fsu_unlink);
/* Link IDMAC channels in the FSU */
int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink)
{
return ipu_fsu_link(src->ipu, src->num, sink->num);
}
EXPORT_SYMBOL_GPL(ipu_idmac_link);
/* Unlink IDMAC channels in the FSU */
int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink)
{
return ipu_fsu_unlink(src->ipu, src->num, sink->num);
}
EXPORT_SYMBOL_GPL(ipu_idmac_unlink);
struct ipu_devtype {
const char *name;
unsigned long cm_ofs;
......@@ -839,6 +970,20 @@ static int ipu_submodules_init(struct ipu_soc *ipu,
goto err_ic;
}
ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs,
IPU_CONF_VDI_EN | IPU_CONF_ISP_EN |
IPU_CONF_IC_INPUT);
if (ret) {
unit = "vdi";
goto err_vdi;
}
ret = ipu_image_convert_init(ipu, dev);
if (ret) {
unit = "image_convert";
goto err_image_convert;
}
ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
IPU_CONF_DI0_EN, ipu_clk);
if (ret) {
......@@ -893,6 +1038,10 @@ static int ipu_submodules_init(struct ipu_soc *ipu,
err_di_1:
ipu_di_exit(ipu, 0);
err_di_0:
ipu_image_convert_exit(ipu);
err_image_convert:
ipu_vdi_exit(ipu);
err_vdi:
ipu_ic_exit(ipu);
err_ic:
ipu_csi_exit(ipu, 1);
......@@ -977,6 +1126,8 @@ static void ipu_submodules_exit(struct ipu_soc *ipu)
ipu_dc_exit(ipu);
ipu_di_exit(ipu, 1);
ipu_di_exit(ipu, 0);
ipu_image_convert_exit(ipu);
ipu_vdi_exit(ipu);
ipu_ic_exit(ipu);
ipu_csi_exit(ipu, 1);
ipu_csi_exit(ipu, 0);
......@@ -1213,8 +1364,6 @@ EXPORT_SYMBOL_GPL(ipu_dump);
static int ipu_probe(struct platform_device *pdev)
{
const struct of_device_id *of_id =
of_match_device(imx_ipu_dt_ids, &pdev->dev);
struct device_node *np = pdev->dev.of_node;
struct ipu_soc *ipu;
struct resource *res;
......@@ -1222,7 +1371,9 @@ static int ipu_probe(struct platform_device *pdev)
int i, ret, irq_sync, irq_err;
const struct ipu_devtype *devtype;
devtype = of_id->data;
devtype = of_device_get_match_data(&pdev->dev);
if (!devtype)
return -EINVAL;
irq_sync = platform_get_irq(pdev, 0);
irq_err = platform_get_irq(pdev, 1);
......
drivers/gpu/ipu-v3/ipu-dmfc.c
View file @ 26e34d2d
......@@ -123,20 +123,6 @@ int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc)
}
EXPORT_SYMBOL_GPL(ipu_dmfc_enable_channel);
static void ipu_dmfc_wait_fifos(struct ipu_dmfc_priv *priv)
{
unsigned long timeout = jiffies + msecs_to_jiffies(1000);
while ((readl(priv->base + DMFC_STAT) & 0x02fff000) != 0x02fff000) {
if (time_after(jiffies, timeout)) {
dev_warn(priv->dev,
"Timeout waiting for DMFC FIFOs to clear\n");
break;
}
cpu_relax();
}
}
void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
{
struct ipu_dmfc_priv *priv = dmfc->priv;
......@@ -145,10 +131,8 @@ void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
priv->use_count--;
if (!priv->use_count) {
ipu_dmfc_wait_fifos(priv);
if (!priv->use_count)
ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN);
}
if (priv->use_count < 0)
priv->use_count = 0;
......
drivers/gpu/ipu-v3/ipu-ic.c
View file @ 26e34d2d
......@@ -619,7 +619,7 @@ int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
ipu_ic_write(ic, ic_idmac_2, IC_IDMAC_2);
ipu_ic_write(ic, ic_idmac_3, IC_IDMAC_3);
if (rot >= IPU_ROTATE_90_RIGHT)
if (ipu_rot_mode_is_irt(rot))
ic->rotation = true;
unlock:
......
drivers/gpu/ipu-v3/ipu-image-convert.c 0 → 100644
View file @ 26e34d2d
/*
* Copyright (C) 2012-2016 Mentor Graphics Inc.
*
* Queued image conversion support, with tiling and rotation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <video/imx-ipu-image-convert.h>
#include "ipu-prv.h"
/*
* The IC Resizer has a restriction that the output frame from the
* resizer must be 1024 or less in both width (pixels) and height
* (lines).
*
* The image converter attempts to split up a conversion when
* the desired output (converted) frame resolution exceeds the
* IC resizer limit of 1024 in either dimension.
*
* If either dimension of the output frame exceeds the limit, the
* dimension is split into 1, 2, or 4 equal stripes, for a maximum
* of 4*4 or 16 tiles. A conversion is then carried out for each
* tile (but taking care to pass the full frame stride length to
* the DMA channel's parameter memory!). IDMA double-buffering is used
* to convert each tile back-to-back when possible (see note below
* when double_buffering boolean is set).
*
* Note that the input frame must be split up into the same number
* of tiles as the output frame.
*
* FIXME: at this point there is no attempt to deal with visible seams
* at the tile boundaries when upscaling. The seams are caused by a reset
* of the bilinear upscale interpolation when starting a new tile. The
* seams are barely visible for small upscale factors, but become
* increasingly visible as the upscale factor gets larger, since more
* interpolated pixels get thrown out at the tile boundaries. A possilble
* fix might be to overlap tiles of different sizes, but this must be done
* while also maintaining the IDMAC dma buffer address alignment and 8x8 IRT
* alignment restrictions of each tile.
*/
#define MAX_STRIPES_W 4
#define MAX_STRIPES_H 4
#define MAX_TILES (MAX_STRIPES_W * MAX_STRIPES_H)
#define MIN_W 16
#define MIN_H 8
#define MAX_W 4096
#define MAX_H 4096
enum ipu_image_convert_type {
IMAGE_CONVERT_IN = 0,
IMAGE_CONVERT_OUT,
};
struct ipu_image_convert_dma_buf {
void *virt;
dma_addr_t phys;
unsigned long len;
};
struct ipu_image_convert_dma_chan {
int in;
int out;
int rot_in;
int rot_out;
int vdi_in_p;
int vdi_in;
int vdi_in_n;
};
/* dimensions of one tile */
struct ipu_image_tile {
u32 width;
u32 height;
/* size and strides are in bytes */
u32 size;
u32 stride;
u32 rot_stride;
/* start Y or packed offset of this tile */
u32 offset;
/* offset from start to tile in U plane, for planar formats */
u32 u_off;
/* offset from start to tile in V plane, for planar formats */
u32 v_off;
};
struct ipu_image_convert_image {
struct ipu_image base;
enum ipu_image_convert_type type;
const struct ipu_image_pixfmt *fmt;
unsigned int stride;
/* # of rows (horizontal stripes) if dest height is > 1024 */
unsigned int num_rows;
/* # of columns (vertical stripes) if dest width is > 1024 */
unsigned int num_cols;
struct ipu_image_tile tile[MAX_TILES];
};
struct ipu_image_pixfmt {
u32 fourcc; /* V4L2 fourcc */
int bpp; /* total bpp */
int uv_width_dec; /* decimation in width for U/V planes */
int uv_height_dec; /* decimation in height for U/V planes */
bool planar; /* planar format */
bool uv_swapped; /* U and V planes are swapped */
bool uv_packed; /* partial planar (U and V in same plane) */
};
struct ipu_image_convert_ctx;
struct ipu_image_convert_chan;
struct ipu_image_convert_priv;
struct ipu_image_convert_ctx {
struct ipu_image_convert_chan *chan;
ipu_image_convert_cb_t complete;
void *complete_context;
/* Source/destination image data and rotation mode */
struct ipu_image_convert_image in;
struct ipu_image_convert_image out;
enum ipu_rotate_mode rot_mode;
/* intermediate buffer for rotation */
struct ipu_image_convert_dma_buf rot_intermediate[2];
/* current buffer number for double buffering */
int cur_buf_num;
bool aborting;
struct completion aborted;
/* can we use double-buffering for this conversion operation? */
bool double_buffering;
/* num_rows * num_cols */
unsigned int num_tiles;
/* next tile to process */
unsigned int next_tile;
/* where to place converted tile in dest image */
unsigned int out_tile_map[MAX_TILES];
struct list_head list;
};
struct ipu_image_convert_chan {
struct ipu_image_convert_priv *priv;
enum ipu_ic_task ic_task;
const struct ipu_image_convert_dma_chan *dma_ch;
struct ipu_ic *ic;
struct ipuv3_channel *in_chan;
struct ipuv3_channel *out_chan;
struct ipuv3_channel *rotation_in_chan;
struct ipuv3_channel *rotation_out_chan;
/* the IPU end-of-frame irqs */
int out_eof_irq;
int rot_out_eof_irq;
spinlock_t irqlock;
/* list of convert contexts */
struct list_head ctx_list;
/* queue of conversion runs */
struct list_head pending_q;
/* queue of completed runs */
struct list_head done_q;
/* the current conversion run */
struct ipu_image_convert_run *current_run;
};
struct ipu_image_convert_priv {
struct ipu_image_convert_chan chan[IC_NUM_TASKS];
struct ipu_soc *ipu;
};
static const struct ipu_image_convert_dma_chan
image_convert_dma_chan[IC_NUM_TASKS] = {
[IC_TASK_VIEWFINDER] = {
.in = IPUV3_CHANNEL_MEM_IC_PRP_VF,
.out = IPUV3_CHANNEL_IC_PRP_VF_MEM,
.rot_in = IPUV3_CHANNEL_MEM_ROT_VF,
.rot_out = IPUV3_CHANNEL_ROT_VF_MEM,
.vdi_in_p = IPUV3_CHANNEL_MEM_VDI_PREV,
.vdi_in = IPUV3_CHANNEL_MEM_VDI_CUR,
.vdi_in_n = IPUV3_CHANNEL_MEM_VDI_NEXT,
},
[IC_TASK_POST_PROCESSOR] = {
.in = IPUV3_CHANNEL_MEM_IC_PP,
.out = IPUV3_CHANNEL_IC_PP_MEM,
.rot_in = IPUV3_CHANNEL_MEM_ROT_PP,
.rot_out = IPUV3_CHANNEL_ROT_PP_MEM,
},
};
static const struct ipu_image_pixfmt image_convert_formats[] = {
{
.fourcc = V4L2_PIX_FMT_RGB565,
.bpp = 16,
}, {
.fourcc = V4L2_PIX_FMT_RGB24,
.bpp = 24,
}, {
.fourcc = V4L2_PIX_FMT_BGR24,
.bpp = 24,
}, {
.fourcc = V4L2_PIX_FMT_RGB32,
.bpp = 32,
}, {
.fourcc = V4L2_PIX_FMT_BGR32,
.bpp = 32,
}, {
.fourcc = V4L2_PIX_FMT_YUYV,
.bpp = 16,
.uv_width_dec = 2,
.uv_height_dec = 1,
}, {
.fourcc = V4L2_PIX_FMT_UYVY,
.bpp = 16,
.uv_width_dec = 2,
.uv_height_dec = 1,
}, {
.fourcc = V4L2_PIX_FMT_YUV420,
.bpp = 12,
.planar = true,
.uv_width_dec = 2,
.uv_height_dec = 2,
}, {
.fourcc = V4L2_PIX_FMT_YVU420,
.bpp = 12,
.planar = true,
.uv_width_dec = 2,
.uv_height_dec = 2,
.uv_swapped = true,
}, {
.fourcc = V4L2_PIX_FMT_NV12,
.bpp = 12,
.planar = true,
.uv_width_dec = 2,
.uv_height_dec = 2,
.uv_packed = true,
}, {
.fourcc = V4L2_PIX_FMT_YUV422P,
.bpp = 16,
.planar = true,
.uv_width_dec = 2,
.uv_height_dec = 1,
}, {
.fourcc = V4L2_PIX_FMT_NV16,
.bpp = 16,
.planar = true,
.uv_width_dec = 2,
.uv_height_dec = 1,
.uv_packed = true,
},
};
static const struct ipu_image_pixfmt *get_format(u32 fourcc)
{
const struct ipu_image_pixfmt *ret = NULL;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(image_convert_formats); i++) {
if (image_convert_formats[i].fourcc == fourcc) {
ret = &image_convert_formats[i];
break;
}
}
return ret;
}
static void dump_format(struct ipu_image_convert_ctx *ctx,
struct ipu_image_convert_image *ic_image)
{
struct ipu_image_convert_chan *chan = ctx->chan;
struct ipu_image_convert_priv *priv = chan->priv;
dev_dbg(priv->ipu->dev,
"task %u: ctx %p: %s format: %dx%d (%dx%d tiles of size %dx%d), %c%c%c%c\n",
chan->ic_task, ctx,
ic_image->type == IMAGE_CONVERT_OUT ? "Output" : "Input",
ic_image->base.pix.width, ic_image->base.pix.height,
ic_image->num_cols, ic_image->num_rows,
ic_image->tile[0].width, ic_image->tile[0].height,
ic_image->fmt->fourcc & 0xff,
(ic_image->fmt->fourcc >> 8) & 0xff,
(ic_image->fmt->fourcc >> 16) & 0xff,
(ic_image->fmt->fourcc >> 24) & 0xff);
}
int ipu_image_convert_enum_format(int index, u32 *fourcc)
{
const struct ipu_image_pixfmt *fmt;
if (index >= (int)ARRAY_SIZE(image_convert_formats))
return -EINVAL;
/* Format found */
fmt = &image_convert_formats[index];
*fourcc = fmt->fourcc;
return 0;
}
EXPORT_SYMBOL_GPL(ipu_image_convert_enum_format);
static void free_dma_buf(struct ipu_image_convert_priv *priv,
struct ipu_image_convert_dma_buf *buf)
{
if (buf->virt)
dma_free_coherent(priv->ipu->dev,
buf->len, buf->virt, buf->phys);
buf->virt = NULL;
buf->phys = 0;
}
static int alloc_dma_buf(struct ipu_image_convert_priv *priv,
struct ipu_image_convert_dma_buf *buf,
int size)
{
buf->len = PAGE_ALIGN(size);
buf->virt = dma_alloc_coherent(priv->ipu->dev, buf->len, &buf->phys,
GFP_DMA | GFP_KERNEL);
if (!buf->virt) {
dev_err(priv->ipu->dev, "failed to alloc dma buffer\n");
return -ENOMEM;
}
return 0;
}
static inline int num_stripes(int dim)
{
if (dim <= 1024)
return 1;
else if (dim <= 2048)
return 2;
else
return 4;
}
static void calc_tile_dimensions(struct ipu_image_convert_ctx *ctx,
struct ipu_image_convert_image *image)
{
int i;
for (i = 0; i < ctx->num_tiles; i++) {
struct ipu_image_tile *tile = &image->tile[i];
tile->height = image->base.pix.height / image->num_rows;
tile->width = image->base.pix.width / image->num_cols;
tile->size = ((tile->height * image->fmt->bpp) >> 3) *
tile->width;
if (image->fmt->planar) {
tile->stride = tile->width;
tile->rot_stride = tile->height;
} else {
tile->stride =
(image->fmt->bpp * tile->width) >> 3;
tile->rot_stride =
(image->fmt->bpp * tile->height) >> 3;
}
}
}
/*
* Use the rotation transformation to find the tile coordinates
* (row, col) of a tile in the destination frame that corresponds
* to the given tile coordinates of a source frame. The destination
* coordinate is then converted to a tile index.
*/
static int transform_tile_index(struct ipu_image_convert_ctx *ctx,
int src_row, int src_col)
{
struct ipu_image_convert_chan *chan = ctx->chan;
struct ipu_image_convert_priv *priv = chan->priv;
struct ipu_image_convert_image *s_image = &ctx->in;
struct ipu_image_convert_image *d_image = &ctx->out;
int dst_row, dst_col;
/* with no rotation it's a 1:1 mapping */
if (ctx->rot_mode == IPU_ROTATE_NONE)
return src_row * s_image->num_cols + src_col;
/*
* before doing the transform, first we have to translate
* source row,col for an origin in the center of s_image
*/
src_row = src_row * 2 - (s_image->num_rows - 1);
src_col = src_col * 2 - (s_image->num_cols - 1);
/* do the rotation transform */
if (ctx->rot_mode & IPU_ROT_BIT_90) {
dst_col = -src_row;
dst_row = src_col;
} else {
dst_col = src_col;
dst_row = src_row;
}
/* apply flip */
if (ctx->rot_mode & IPU_ROT_BIT_HFLIP)
dst_col = -dst_col;
if (ctx->rot_mode & IPU_ROT_BIT_VFLIP)
dst_row = -dst_row;
dev_dbg(priv->ipu->dev, "task %u: ctx %p: [%d,%d] --> [%d,%d]\n",
chan->ic_task, ctx, src_col, src_row, dst_col, dst_row);
/*
* finally translate dest row,col using an origin in upper
* left of d_image
*/
dst_row += d_image->num_rows - 1;
dst_col += d_image->num_cols - 1;
dst_row /= 2;
dst_col /= 2;
return dst_row * d_image->num_cols + dst_col;
}
/*
* Fill the out_tile_map[] with transformed destination tile indeces.
*/
static void calc_out_tile_map(struct ipu_image_convert_ctx *ctx)
{
struct ipu_image_convert_image *s_image = &ctx->in;
unsigned int row, col, tile = 0;
for (row = 0; row < s_image->num_rows; row++) {
for (col = 0; col < s_image->num_cols; col++) {
ctx->out_tile_map[tile] =
transform_tile_index(ctx, row, col);
tile++;
}
}
}
static void calc_tile_offsets_planar(struct ipu_image_convert_ctx *ctx,
struct ipu_image_convert_image *image)
{
struct ipu_image_convert_chan *chan = ctx->chan;
struct ipu_image_convert_priv *priv = chan->priv;
const struct ipu_image_pixfmt *fmt = image->fmt;
unsigned int row, col, tile = 0;
u32 H, w, h, y_stride, uv_stride;
u32 uv_row_off, uv_col_off, uv_off, u_off, v_off, tmp;
u32 y_row_off, y_col_off, y_off;
u32 y_size, uv_size;
/* setup some convenience vars */
H = image->base.pix.height;
y_stride = image->stride;
uv_stride = y_stride / fmt->uv_width_dec;
if (fmt->uv_packed)
uv_stride *= 2;
y_size = H * y_stride;
uv_size = y_size / (fmt->uv_width_dec * fmt->uv_height_dec);
for (row = 0; row < image->num_rows; row++) {
w = image->tile[tile].width;
h = image->tile[tile].height;
y_row_off = row * h * y_stride;
uv_row_off = (row * h * uv_stride) / fmt->uv_height_dec;
for (col = 0; col < image->num_cols; col++) {
y_col_off = col * w;
uv_col_off = y_col_off / fmt->uv_width_dec;
if (fmt->uv_packed)
uv_col_off *= 2;
y_off = y_row_off + y_col_off;
uv_off = uv_row_off + uv_col_off;
u_off = y_size - y_off + uv_off;
v_off = (fmt->uv_packed) ? 0 : u_off + uv_size;
if (fmt->uv_swapped) {
tmp = u_off;
u_off = v_off;
v_off = tmp;
}
image->tile[tile].offset = y_off;
image->tile[tile].u_off = u_off;
image->tile[tile++].v_off = v_off;
dev_dbg(priv->ipu->dev,
"task %u: ctx %p: %s@[%d,%d]: y_off %08x, u_off %08x, v_off %08x\n",
chan->ic_task, ctx,
image->type == IMAGE_CONVERT_IN ?
"Input" : "Output", row, col,
y_off, u_off, v_off);
}
}
}
static void calc_tile_offsets_packed(struct ipu_image_convert_ctx *ctx,
struct ipu_image_convert_image *image)
{
struct ipu_image_convert_chan *chan = ctx->chan;
struct ipu_image_convert_priv *priv = chan->priv;
const struct ipu_image_pixfmt *fmt = image->fmt;
unsigned int row, col, tile = 0;
u32 w, h, bpp, stride;
u32 row_off, col_off;
/* setup some convenience vars */
stride = image->stride;
bpp = fmt->bpp;
for (row = 0; row < image->num_rows; row++) {
w = image->tile[tile].width;
h = image->tile[tile].height;
row_off = row * h * stride;
for (col = 0; col < image->num_cols; col++) {
col_off = (col * w * bpp) >> 3;
image->tile[tile].offset = row_off + col_off;
image->tile[tile].u_off = 0;
image->tile[tile++].v_off = 0;
dev_dbg(priv->ipu->dev,
"task %u: ctx %p: %s@[%d,%d]: phys %08x\n",
chan->ic_task, ctx,
image->type == IMAGE_CONVERT_IN ?
"Input" : "Output", row, col,
row_off + col_off);
}
}
}
static void calc_tile_offsets(struct ipu_image_convert_ctx *ctx,
struct ipu_image_convert_image *image)
{
if (image->fmt->planar)
calc_tile_offsets_planar(ctx, image);
else
calc_tile_offsets_packed(ctx, image);
}
/*
* return the number of runs in given queue (pending_q or done_q)
* for this context. hold irqlock when calling.
*/
static int get_run_count(struct ipu_image_convert_ctx *ctx,
struct list_head *q)
{
struct ipu_image_convert_run *run;
int count = 0;
lockdep_assert_held(&ctx->chan->irqlock);
list_for_each_entry(run, q, list) {
if (run->ctx == ctx)
count++;
}
return count;
}
static void convert_stop(struct ipu_image_convert_run *run)
{
struct ipu_image_convert_ctx *ctx = run->ctx;
struct ipu_image_convert_chan *chan = ctx->chan;
struct ipu_image_convert_priv *priv = chan->priv;
dev_dbg(priv->ipu->dev, "%s: task %u: stopping ctx %p run %p\n",
__func__, chan->ic_task, ctx, run);
/* disable IC tasks and the channels */
ipu_ic_task_disable(chan->ic);
ipu_idmac_disable_channel(chan->in_chan);
ipu_idmac_disable_channel(chan->out_chan);
if (ipu_rot_mode_is_irt(ctx->rot_mode)) {
ipu_idmac_disable_channel(chan->rotation_in_chan);
ipu_idmac_disable_channel(chan->rotation_out_chan);
ipu_idmac_unlink(chan->out_chan, chan->rotation_in_chan);
}
ipu_ic_disable(chan->ic);
}
static void init_idmac_channel(struct ipu_image_convert_ctx *ctx,
struct ipuv3_channel *channel,
struct ipu_image_convert_image *image,
enum ipu_rotate_mode rot_mode,
bool rot_swap_width_height)
{
struct ipu_image_convert_chan *chan = ctx->chan;
unsigned int burst_size;
u32 width, height, stride;
dma_addr_t addr0, addr1 = 0;
struct ipu_image tile_image;
unsigned int tile_idx[2];
if (image->type == IMAGE_CONVERT_OUT) {
tile_idx[0] = ctx->out_tile_map[0];
tile_idx[1] = ctx->out_tile_map[1];
} else {
tile_idx[0] = 0;
tile_idx[1] = 1;
}
if (rot_swap_width_height) {
width = image->tile[0].height;
height = image->tile[0].width;
stride = image->tile[0].rot_stride;
addr0 = ctx->rot_intermediate[0].phys;
if (ctx->double_buffering)
addr1 = ctx->rot_intermediate[1].phys;
} else {
width = image->tile[0].width;
height = image->tile[0].height;
stride = image->stride;
addr0 = image->base.phys0 +
image->tile[tile_idx[0]].offset;
if (ctx->double_buffering)
addr1 = image->base.phys0 +
image->tile[tile_idx[1]].offset;
}
ipu_cpmem_zero(channel);
memset(&tile_image, 0, sizeof(tile_image));
tile_image.pix.width = tile_image.rect.width = width;
tile_image.pix.height = tile_image.rect.height = height;
tile_image.pix.bytesperline = stride;
tile_image.pix.pixelformat = image->fmt->fourcc;
tile_image.phys0 = addr0;
tile_image.phys1 = addr1;
ipu_cpmem_set_image(channel, &tile_image);
if (image->fmt->planar && !rot_swap_width_height)
ipu_cpmem_set_uv_offset(channel,
image->tile[tile_idx[0]].u_off,
image->tile[tile_idx[0]].v_off);
if (rot_mode)
ipu_cpmem_set_rotation(channel, rot_mode);
if (channel == chan->rotation_in_chan ||
channel == chan->rotation_out_chan) {
burst_size = 8;
ipu_cpmem_set_block_mode(channel);
} else
burst_size = (width % 16) ? 8 : 16;
ipu_cpmem_set_burstsize(channel, burst_size);
ipu_ic_task_idma_init(chan->ic, channel, width, height,
burst_size, rot_mode);
ipu_cpmem_set_axi_id(channel, 1);
ipu_idmac_set_double_buffer(channel, ctx->double_buffering);
}
static int convert_start(struct ipu_image_convert_run *run)
{
struct ipu_image_convert_ctx *ctx = run->ctx;
struct ipu_image_convert_chan *chan = ctx->chan;
struct ipu_image_convert_priv *priv = chan->priv;
struct ipu_image_convert_image *s_image = &ctx->in;
struct ipu_image_convert_image *d_image = &ctx->out;
enum ipu_color_space src_cs, dest_cs;
unsigned int dest_width, dest_height;
int ret;
dev_dbg(priv->ipu->dev, "%s: task %u: starting ctx %p run %p\n",
__func__, chan->ic_task, ctx, run);
src_cs = ipu_pixelformat_to_colorspace(s_image->fmt->fourcc);
dest_cs = ipu_pixelformat_to_colorspace(d_image->fmt->fourcc);
if (ipu_rot_mode_is_irt(ctx->rot_mode)) {
/* swap width/height for resizer */
dest_width = d_image->tile[0].height;
dest_height = d_image->tile[0].width;
} else {
dest_width = d_image->tile[0].width;
dest_height = d_image->tile[0].height;
}
/* setup the IC resizer and CSC */
ret = ipu_ic_task_init(chan->ic,
s_image->tile[0].width,
s_image->tile[0].height,
dest_width,
dest_height,
src_cs, dest_cs);
if (ret) {
dev_err(priv->ipu->dev, "ipu_ic_task_init failed, %d\n", ret);
return ret;
}
/* init the source MEM-->IC PP IDMAC channel */
init_idmac_channel(ctx, chan->in_chan, s_image,
IPU_ROTATE_NONE, false);
if (ipu_rot_mode_is_irt(ctx->rot_mode)) {
/* init the IC PP-->MEM IDMAC channel */
init_idmac_channel(ctx, chan->out_chan, d_image,
IPU_ROTATE_NONE, true);
/* init the MEM-->IC PP ROT IDMAC channel */
init_idmac_channel(ctx, chan->rotation_in_chan, d_image,
ctx->rot_mode, true);
/* init the destination IC PP ROT-->MEM IDMAC channel */
init_idmac_channel(ctx, chan->rotation_out_chan, d_image,
IPU_ROTATE_NONE, false);
/* now link IC PP-->MEM to MEM-->IC PP ROT */
ipu_idmac_link(chan->out_chan, chan->rotation_in_chan);
} else {
/* init the destination IC PP-->MEM IDMAC channel */
init_idmac_channel(ctx, chan->out_chan, d_image,
ctx->rot_mode, false);
}
/* enable the IC */
ipu_ic_enable(chan->ic);
/* set buffers ready */
ipu_idmac_select_buffer(chan->in_chan, 0);
ipu_idmac_select_buffer(chan->out_chan, 0);
if (ipu_rot_mode_is_irt(ctx->rot_mode))
ipu_idmac_select_buffer(chan->rotation_out_chan, 0);
if (ctx->double_buffering) {
ipu_idmac_select_buffer(chan->in_chan, 1);
ipu_idmac_select_buffer(chan->out_chan, 1);
if (ipu_rot_mode_is_irt(ctx->rot_mode))
ipu_idmac_select_buffer(chan->rotation_out_chan, 1);
}
/* enable the channels! */
ipu_idmac_enable_channel(chan->in_chan);
ipu_idmac_enable_channel(chan->out_chan);
if (ipu_rot_mode_is_irt(ctx->rot_mode)) {
ipu_idmac_enable_channel(chan->rotation_in_chan);
ipu_idmac_enable_channel(chan->rotation_out_chan);
}
ipu_ic_task_enable(chan->ic);
ipu_cpmem_dump(chan->in_chan);
ipu_cpmem_dump(chan->out_chan);
if (ipu_rot_mode_is_irt(ctx->rot_mode)) {
ipu_cpmem_dump(chan->rotation_in_chan);
ipu_cpmem_dump(chan->rotation_out_chan);
}
ipu_dump(priv->ipu);
return 0;
}
/* hold irqlock when calling */
static int do_run(struct ipu_image_convert_run *run)
{
struct ipu_image_convert_ctx *ctx = run->ctx;
struct ipu_image_convert_chan *chan = ctx->chan;
lockdep_assert_held(&chan->irqlock);
ctx->in.base.phys0 = run->in_phys;
ctx->out.base.phys0 = run->out_phys;
ctx->cur_buf_num = 0;
ctx->next_tile = 1;
/* remove run from pending_q and set as current */
list_del(&run->list);
chan->current_run = run;
return convert_start(run);
}
/* hold irqlock when calling */
static void run_next(struct ipu_image_convert_chan *chan)
{
struct ipu_image_convert_priv *priv = chan->priv;
struct ipu_image_convert_run *run, *tmp;
int ret;
lockdep_assert_held(&chan->irqlock);
list_for_each_entry_safe(run, tmp, &chan->pending_q, list) {
/* skip contexts that are aborting */
if (run->ctx->aborting) {
dev_dbg(priv->ipu->dev,
"%s: task %u: skipping aborting ctx %p run %p\n",
__func__, chan->ic_task, run->ctx, run);
continue;
}
ret = do_run(run);
if (!ret)
break;
/*
* something went wrong with start, add the run
* to done q and continue to the next run in the
* pending q.
*/
run->status = ret;
list_add_tail(&run->list, &chan->done_q);
chan->current_run = NULL;
}
}
static void empty_done_q(struct ipu_image_convert_chan *chan)
{
struct ipu_image_convert_priv *priv = chan->priv;
struct ipu_image_convert_run *run;
unsigned long flags;
spin_lock_irqsave(&chan->irqlock, flags);
while (!list_empty(&chan->done_q)) {
run = list_entry(chan->done_q.next,
struct ipu_image_convert_run,
list);
list_del(&run->list);
dev_dbg(priv->ipu->dev,
"%s: task %u: completing ctx %p run %p with %d\n",
__func__, chan->ic_task, run->ctx, run, run->status);
/* call the completion callback and free the run */
spin_unlock_irqrestore(&chan->irqlock, flags);
run->ctx->complete(run, run->ctx->complete_context);
spin_lock_irqsave(&chan->irqlock, flags);
}
spin_unlock_irqrestore(&chan->irqlock, flags);
}
/*
* the bottom half thread clears out the done_q, calling the
* completion handler for each.
*/
static irqreturn_t do_bh(int irq, void *dev_id)
{
struct ipu_image_convert_chan *chan = dev_id;
struct ipu_image_convert_priv *priv = chan->priv;
struct ipu_image_convert_ctx *ctx;
unsigned long flags;
dev_dbg(priv->ipu->dev, "%s: task %u: enter\n", __func__,
chan->ic_task);
empty_done_q(chan);
spin_lock_irqsave(&chan->irqlock, flags);
/*
* the done_q is cleared out, signal any contexts
* that are aborting that abort can complete.
*/
list_for_each_entry(ctx, &chan->ctx_list, list) {
if (ctx->aborting) {
dev_dbg(priv->ipu->dev,
"%s: task %u: signaling abort for ctx %p\n",
__func__, chan->ic_task, ctx);
complete(&ctx->aborted);
}
}
spin_unlock_irqrestore(&chan->irqlock, flags);
dev_dbg(priv->ipu->dev, "%s: task %u: exit\n", __func__,
chan->ic_task);
return IRQ_HANDLED;
}
/* hold irqlock when calling */
static irqreturn_t do_irq(struct ipu_image_convert_run *run)
{
struct ipu_image_convert_ctx *ctx = run->ctx;
struct ipu_image_convert_chan *chan = ctx->chan;
struct ipu_image_tile *src_tile, *dst_tile;
struct ipu_image_convert_image *s_image = &ctx->in;
struct ipu_image_convert_image *d_image = &ctx->out;
struct ipuv3_channel *outch;
unsigned int dst_idx;
lockdep_assert_held(&chan->irqlock);
outch = ipu_rot_mode_is_irt(ctx->rot_mode) ?
chan->rotation_out_chan : chan->out_chan;
/*
* It is difficult to stop the channel DMA before the channels
* enter the paused state. Without double-buffering the channels
* are always in a paused state when the EOF irq occurs, so it
* is safe to stop the channels now. For double-buffering we
* just ignore the abort until the operation completes, when it
* is safe to shut down.
*/
if (ctx->aborting && !ctx->double_buffering) {
convert_stop(run);
run->status = -EIO;
goto done;
}
if (ctx->next_tile == ctx->num_tiles) {
/*
* the conversion is complete
*/
convert_stop(run);
run->status = 0;
goto done;
}
/*
* not done, place the next tile buffers.
*/
if (!ctx->double_buffering) {
src_tile = &s_image->tile[ctx->next_tile];
dst_idx = ctx->out_tile_map[ctx->next_tile];
dst_tile = &d_image->tile[dst_idx];
ipu_cpmem_set_buffer(chan->in_chan, 0,
s_image->base.phys0 + src_tile->offset);
ipu_cpmem_set_buffer(outch, 0,
d_image->base.phys0 + dst_tile->offset);
if (s_image->fmt->planar)
ipu_cpmem_set_uv_offset(chan->in_chan,
src_tile->u_off,
src_tile->v_off);
if (d_image->fmt->planar)
ipu_cpmem_set_uv_offset(outch,
dst_tile->u_off,
dst_tile->v_off);
ipu_idmac_select_buffer(chan->in_chan, 0);
ipu_idmac_select_buffer(outch, 0);
} else if (ctx->next_tile < ctx->num_tiles - 1) {
src_tile = &s_image->tile[ctx->next_tile + 1];
dst_idx = ctx->out_tile_map[ctx->next_tile + 1];
dst_tile = &d_image->tile[dst_idx];
ipu_cpmem_set_buffer(chan->in_chan, ctx->cur_buf_num,
s_image->base.phys0 + src_tile->offset);
ipu_cpmem_set_buffer(outch, ctx->cur_buf_num,
d_image->base.phys0 + dst_tile->offset);
ipu_idmac_select_buffer(chan->in_chan, ctx->cur_buf_num);
ipu_idmac_select_buffer(outch, ctx->cur_buf_num);
ctx->cur_buf_num ^= 1;
}
ctx->next_tile++;
return IRQ_HANDLED;
done:
list_add_tail(&run->list, &chan->done_q);
chan->current_run = NULL;
run_next(chan);
return IRQ_WAKE_THREAD;
}
static irqreturn_t norotate_irq(int irq, void *data)
{
struct ipu_image_convert_chan *chan = data;
struct ipu_image_convert_ctx *ctx;
struct ipu_image_convert_run *run;
unsigned long flags;
irqreturn_t ret;
spin_lock_irqsave(&chan->irqlock, flags);
/* get current run and its context */
run = chan->current_run;
if (!run) {
ret = IRQ_NONE;
goto out;
}
ctx = run->ctx;
if (ipu_rot_mode_is_irt(ctx->rot_mode)) {
/* this is a rotation operation, just ignore */
spin_unlock_irqrestore(&chan->irqlock, flags);
return IRQ_HANDLED;
}
ret = do_irq(run);
out:
spin_unlock_irqrestore(&chan->irqlock, flags);
return ret;
}
static irqreturn_t rotate_irq(int irq, void *data)
{
struct ipu_image_convert_chan *chan = data;
struct ipu_image_convert_priv *priv = chan->priv;
struct ipu_image_convert_ctx *ctx;
struct ipu_image_convert_run *run;
unsigned long flags;
irqreturn_t ret;
spin_lock_irqsave(&chan->irqlock, flags);
/* get current run and its context */
run = chan->current_run;
if (!run) {
ret = IRQ_NONE;
goto out;
}
ctx = run->ctx;
if (!ipu_rot_mode_is_irt(ctx->rot_mode)) {
/* this was NOT a rotation operation, shouldn't happen */
dev_err(priv->ipu->dev, "Unexpected rotation interrupt\n");
spin_unlock_irqrestore(&chan->irqlock, flags);
return IRQ_HANDLED;
}
ret = do_irq(run);
out:
spin_unlock_irqrestore(&chan->irqlock, flags);
return ret;
}
/*
* try to force the completion of runs for this ctx. Called when
* abort wait times out in ipu_image_convert_abort().
*/
static void force_abort(struct ipu_image_convert_ctx *ctx)
{
struct ipu_image_convert_chan *chan = ctx->chan;
struct ipu_image_convert_run *run;
unsigned long flags;
spin_lock_irqsave(&chan->irqlock, flags);
run = chan->current_run;
if (run && run->ctx == ctx) {
convert_stop(run);
run->status = -EIO;
list_add_tail(&run->list, &chan->done_q);
chan->current_run = NULL;
run_next(chan);
}
spin_unlock_irqrestore(&chan->irqlock, flags);
empty_done_q(chan);
}
static void release_ipu_resources(struct ipu_image_convert_chan *chan)
{
if (chan->out_eof_irq >= 0)
free_irq(chan->out_eof_irq, chan);
if (chan->rot_out_eof_irq >= 0)
free_irq(chan->rot_out_eof_irq, chan);
if (!IS_ERR_OR_NULL(chan->in_chan))
ipu_idmac_put(chan->in_chan);
if (!IS_ERR_OR_NULL(chan->out_chan))
ipu_idmac_put(chan->out_chan);
if (!IS_ERR_OR_NULL(chan->rotation_in_chan))
ipu_idmac_put(chan->rotation_in_chan);
if (!IS_ERR_OR_NULL(chan->rotation_out_chan))
ipu_idmac_put(chan->rotation_out_chan);
if (!IS_ERR_OR_NULL(chan->ic))
ipu_ic_put(chan->ic);
chan->in_chan = chan->out_chan = chan->rotation_in_chan =
chan->rotation_out_chan = NULL;
chan->out_eof_irq = chan->rot_out_eof_irq = -1;
}
static int get_ipu_resources(struct ipu_image_convert_chan *chan)
{
const struct ipu_image_convert_dma_chan *dma = chan->dma_ch;
struct ipu_image_convert_priv *priv = chan->priv;
int ret;
/* get IC */
chan->ic = ipu_ic_get(priv->ipu, chan->ic_task);
if (IS_ERR(chan->ic)) {
dev_err(priv->ipu->dev, "could not acquire IC\n");
ret = PTR_ERR(chan->ic);
goto err;
}
/* get IDMAC channels */
chan->in_chan = ipu_idmac_get(priv->ipu, dma->in);
chan->out_chan = ipu_idmac_get(priv->ipu, dma->out);
if (IS_ERR(chan->in_chan) || IS_ERR(chan->out_chan)) {
dev_err(priv->ipu->dev, "could not acquire idmac channels\n");
ret = -EBUSY;
goto err;
}
chan->rotation_in_chan = ipu_idmac_get(priv->ipu, dma->rot_in);
chan->rotation_out_chan = ipu_idmac_get(priv->ipu, dma->rot_out);
if (IS_ERR(chan->rotation_in_chan) || IS_ERR(chan->rotation_out_chan)) {
dev_err(priv->ipu->dev,
"could not acquire idmac rotation channels\n");
ret = -EBUSY;
goto err;
}
/* acquire the EOF interrupts */
chan->out_eof_irq = ipu_idmac_channel_irq(priv->ipu,
chan->out_chan,
IPU_IRQ_EOF);
ret = request_threaded_irq(chan->out_eof_irq, norotate_irq, do_bh,
0, "ipu-ic", chan);
if (ret < 0) {
dev_err(priv->ipu->dev, "could not acquire irq %d\n",
chan->out_eof_irq);
chan->out_eof_irq = -1;
goto err;
}
chan->rot_out_eof_irq = ipu_idmac_channel_irq(priv->ipu,
chan->rotation_out_chan,
IPU_IRQ_EOF);
ret = request_threaded_irq(chan->rot_out_eof_irq, rotate_irq, do_bh,
0, "ipu-ic", chan);
if (ret < 0) {
dev_err(priv->ipu->dev, "could not acquire irq %d\n",
chan->rot_out_eof_irq);
chan->rot_out_eof_irq = -1;
goto err;
}
return 0;
err:
release_ipu_resources(chan);
return ret;
}
static int fill_image(struct ipu_image_convert_ctx *ctx,
struct ipu_image_convert_image *ic_image,
struct ipu_image *image,
enum ipu_image_convert_type type)
{
struct ipu_image_convert_priv *priv = ctx->chan->priv;
ic_image->base = *image;
ic_image->type = type;
ic_image->fmt = get_format(image->pix.pixelformat);
if (!ic_image->fmt) {
dev_err(priv->ipu->dev, "pixelformat not supported for %s\n",
type == IMAGE_CONVERT_OUT ? "Output" : "Input");
return -EINVAL;
}
if (ic_image->fmt->planar)
ic_image->stride = ic_image->base.pix.width;
else
ic_image->stride = ic_image->base.pix.bytesperline;
calc_tile_dimensions(ctx, ic_image);
calc_tile_offsets(ctx, ic_image);
return 0;
}
/* borrowed from drivers/media/v4l2-core/v4l2-common.c */
static unsigned int clamp_align(unsigned int x, unsigned int min,
unsigned int max, unsigned int align)
{
/* Bits that must be zero to be aligned */
unsigned int mask = ~((1 << align) - 1);
/* Clamp to aligned min and max */
x = clamp(x, (min + ~mask) & mask, max & mask);
/* Round to nearest aligned value */
if (align)
x = (x + (1 << (align - 1))) & mask;
return x;
}
/*
* We have to adjust the tile width such that the tile physaddrs and
* U and V plane offsets are multiples of 8 bytes as required by
* the IPU DMA Controller. For the planar formats, this corresponds
* to a pixel alignment of 16 (but use a more formal equation since
* the variables are available). For all the packed formats, 8 is
* good enough.
*/
static inline u32 tile_width_align(const struct ipu_image_pixfmt *fmt)
{
return fmt->planar ? 8 * fmt->uv_width_dec : 8;
}
/*
* For tile height alignment, we have to ensure that the output tile
* heights are multiples of 8 lines if the IRT is required by the
* given rotation mode (the IRT performs rotations on 8x8 blocks
* at a time). If the IRT is not used, or for input image tiles,
* 2 lines are good enough.
*/
static inline u32 tile_height_align(enum ipu_image_convert_type type,
enum ipu_rotate_mode rot_mode)
{
return (type == IMAGE_CONVERT_OUT &&
ipu_rot_mode_is_irt(rot_mode)) ? 8 : 2;
}
/* Adjusts input/output images to IPU restrictions */
void ipu_image_convert_adjust(struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode)
{
const struct ipu_image_pixfmt *infmt, *outfmt;
unsigned int num_in_rows, num_in_cols;
unsigned int num_out_rows, num_out_cols;
u32 w_align, h_align;
infmt = get_format(in->pix.pixelformat);
outfmt = get_format(out->pix.pixelformat);
/* set some default pixel formats if needed */
if (!infmt) {
in->pix.pixelformat = V4L2_PIX_FMT_RGB24;
infmt = get_format(V4L2_PIX_FMT_RGB24);
}
if (!outfmt) {
out->pix.pixelformat = V4L2_PIX_FMT_RGB24;
outfmt = get_format(V4L2_PIX_FMT_RGB24);
}
/* image converter does not handle fields */
in->pix.field = out->pix.field = V4L2_FIELD_NONE;
/* resizer cannot downsize more than 4:1 */
if (ipu_rot_mode_is_irt(rot_mode)) {
out->pix.height = max_t(__u32, out->pix.height,
in->pix.width / 4);
out->pix.width = max_t(__u32, out->pix.width,
in->pix.height / 4);
} else {
out->pix.width = max_t(__u32, out->pix.width,
in->pix.width / 4);
out->pix.height = max_t(__u32, out->pix.height,
in->pix.height / 4);
}
/* get tiling rows/cols from output format */
num_out_rows = num_stripes(out->pix.height);
num_out_cols = num_stripes(out->pix.width);
if (ipu_rot_mode_is_irt(rot_mode)) {
num_in_rows = num_out_cols;
num_in_cols = num_out_rows;
} else {
num_in_rows = num_out_rows;
num_in_cols = num_out_cols;
}
/* align input width/height */
w_align = ilog2(tile_width_align(infmt) * num_in_cols);
h_align = ilog2(tile_height_align(IMAGE_CONVERT_IN, rot_mode) *
num_in_rows);
in->pix.width = clamp_align(in->pix.width, MIN_W, MAX_W, w_align);
in->pix.height = clamp_align(in->pix.height, MIN_H, MAX_H, h_align);
/* align output width/height */
w_align = ilog2(tile_width_align(outfmt) * num_out_cols);
h_align = ilog2(tile_height_align(IMAGE_CONVERT_OUT, rot_mode) *
num_out_rows);
out->pix.width = clamp_align(out->pix.width, MIN_W, MAX_W, w_align);
out->pix.height = clamp_align(out->pix.height, MIN_H, MAX_H, h_align);
/* set input/output strides and image sizes */
in->pix.bytesperline = (in->pix.width * infmt->bpp) >> 3;
in->pix.sizeimage = in->pix.height * in->pix.bytesperline;
out->pix.bytesperline = (out->pix.width * outfmt->bpp) >> 3;
out->pix.sizeimage = out->pix.height * out->pix.bytesperline;
}
EXPORT_SYMBOL_GPL(ipu_image_convert_adjust);
/*
* this is used by ipu_image_convert_prepare() to verify set input and
* output images are valid before starting the conversion. Clients can
* also call it before calling ipu_image_convert_prepare().
*/
int ipu_image_convert_verify(struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode)
{
struct ipu_image testin, testout;
testin = *in;
testout = *out;
ipu_image_convert_adjust(&testin, &testout, rot_mode);
if (testin.pix.width != in->pix.width ||
testin.pix.height != in->pix.height ||
testout.pix.width != out->pix.width ||
testout.pix.height != out->pix.height)
return -EINVAL;
return 0;
}
EXPORT_SYMBOL_GPL(ipu_image_convert_verify);
/*
* Call ipu_image_convert_prepare() to prepare for the conversion of
* given images and rotation mode. Returns a new conversion context.
*/
struct ipu_image_convert_ctx *
ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task,
struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode,
ipu_image_convert_cb_t complete,
void *complete_context)
{
struct ipu_image_convert_priv *priv = ipu->image_convert_priv;
struct ipu_image_convert_image *s_image, *d_image;
struct ipu_image_convert_chan *chan;
struct ipu_image_convert_ctx *ctx;
unsigned long flags;
bool get_res;
int ret;
if (!in || !out || !complete ||
(ic_task != IC_TASK_VIEWFINDER &&
ic_task != IC_TASK_POST_PROCESSOR))
return ERR_PTR(-EINVAL);
/* verify the in/out images before continuing */
ret = ipu_image_convert_verify(in, out, rot_mode);
if (ret) {
dev_err(priv->ipu->dev, "%s: in/out formats invalid\n",
__func__);
return ERR_PTR(ret);
}
chan = &priv->chan[ic_task];
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return ERR_PTR(-ENOMEM);
dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p\n", __func__,
chan->ic_task, ctx);
ctx->chan = chan;
init_completion(&ctx->aborted);
s_image = &ctx->in;
d_image = &ctx->out;
/* set tiling and rotation */
d_image->num_rows = num_stripes(out->pix.height);
d_image->num_cols = num_stripes(out->pix.width);
if (ipu_rot_mode_is_irt(rot_mode)) {
s_image->num_rows = d_image->num_cols;
s_image->num_cols = d_image->num_rows;
} else {
s_image->num_rows = d_image->num_rows;
s_image->num_cols = d_image->num_cols;
}
ctx->num_tiles = d_image->num_cols * d_image->num_rows;
ctx->rot_mode = rot_mode;
ret = fill_image(ctx, s_image, in, IMAGE_CONVERT_IN);
if (ret)
goto out_free;
ret = fill_image(ctx, d_image, out, IMAGE_CONVERT_OUT);
if (ret)
goto out_free;
calc_out_tile_map(ctx);
dump_format(ctx, s_image);
dump_format(ctx, d_image);
ctx->complete = complete;
ctx->complete_context = complete_context;
/*
* Can we use double-buffering for this operation? If there is
* only one tile (the whole image can be converted in a single
* operation) there's no point in using double-buffering. Also,
* the IPU's IDMAC channels allow only a single U and V plane
* offset shared between both buffers, but these offsets change
* for every tile, and therefore would have to be updated for
* each buffer which is not possible. So double-buffering is
* impossible when either the source or destination images are
* a planar format (YUV420, YUV422P, etc.).
*/
ctx->double_buffering = (ctx->num_tiles > 1 &&
!s_image->fmt->planar &&
!d_image->fmt->planar);
if (ipu_rot_mode_is_irt(ctx->rot_mode)) {
ret = alloc_dma_buf(priv, &ctx->rot_intermediate[0],
d_image->tile[0].size);
if (ret)
goto out_free;
if (ctx->double_buffering) {
ret = alloc_dma_buf(priv,
&ctx->rot_intermediate[1],
d_image->tile[0].size);
if (ret)
goto out_free_dmabuf0;
}
}
spin_lock_irqsave(&chan->irqlock, flags);
get_res = list_empty(&chan->ctx_list);
list_add_tail(&ctx->list, &chan->ctx_list);
spin_unlock_irqrestore(&chan->irqlock, flags);
if (get_res) {
ret = get_ipu_resources(chan);
if (ret)
goto out_free_dmabuf1;
}
return ctx;
out_free_dmabuf1:
free_dma_buf(priv, &ctx->rot_intermediate[1]);
spin_lock_irqsave(&chan->irqlock, flags);
list_del(&ctx->list);
spin_unlock_irqrestore(&chan->irqlock, flags);
out_free_dmabuf0:
free_dma_buf(priv, &ctx->rot_intermediate[0]);
out_free:
kfree(ctx);
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(ipu_image_convert_prepare);
/*
* Carry out a single image conversion run. Only the physaddr's of the input
* and output image buffers are needed. The conversion context must have
* been created previously with ipu_image_convert_prepare().
*/
int ipu_image_convert_queue(struct ipu_image_convert_run *run)
{
struct ipu_image_convert_chan *chan;
struct ipu_image_convert_priv *priv;
struct ipu_image_convert_ctx *ctx;
unsigned long flags;
int ret = 0;
if (!run || !run->ctx || !run->in_phys || !run->out_phys)
return -EINVAL;
ctx = run->ctx;
chan = ctx->chan;
priv = chan->priv;
dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p run %p\n", __func__,
chan->ic_task, ctx, run);
INIT_LIST_HEAD(&run->list);
spin_lock_irqsave(&chan->irqlock, flags);
if (ctx->aborting) {
ret = -EIO;
goto unlock;
}
list_add_tail(&run->list, &chan->pending_q);
if (!chan->current_run) {
ret = do_run(run);
if (ret)
chan->current_run = NULL;
}
unlock:
spin_unlock_irqrestore(&chan->irqlock, flags);
return ret;
}
EXPORT_SYMBOL_GPL(ipu_image_convert_queue);
/* Abort any active or pending conversions for this context */
void ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx)
{
struct ipu_image_convert_chan *chan = ctx->chan;
struct ipu_image_convert_priv *priv = chan->priv;
struct ipu_image_convert_run *run, *active_run, *tmp;
unsigned long flags;
int run_count, ret;
bool need_abort;
reinit_completion(&ctx->aborted);
spin_lock_irqsave(&chan->irqlock, flags);
/* move all remaining pending runs in this context to done_q */
list_for_each_entry_safe(run, tmp, &chan->pending_q, list) {
if (run->ctx != ctx)
continue;
run->status = -EIO;
list_move_tail(&run->list, &chan->done_q);
}
run_count = get_run_count(ctx, &chan->done_q);
active_run = (chan->current_run && chan->current_run->ctx == ctx) ?
chan->current_run : NULL;
need_abort = (run_count || active_run);
ctx->aborting = need_abort;
spin_unlock_irqrestore(&chan->irqlock, flags);
if (!need_abort) {
dev_dbg(priv->ipu->dev,
"%s: task %u: no abort needed for ctx %p\n",
__func__, chan->ic_task, ctx);
return;
}
dev_dbg(priv->ipu->dev,
"%s: task %u: wait for completion: %d runs, active run %p\n",
__func__, chan->ic_task, run_count, active_run);
ret = wait_for_completion_timeout(&ctx->aborted,
msecs_to_jiffies(10000));
if (ret == 0) {
dev_warn(priv->ipu->dev, "%s: timeout\n", __func__);
force_abort(ctx);
}
ctx->aborting = false;
}
EXPORT_SYMBOL_GPL(ipu_image_convert_abort);
/* Unprepare image conversion context */
void ipu_image_convert_unprepare(struct ipu_image_convert_ctx *ctx)
{
struct ipu_image_convert_chan *chan = ctx->chan;
struct ipu_image_convert_priv *priv = chan->priv;
unsigned long flags;
bool put_res;
/* make sure no runs are hanging around */
ipu_image_convert_abort(ctx);
dev_dbg(priv->ipu->dev, "%s: task %u: removing ctx %p\n", __func__,
chan->ic_task, ctx);
spin_lock_irqsave(&chan->irqlock, flags);
list_del(&ctx->list);
put_res = list_empty(&chan->ctx_list);
spin_unlock_irqrestore(&chan->irqlock, flags);
if (put_res)
release_ipu_resources(chan);
free_dma_buf(priv, &ctx->rot_intermediate[1]);
free_dma_buf(priv, &ctx->rot_intermediate[0]);
kfree(ctx);
}
EXPORT_SYMBOL_GPL(ipu_image_convert_unprepare);
/*
* "Canned" asynchronous single image conversion. Allocates and returns
* a new conversion run. On successful return the caller must free the
* run and call ipu_image_convert_unprepare() after conversion completes.
*/
struct ipu_image_convert_run *
ipu_image_convert(struct ipu_soc *ipu, enum ipu_ic_task ic_task,
struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode,
ipu_image_convert_cb_t complete,
void *complete_context)
{
struct ipu_image_convert_ctx *ctx;
struct ipu_image_convert_run *run;
int ret;
ctx = ipu_image_convert_prepare(ipu, ic_task, in, out, rot_mode,
complete, complete_context);
if (IS_ERR(ctx))
return ERR_PTR(PTR_ERR(ctx));
run = kzalloc(sizeof(*run), GFP_KERNEL);
if (!run) {
ipu_image_convert_unprepare(ctx);
return ERR_PTR(-ENOMEM);
}
run->ctx = ctx;
run->in_phys = in->phys0;
run->out_phys = out->phys0;
ret = ipu_image_convert_queue(run);
if (ret) {
ipu_image_convert_unprepare(ctx);
kfree(run);
return ERR_PTR(ret);
}
return run;
}
EXPORT_SYMBOL_GPL(ipu_image_convert);
/* "Canned" synchronous single image conversion */
static void image_convert_sync_complete(struct ipu_image_convert_run *run,
void *data)
{
struct completion *comp = data;
complete(comp);
}
int ipu_image_convert_sync(struct ipu_soc *ipu, enum ipu_ic_task ic_task,
struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode)
{
struct ipu_image_convert_run *run;
struct completion comp;
int ret;
init_completion(&comp);
run = ipu_image_convert(ipu, ic_task, in, out, rot_mode,
image_convert_sync_complete, &comp);
if (IS_ERR(run))
return PTR_ERR(run);
ret = wait_for_completion_timeout(&comp, msecs_to_jiffies(10000));
ret = (ret == 0) ? -ETIMEDOUT : 0;
ipu_image_convert_unprepare(run->ctx);
kfree(run);
return ret;
}
EXPORT_SYMBOL_GPL(ipu_image_convert_sync);
int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev)
{
struct ipu_image_convert_priv *priv;
int i;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
ipu->image_convert_priv = priv;
priv->ipu = ipu;
for (i = 0; i < IC_NUM_TASKS; i++) {
struct ipu_image_convert_chan *chan = &priv->chan[i];
chan->ic_task = i;
chan->priv = priv;
chan->dma_ch = &image_convert_dma_chan[i];
chan->out_eof_irq = -1;
chan->rot_out_eof_irq = -1;
spin_lock_init(&chan->irqlock);
INIT_LIST_HEAD(&chan->ctx_list);
INIT_LIST_HEAD(&chan->pending_q);
INIT_LIST_HEAD(&chan->done_q);
}
return 0;
}
void ipu_image_convert_exit(struct ipu_soc *ipu)
{
}
drivers/gpu/ipu-v3/ipu-prv.h
View file @ 26e34d2d
......@@ -75,6 +75,33 @@ struct ipu_soc;
#define IPU_INT_CTRL(n) IPU_CM_REG(0x003C + 4 * (n))
#define IPU_INT_STAT(n) IPU_CM_REG(0x0200 + 4 * (n))
/* FS_PROC_FLOW1 */
#define FS_PRPENC_ROT_SRC_SEL_MASK (0xf << 0)
#define FS_PRPENC_ROT_SRC_SEL_ENC (0x7 << 0)
#define FS_PRPVF_ROT_SRC_SEL_MASK (0xf << 8)
#define FS_PRPVF_ROT_SRC_SEL_VF (0x8 << 8)
#define FS_PP_SRC_SEL_MASK (0xf << 12)
#define FS_PP_ROT_SRC_SEL_MASK (0xf << 16)
#define FS_PP_ROT_SRC_SEL_PP (0x5 << 16)
#define FS_VDI1_SRC_SEL_MASK (0x3 << 20)
#define FS_VDI3_SRC_SEL_MASK (0x3 << 20)
#define FS_PRP_SRC_SEL_MASK (0xf << 24)
#define FS_VDI_SRC_SEL_MASK (0x3 << 28)
#define FS_VDI_SRC_SEL_CSI_DIRECT (0x1 << 28)
#define FS_VDI_SRC_SEL_VDOA (0x2 << 28)
/* FS_PROC_FLOW2 */
#define FS_PRP_ENC_DEST_SEL_MASK (0xf << 0)
#define FS_PRP_ENC_DEST_SEL_IRT_ENC (0x1 << 0)
#define FS_PRPVF_DEST_SEL_MASK (0xf << 4)
#define FS_PRPVF_DEST_SEL_IRT_VF (0x1 << 4)
#define FS_PRPVF_ROT_DEST_SEL_MASK (0xf << 8)
#define FS_PP_DEST_SEL_MASK (0xf << 12)
#define FS_PP_DEST_SEL_IRT_PP (0x3 << 12)
#define FS_PP_ROT_DEST_SEL_MASK (0xf << 16)
#define FS_PRPENC_ROT_DEST_SEL_MASK (0xf << 20)
#define FS_PRP_DEST_SEL_MASK (0xf << 24)
#define IPU_DI0_COUNTER_RELEASE (1 << 24)
#define IPU_DI1_COUNTER_RELEASE (1 << 25)
......@@ -138,6 +165,8 @@ struct ipu_dc_priv;
struct ipu_dmfc_priv;
struct ipu_di;
struct ipu_ic_priv;
struct ipu_vdi;
struct ipu_image_convert_priv;
struct ipu_smfc_priv;
struct ipu_devtype;
......@@ -170,6 +199,8 @@ struct ipu_soc {
struct ipu_di *di_priv[2];
struct ipu_csi *csi_priv[2];
struct ipu_ic_priv *ic_priv;
struct ipu_vdi *vdi_priv;
struct ipu_image_convert_priv *image_convert_priv;
struct ipu_smfc_priv *smfc_priv;
};
......@@ -200,6 +231,13 @@ int ipu_ic_init(struct ipu_soc *ipu, struct device *dev,
unsigned long base, unsigned long tpmem_base);
void ipu_ic_exit(struct ipu_soc *ipu);
int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev,
unsigned long base, u32 module);
void ipu_vdi_exit(struct ipu_soc *ipu);
int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev);
void ipu_image_convert_exit(struct ipu_soc *ipu);
int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
unsigned long base, u32 module, struct clk *ipu_clk);
void ipu_di_exit(struct ipu_soc *ipu, int id);
......
drivers/gpu/ipu-v3/ipu-vdi.c 0 → 100644
View file @ 26e34d2d
/*
* Copyright (C) 2012-2016 Mentor Graphics Inc.
* Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include <linux/io.h>
#include "ipu-prv.h"
struct ipu_vdi {
void __iomem *base;
u32 module;
spinlock_t lock;
int use_count;
struct ipu_soc *ipu;
};
/* VDI Register Offsets */
#define VDI_FSIZE 0x0000
#define VDI_C 0x0004
/* VDI Register Fields */
#define VDI_C_CH_420 (0 << 1)
#define VDI_C_CH_422 (1 << 1)
#define VDI_C_MOT_SEL_MASK (0x3 << 2)
#define VDI_C_MOT_SEL_FULL (2 << 2)
#define VDI_C_MOT_SEL_LOW (1 << 2)
#define VDI_C_MOT_SEL_MED (0 << 2)
#define VDI_C_BURST_SIZE1_4 (3 << 4)
#define VDI_C_BURST_SIZE2_4 (3 << 8)
#define VDI_C_BURST_SIZE3_4 (3 << 12)
#define VDI_C_BURST_SIZE_MASK 0xF
#define VDI_C_BURST_SIZE1_OFFSET 4
#define VDI_C_BURST_SIZE2_OFFSET 8
#define VDI_C_BURST_SIZE3_OFFSET 12
#define VDI_C_VWM1_SET_1 (0 << 16)
#define VDI_C_VWM1_SET_2 (1 << 16)
#define VDI_C_VWM1_CLR_2 (1 << 19)
#define VDI_C_VWM3_SET_1 (0 << 22)
#define VDI_C_VWM3_SET_2 (1 << 22)
#define VDI_C_VWM3_CLR_2 (1 << 25)
#define VDI_C_TOP_FIELD_MAN_1 (1 << 30)
#define VDI_C_TOP_FIELD_AUTO_1 (1 << 31)
static inline u32 ipu_vdi_read(struct ipu_vdi *vdi, unsigned int offset)
{
return readl(vdi->base + offset);
}
static inline void ipu_vdi_write(struct ipu_vdi *vdi, u32 value,
unsigned int offset)
{
writel(value, vdi->base + offset);
}
void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field)
{
bool top_field_0 = false;
unsigned long flags;
u32 reg;
switch (field) {
case V4L2_FIELD_INTERLACED_TB:
case V4L2_FIELD_SEQ_TB:
case V4L2_FIELD_TOP:
top_field_0 = true;
break;
case V4L2_FIELD_INTERLACED_BT:
case V4L2_FIELD_SEQ_BT:
case V4L2_FIELD_BOTTOM:
top_field_0 = false;
break;
default:
top_field_0 = (std & V4L2_STD_525_60) ? true : false;
break;
}
spin_lock_irqsave(&vdi->lock, flags);
reg = ipu_vdi_read(vdi, VDI_C);
if (top_field_0)
reg &= ~VDI_C_TOP_FIELD_MAN_1;
else
reg |= VDI_C_TOP_FIELD_MAN_1;
ipu_vdi_write(vdi, reg, VDI_C);
spin_unlock_irqrestore(&vdi->lock, flags);
}
EXPORT_SYMBOL_GPL(ipu_vdi_set_field_order);
void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel)
{
unsigned long flags;
u32 reg;
spin_lock_irqsave(&vdi->lock, flags);
reg = ipu_vdi_read(vdi, VDI_C);
reg &= ~VDI_C_MOT_SEL_MASK;
switch (motion_sel) {
case MED_MOTION:
reg |= VDI_C_MOT_SEL_MED;
break;
case HIGH_MOTION:
reg |= VDI_C_MOT_SEL_FULL;
break;
default:
reg |= VDI_C_MOT_SEL_LOW;
break;
}
ipu_vdi_write(vdi, reg, VDI_C);
spin_unlock_irqrestore(&vdi->lock, flags);
}
EXPORT_SYMBOL_GPL(ipu_vdi_set_motion);
void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres)
{
unsigned long flags;
u32 pixel_fmt, reg;
spin_lock_irqsave(&vdi->lock, flags);
reg = ((yres - 1) << 16) | (xres - 1);
ipu_vdi_write(vdi, reg, VDI_FSIZE);
/*
* Full motion, only vertical filter is used.
* Burst size is 4 accesses
*/
if (code == MEDIA_BUS_FMT_UYVY8_2X8 ||
code == MEDIA_BUS_FMT_UYVY8_1X16 ||
code == MEDIA_BUS_FMT_YUYV8_2X8 ||
code == MEDIA_BUS_FMT_YUYV8_1X16)
pixel_fmt = VDI_C_CH_422;
else
pixel_fmt = VDI_C_CH_420;
reg = ipu_vdi_read(vdi, VDI_C);
reg |= pixel_fmt;
reg |= VDI_C_BURST_SIZE2_4;
reg |= VDI_C_BURST_SIZE1_4 | VDI_C_VWM1_CLR_2;
reg |= VDI_C_BURST_SIZE3_4 | VDI_C_VWM3_CLR_2;
ipu_vdi_write(vdi, reg, VDI_C);
spin_unlock_irqrestore(&vdi->lock, flags);
}
EXPORT_SYMBOL_GPL(ipu_vdi_setup);
void ipu_vdi_unsetup(struct ipu_vdi *vdi)
{
unsigned long flags;
spin_lock_irqsave(&vdi->lock, flags);
ipu_vdi_write(vdi, 0, VDI_FSIZE);
ipu_vdi_write(vdi, 0, VDI_C);
spin_unlock_irqrestore(&vdi->lock, flags);
}
EXPORT_SYMBOL_GPL(ipu_vdi_unsetup);
int ipu_vdi_enable(struct ipu_vdi *vdi)
{
unsigned long flags;
spin_lock_irqsave(&vdi->lock, flags);
if (!vdi->use_count)
ipu_module_enable(vdi->ipu, vdi->module);
vdi->use_count++;
spin_unlock_irqrestore(&vdi->lock, flags);
return 0;
}
EXPORT_SYMBOL_GPL(ipu_vdi_enable);
int ipu_vdi_disable(struct ipu_vdi *vdi)
{
unsigned long flags;
spin_lock_irqsave(&vdi->lock, flags);
if (vdi->use_count) {
if (!--vdi->use_count)
ipu_module_disable(vdi->ipu, vdi->module);
}
spin_unlock_irqrestore(&vdi->lock, flags);
return 0;
}
EXPORT_SYMBOL_GPL(ipu_vdi_disable);
struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu)
{
return ipu->vdi_priv;
}
EXPORT_SYMBOL_GPL(ipu_vdi_get);
void ipu_vdi_put(struct ipu_vdi *vdi)
{
}
EXPORT_SYMBOL_GPL(ipu_vdi_put);
int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev,
unsigned long base, u32 module)
{
struct ipu_vdi *vdi;
vdi = devm_kzalloc(dev, sizeof(*vdi), GFP_KERNEL);
if (!vdi)
return -ENOMEM;
ipu->vdi_priv = vdi;
spin_lock_init(&vdi->lock);
vdi->module = module;
vdi->base = devm_ioremap(dev, base, PAGE_SIZE);
if (!vdi->base)
return -ENOMEM;
dev_dbg(dev, "VDI base: 0x%08lx remapped to %p\n", base, vdi->base);
vdi->ipu = ipu;
return 0;
}
void ipu_vdi_exit(struct ipu_soc *ipu)
{
}
include/video/imx-ipu-image-convert.h 0 → 100644
View file @ 26e34d2d
/*
* Copyright (C) 2012-2016 Mentor Graphics Inc.
*
* i.MX Queued image conversion support, with tiling and rotation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#ifndef __IMX_IPU_IMAGE_CONVERT_H__
#define __IMX_IPU_IMAGE_CONVERT_H__
#include <video/imx-ipu-v3.h>
struct ipu_image_convert_ctx;
/**
* struct ipu_image_convert_run - image conversion run request struct
*
* @ctx: the conversion context
* @in_phys: dma addr of input image buffer for this run
* @out_phys: dma addr of output image buffer for this run
* @status: completion status of this run
*/
struct ipu_image_convert_run {
struct ipu_image_convert_ctx *ctx;
dma_addr_t in_phys;
dma_addr_t out_phys;
int status;
/* internal to image converter, callers don't touch */
struct list_head list;
};
/**
* ipu_image_convert_cb_t - conversion callback function prototype
*
* @run: the completed conversion run pointer
* @ctx: a private context pointer for the callback
*/
typedef void (*ipu_image_convert_cb_t)(struct ipu_image_convert_run *run,
void *ctx);
/**
* ipu_image_convert_enum_format() - enumerate the image converter's
* supported input and output pixel formats.
*
* @index: pixel format index
* @fourcc: v4l2 fourcc for this index
*
* Returns 0 with a valid index and fills in v4l2 fourcc, -EINVAL otherwise.
*
* In V4L2, drivers can call ipu_image_enum_format() in .enum_fmt.
*/
int ipu_image_convert_enum_format(int index, u32 *fourcc);
/**
* ipu_image_convert_adjust() - adjust input/output images to IPU restrictions.
*
* @in: input image format, adjusted on return
* @out: output image format, adjusted on return
* @rot_mode: rotation mode
*
* In V4L2, drivers can call ipu_image_convert_adjust() in .try_fmt.
*/
void ipu_image_convert_adjust(struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode);
/**
* ipu_image_convert_verify() - verify that input/output image formats
* and rotation mode meet IPU restrictions.
*
* @in: input image format
* @out: output image format
* @rot_mode: rotation mode
*
* Returns 0 if the formats and rotation mode meet IPU restrictions,
* -EINVAL otherwise.
*/
int ipu_image_convert_verify(struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode);
/**
* ipu_image_convert_prepare() - prepare a conversion context.
*
* @ipu: the IPU handle to use for the conversions
* @ic_task: the IC task to use for the conversions
* @in: input image format
* @out: output image format
* @rot_mode: rotation mode
* @complete: run completion callback
* @complete_context: a context pointer for the completion callback
*
* Returns an opaque conversion context pointer on success, error pointer
* on failure. The input/output formats and rotation mode must already meet
* IPU retrictions.
*
* In V4L2, drivers should call ipu_image_convert_prepare() at streamon.
*/
struct ipu_image_convert_ctx *
ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task,
struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode,
ipu_image_convert_cb_t complete,
void *complete_context);
/**
* ipu_image_convert_unprepare() - unprepare a conversion context.
*
* @ctx: the conversion context pointer to unprepare
*
* Aborts any active or pending conversions for this context and
* frees the context. Any currently active or pending runs belonging
* to this context are returned via the completion callback with an
* error run status.
*
* In V4L2, drivers should call ipu_image_convert_unprepare() at
* streamoff.
*/
void ipu_image_convert_unprepare(struct ipu_image_convert_ctx *ctx);
/**
* ipu_image_convert_queue() - queue a conversion run
*
* @run: the run request pointer
*
* ipu_image_convert_run must be dynamically allocated (_not_ as a local
* var) by callers and filled in with a previously prepared conversion
* context handle and the dma addr's of the input and output image buffers
* for this conversion run.
*
* When this conversion completes, the run pointer is returned via the
* completion callback. The caller is responsible for freeing the run
* object after it completes.
*
* In V4L2, drivers should call ipu_image_convert_queue() while
* streaming to queue the conversion of a received input buffer.
* For example mem2mem devices this would be called in .device_run.
*/
int ipu_image_convert_queue(struct ipu_image_convert_run *run);
/**
* ipu_image_convert_abort() - abort conversions
*
* @ctx: the conversion context pointer
*
* This will abort any active or pending conversions for this context.
* Any currently active or pending runs belonging to this context are
* returned via the completion callback with an error run status.
*/
void ipu_image_convert_abort(struct ipu_image_convert_ctx *ctx);
/**
* ipu_image_convert() - asynchronous image conversion request
*
* @ipu: the IPU handle to use for the conversion
* @ic_task: the IC task to use for the conversion
* @in: input image format
* @out: output image format
* @rot_mode: rotation mode
* @complete: run completion callback
* @complete_context: a context pointer for the completion callback
*
* Request a single image conversion. Returns the run that has been queued.
* A conversion context is automatically created and is available in run->ctx.
* As with ipu_image_convert_prepare(), the input/output formats and rotation
* mode must already meet IPU retrictions.
*
* On successful return the caller can queue more run requests if needed, using
* the prepared context in run->ctx. The caller is responsible for unpreparing
* the context when no more conversion requests are needed.
*/
struct ipu_image_convert_run *
ipu_image_convert(struct ipu_soc *ipu, enum ipu_ic_task ic_task,
struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode,
ipu_image_convert_cb_t complete,
void *complete_context);
/**
* ipu_image_convert_sync() - synchronous single image conversion request
*
* @ipu: the IPU handle to use for the conversion
* @ic_task: the IC task to use for the conversion
* @in: input image format
* @out: output image format
* @rot_mode: rotation mode
*
* Carry out a single image conversion. Returns when the conversion
* completes. The input/output formats and rotation mode must already
* meet IPU retrictions. The created context is automatically unprepared
* and the run freed on return.
*/
int ipu_image_convert_sync(struct ipu_soc *ipu, enum ipu_ic_task ic_task,
struct ipu_image *in, struct ipu_image *out,
enum ipu_rotate_mode rot_mode);
#endif /* __IMX_IPU_IMAGE_CONVERT_H__ */
include/video/imx-ipu-v3.h
View file @ 26e34d2d
......@@ -63,23 +63,41 @@ enum ipu_csi_dest {
/*
* Enumeration of IPU rotation modes
*/
#define IPU_ROT_BIT_VFLIP (1 << 0)
#define IPU_ROT_BIT_HFLIP (1 << 1)
#define IPU_ROT_BIT_90 (1 << 2)
enum ipu_rotate_mode {
IPU_ROTATE_NONE = 0,
IPU_ROTATE_VERT_FLIP,
IPU_ROTATE_HORIZ_FLIP,
IPU_ROTATE_180,
IPU_ROTATE_90_RIGHT,
IPU_ROTATE_90_RIGHT_VFLIP,
IPU_ROTATE_90_RIGHT_HFLIP,
IPU_ROTATE_90_LEFT,
IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP,
IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP,
IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90,
IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP),
IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP),
IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 |
IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
};
/* 90-degree rotations require the IRT unit */
#define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0)
enum ipu_color_space {
IPUV3_COLORSPACE_RGB,
IPUV3_COLORSPACE_YUV,
IPUV3_COLORSPACE_UNKNOWN,
};
/*
* Enumeration of VDI MOTION select
*/
enum ipu_motion_sel {
MOTION_NONE = 0,
LOW_MOTION,
MED_MOTION,
HIGH_MOTION,
};
struct ipuv3_channel;
enum ipu_channel_irq {
......@@ -97,6 +115,14 @@ enum ipu_channel_irq {
#define IPUV3_CHANNEL_CSI2 2
#define IPUV3_CHANNEL_CSI3 3
#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
/*
* NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels,
* but the direct CSI->VDI linking is handled the same way as IDMAC
* channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so
* these channel names are used to support the direct CSI->VDI link.
*/
#define IPUV3_CHANNEL_CSI_DIRECT 6
#define IPUV3_CHANNEL_CSI_VDI_PREV 7
#define IPUV3_CHANNEL_MEM_VDI_PREV 8
#define IPUV3_CHANNEL_MEM_VDI_CUR 9
#define IPUV3_CHANNEL_MEM_VDI_NEXT 10
......@@ -133,6 +159,7 @@ enum ipu_channel_irq {
#define IPUV3_CHANNEL_ROT_PP_MEM 50
#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
#define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52
#define IPUV3_NUM_CHANNELS 64
int ipu_map_irq(struct ipu_soc *ipu, int irq);
int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
......@@ -176,6 +203,10 @@ int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);
int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);
/*
* IPU Channel Parameter Memory (cpmem) functions
......@@ -334,6 +365,19 @@ struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
void ipu_ic_put(struct ipu_ic *ic);
void ipu_ic_dump(struct ipu_ic *ic);
/*
* IPU Video De-Interlacer (vdi) functions
*/
struct ipu_vdi;
void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field);
void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel);
void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres);
void ipu_vdi_unsetup(struct ipu_vdi *vdi);
int ipu_vdi_enable(struct ipu_vdi *vdi);
int ipu_vdi_disable(struct ipu_vdi *vdi);
struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu);
void ipu_vdi_put(struct ipu_vdi *vdi);
/*
* IPU Sensor Multiple FIFO Controller (SMFC) functions
*/
......
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