Skip to content

L
linux
Commit 2a790ca1 authored by Tom Rini's avatar Tom Rini
Browse files
Options

PPC32: Update the Motorola PowerPlus family support. 

From Randy Vinson <rvinson@mvista.com>
parent bddd7645
Show whitespace changes
Inline Side-by-side
Showing with 1290 additions and 653 deletions
arch/ppc/Kconfig
View file @ 2a790ca1
......@@ -609,7 +609,7 @@ config PPC_OF
config PPC_GEN550
bool
depends on SANDPOINT || MCPN765 || SPRUCE
depends on SANDPOINT || MCPN765 || SPRUCE || PPLUS
default y
config FORCE
......
arch/ppc/configs/pplus_defconfig
View file @ 2a790ca1
......@@ -4,11 +4,17 @@
CONFIG_MMU=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_HAVE_DEC_LOCK=y
CONFIG_PPC=y
CONFIG_PPC32=y
CONFIG_GENERIC_NVRAM=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_CLEAN_COMPILE=y
CONFIG_STANDALONE=y
CONFIG_BROKEN_ON_SMP=y
#
# General setup
......@@ -18,9 +24,16 @@ CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
# CONFIG_HOTPLUG is not set
# CONFIG_IKCONFIG is not set
CONFIG_EMBEDDED=y
CONFIG_KALLSYMS=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
#
# Loadable module support
......@@ -33,24 +46,25 @@ CONFIG_OBSOLETE_MODPARM=y
CONFIG_KMOD=y
#
# Platform support
# Processor
#
CONFIG_PPC=y
CONFIG_PPC32=y
CONFIG_6xx=y
# CONFIG_40x is not set
# CONFIG_44x is not set
# CONFIG_POWER3 is not set
# CONFIG_POWER4 is not set
# CONFIG_8xx is not set
# CONFIG_ALTIVEC is not set
# CONFIG_TAU is not set
# CONFIG_CPU_FREQ is not set
CONFIG_PPC_STD_MMU=y
#
# IBM 4xx options
# Platform options
#
# CONFIG_8260 is not set
CONFIG_GENERIC_ISA_DMA=y
CONFIG_PPC_STD_MMU=y
# CONFIG_PPC_MULTIPLATFORM is not set
# CONFIG_APUS is not set
# CONFIG_WILLOW_2 is not set
# CONFIG_WILLOW is not set
# CONFIG_PCORE is not set
# CONFIG_POWERPMC250 is not set
# CONFIG_EV64260 is not set
......@@ -66,34 +80,29 @@ CONFIG_PPLUS=y
# CONFIG_K2 is not set
# CONFIG_PAL4 is not set
# CONFIG_GEMINI is not set
# CONFIG_EST8260 is not set
# CONFIG_SBS8260 is not set
# CONFIG_RPX6 is not set
# CONFIG_TQM8260 is not set
CONFIG_PPC_GEN550=y
# CONFIG_PPCBUG_NVRAM is not set
# CONFIG_SMP is not set
# CONFIG_PREEMPT is not set
# CONFIG_ALTIVEC is not set
# CONFIG_TAU is not set
# CONFIG_CPU_FREQ is not set
# CONFIG_HIGHMEM is not set
CONFIG_KERNEL_ELF=y
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="ip=on"
#
# General setup
# Bus options
#
# CONFIG_HIGHMEM is not set
CONFIG_GENERIC_ISA_DMA=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
CONFIG_KERNEL_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_PCI_LEGACY_PROC is not set
# CONFIG_PCI_NAMES is not set
# CONFIG_HOTPLUG is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
CONFIG_PPC601_SYNC_FIX=y
# CONFIG_PPCBUG_NVRAM is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="ip=on"
#
# Advanced setup
......@@ -109,15 +118,27 @@ CONFIG_KERNEL_START=0xc0000000
CONFIG_TASK_SIZE=0x80000000
CONFIG_BOOT_LOAD=0x00800000
#
# Device Drivers
#
#
# Generic Driver Options
#
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Block devices
......@@ -131,43 +152,42 @@ CONFIG_BLK_DEV_FD=y
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_LBD is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# ATA/IDE/MFM/RLL support
# ATA/ATAPI/MFM/RLL support
#
CONFIG_IDE=y
#
# IDE, ATA and ATAPI Block devices
#
CONFIG_BLK_DEV_IDE=y
#
# Please see Documentation/ide.txt for help/info on IDE drives
#
# CONFIG_BLK_DEV_HD is not set
CONFIG_BLK_DEV_IDEDISK=y
# CONFIG_IDEDISK_MULTI_MODE is not set
# CONFIG_IDEDISK_STROKE is not set
CONFIG_BLK_DEV_IDECD=y
# CONFIG_BLK_DEV_IDETAPE is not set
CONFIG_BLK_DEV_IDEFLOPPY=y
CONFIG_BLK_DEV_IDESCSI=y
# CONFIG_IDE_TASK_IOCTL is not set
# CONFIG_IDE_TASKFILE_IO is not set
#
# IDE chipset support/bugfixes
#
CONFIG_IDE_GENERIC=y
# CONFIG_BLK_DEV_IDEPCI is not set
# CONFIG_BLK_DEV_IDEDMA is not set
# CONFIG_IDEDMA_AUTO is not set
# CONFIG_DMA_NONPCI is not set
# CONFIG_BLK_DEV_HD is not set
#
# SCSI support
# SCSI device support
#
CONFIG_SCSI=y
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
......@@ -196,11 +216,9 @@ CONFIG_SCSI_CONSTANTS=y
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_IN2000 is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_MEGARAID is not set
# CONFIG_SCSI_SATA is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_CPQFCTS is not set
# CONFIG_SCSI_DMX3191D is not set
......@@ -208,39 +226,36 @@ CONFIG_SCSI_CONSTANTS=y
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_GENERIC_NCR5380 is not set
# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_NCR53C7xx is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_NCR53C8XX is not set
CONFIG_SCSI_SYM53C8XX=y
CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS=8
CONFIG_SCSI_NCR53C8XX_MAX_TAGS=32
CONFIG_SCSI_NCR53C8XX_SYNC=20
# CONFIG_SCSI_NCR53C8XX_PROFILE is not set
# CONFIG_SCSI_NCR53C8XX_IOMAPPED is not set
# CONFIG_SCSI_NCR53C8XX_PQS_PDS is not set
# CONFIG_SCSI_NCR53C8XX_SYMBIOS_COMPAT is not set
# CONFIG_SCSI_PCI2000 is not set
# CONFIG_SCSI_PCI2220I is not set
# CONFIG_SCSI_QLOGIC_ISP is not set
# CONFIG_SCSI_QLOGIC_FC is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
CONFIG_SCSI_QLA2XXX=y
# CONFIG_SCSI_QLA21XX is not set
# CONFIG_SCSI_QLA22XX is not set
# CONFIG_SCSI_QLA2300 is not set
# CONFIG_SCSI_QLA2322 is not set
# CONFIG_SCSI_QLA6312 is not set
# CONFIG_SCSI_QLA6322 is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_U14_34F is not set
# CONFIG_SCSI_NSP32 is not set
# CONFIG_SCSI_DEBUG is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support (EXPERIMENTAL)
# IEEE 1394 (FireWire) support
#
# CONFIG_IEEE1394 is not set
......@@ -249,6 +264,10 @@ CONFIG_SCSI_NCR53C8XX_SYNC=20
#
# CONFIG_I2O is not set
#
# Macintosh device drivers
#
#
# Networking support
#
......@@ -260,8 +279,6 @@ CONFIG_NET=y
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
# CONFIG_NETLINK_DEV is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
......@@ -281,6 +298,16 @@ CONFIG_SYN_COOKIES=y
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
#
# IP: Virtual Server Configuration
#
# CONFIG_IP_VS is not set
# CONFIG_IPV6 is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
#
# IP: Netfilter Configuration
#
......@@ -292,11 +319,13 @@ CONFIG_IP_NF_FTP=m
# CONFIG_IP_NF_QUEUE is not set
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_LIMIT=m
# CONFIG_IP_NF_MATCH_IPRANGE is not set
CONFIG_IP_NF_MATCH_MAC=m
CONFIG_IP_NF_MATCH_PKTTYPE=m
CONFIG_IP_NF_MATCH_MARK=m
CONFIG_IP_NF_MATCH_MULTIPORT=m
CONFIG_IP_NF_MATCH_TOS=m
# CONFIG_IP_NF_MATCH_RECENT is not set
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_DSCP=m
CONFIG_IP_NF_MATCH_AH_ESP=m
......@@ -306,15 +335,15 @@ CONFIG_IP_NF_MATCH_AH_ESP=m
CONFIG_IP_NF_MATCH_HELPER=m
CONFIG_IP_NF_MATCH_STATE=m
CONFIG_IP_NF_MATCH_CONNTRACK=m
CONFIG_IP_NF_MATCH_UNCLEAN=m
CONFIG_IP_NF_MATCH_OWNER=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_MIRROR=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_NAT_NEEDED=y
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_REDIRECT=m
# CONFIG_IP_NF_TARGET_NETMAP is not set
# CONFIG_IP_NF_TARGET_SAME is not set
# CONFIG_IP_NF_NAT_LOCAL is not set
# CONFIG_IP_NF_NAT_SNMP_BASIC is not set
CONFIG_IP_NF_NAT_FTP=m
......@@ -324,10 +353,9 @@ CONFIG_IP_NF_TARGET_ULOG=m
# CONFIG_IP_NF_TARGET_TCPMSS is not set
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
# CONFIG_IP_NF_ARP_MANGLE is not set
CONFIG_IP_NF_COMPAT_IPCHAINS=m
# CONFIG_IP_NF_COMPAT_IPFWADM is not set
# CONFIG_IPV6 is not set
# CONFIG_XFRM_USER is not set
#
# SCTP Configuration (EXPERIMENTAL)
......@@ -336,9 +364,9 @@ CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
......@@ -366,13 +394,13 @@ CONFIG_NETDEVICES=y
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_CRC32=y
# CONFIG_OAKNET is not set
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
......@@ -381,13 +409,22 @@ CONFIG_MII=y
#
# Tulip family network device support
#
# CONFIG_NET_TULIP is not set
CONFIG_NET_TULIP=y
# CONFIG_DE2104X is not set
CONFIG_TULIP=y
# CONFIG_TULIP_MWI is not set
# CONFIG_TULIP_MMIO is not set
# CONFIG_TULIP_NAPI is not set
# CONFIG_DE4X5 is not set
# CONFIG_WINBOND_840 is not set
# CONFIG_DM9102 is not set
# CONFIG_HP100 is not set
CONFIG_NET_PCI=y
# CONFIG_PCNET32 is not set
# CONFIG_AMD8111_ETH is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_B44 is not set
# CONFIG_FORCEDETH is not set
# CONFIG_DGRS is not set
CONFIG_EEPRO100=y
# CONFIG_EEPRO100_PIO is not set
......@@ -413,6 +450,7 @@ CONFIG_EEPRO100=y
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SIS190 is not set
# CONFIG_SK98LIN is not set
# CONFIG_TIGON3 is not set
......@@ -431,8 +469,9 @@ CONFIG_EEPRO100=y
# CONFIG_NET_RADIO is not set
#
# Token Ring devices (depends on LLC=y)
# Token Ring devices
#
# CONFIG_TR is not set
# CONFIG_NET_FC is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
......@@ -453,19 +492,19 @@ CONFIG_EEPRO100=y
# CONFIG_IRDA is not set
#
# ISDN subsystem
# Bluetooth support
#
# CONFIG_ISDN_BOOL is not set
# CONFIG_BT is not set
#
# Graphics support
# ISDN subsystem
#
# CONFIG_FB is not set
# CONFIG_ISDN is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
# Telephony Support
#
# CONFIG_CD_NO_IDESCSI is not set
# CONFIG_PHONE is not set
#
# Input device support
......@@ -482,18 +521,16 @@ CONFIG_EEPRO100=y
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
# CONFIG_SERIO is not set
# CONFIG_SERIO_I8042 is not set
#
# Input Device Drivers
#
#
# Macintosh device drivers
#
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
......@@ -501,6 +538,7 @@ CONFIG_SOUND_GAMEPORT=y
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
#
......@@ -509,26 +547,13 @@ CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
#
# I2C support
#
# CONFIG_I2C is not set
#
# I2C Hardware Sensors Mainboard support
#
#
# I2C Hardware Sensors Chip support
#
# CONFIG_I2C_SENSOR is not set
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
#
# Mice
#
CONFIG_BUSMOUSE=y
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
......@@ -554,7 +579,11 @@ CONFIG_GEN_RTC=y
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# Multimedia devices
......@@ -566,6 +595,26 @@ CONFIG_GEN_RTC=y
#
# CONFIG_DVB is not set
#
# Graphics support
#
# CONFIG_FB is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# File systems
#
......@@ -600,10 +649,11 @@ CONFIG_ISO9660_FS=y
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
# CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
# CONFIG_DEVPTS_FS_XATTR is not set
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
#
......@@ -628,6 +678,7 @@ CONFIG_RAMFS=y
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
......@@ -638,7 +689,6 @@ CONFIG_SUNRPC=y
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
......@@ -648,31 +698,18 @@ CONFIG_SUNRPC=y
CONFIG_MSDOS_PARTITION=y
#
# Sound
# Native Language Support
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
# CONFIG_USB_GADGET is not set
#
# Bluetooth support
#
# CONFIG_BT is not set
# CONFIG_NLS is not set
#
# Library routines
#
# CONFIG_CRC32 is not set
#
# Kernel hacking
#
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_KALLSYMS is not set
# CONFIG_SERIAL_TEXT_DEBUG is not set
#
......
arch/ppc/platforms/Makefile
View file @ 2a790ca1
......@@ -41,7 +41,7 @@ obj-$(CONFIG_MVME5100) += mvme5100_setup.o mvme5100_pci.o
obj-$(CONFIG_PAL4) += pal4_setup.o pal4_pci.o
obj-$(CONFIG_PCORE) += pcore_setup.o pcore_pci.o
obj-$(CONFIG_POWERPMC250) += powerpmc250.o
obj-$(CONFIG_PPLUS) += pplus_pci.o pplus_setup.o
obj-$(CONFIG_PPLUS) += pplus.o
obj-$(CONFIG_PRPMC750) += prpmc750_setup.o prpmc750_pci.o
obj-$(CONFIG_PRPMC800) += prpmc800_setup.o prpmc800_pci.o
obj-$(CONFIG_SANDPOINT) += sandpoint.o
......
arch/ppc/platforms/pplus_pci.c → arch/ppc/platforms/pplus.c
View file @ 2a790ca1
/*
* arch/ppc/platforms/pplus_pci.c
* arch/ppc/platforms/pplus.c
*
* PCI setup for MCG PowerPlus
* Board and PCI setup routines for MCG PowerPlus
*
* Author: Randy Vinson <rvinson@mvista.com>
*
......@@ -9,30 +9,51 @@
* Cort Dougan, Johnnie Peters, Matt Porter, and
* Troy Benjegerdes.
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/config.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/console.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/ide.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <asm/sections.h>
#include <asm/byteorder.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/ptrace.h>
#include <asm/pci-bridge.h>
#include <asm/residual.h>
#include <asm/irq.h>
#include <asm/pgtable.h>
#include <asm/dma.h>
#include <asm/machdep.h>
#include <asm/prep_nvram.h>
#include <asm/vga.h>
#include <asm/i8259.h>
#include <asm/open_pic.h>
#include <asm/pplus.h>
#include <asm/hawk.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#include <asm/kgdb.h>
#include <asm/reg.h>
#include "pplus.h"
#undef DUMP_DBATS
TODC_ALLOC();
extern char saved_command_line[];
extern void pplus_setup_hose(void);
extern void pplus_set_VIA_IDE_native(void);
extern unsigned long loops_per_jiffy;
unsigned char *Motherboard_map_name;
/* Tables for known hardware */
......@@ -49,15 +70,15 @@ mesquite_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
* A B C D
*/
{
{ 18, 0, 0, 0 }, /* IDSEL 14 - Enet 0 */
{ 0, 0, 0, 0 }, /* IDSEL 15 - unused */
{ 19, 19, 19, 19 }, /* IDSEL 16 - PMC Slot 1 */
{ 0, 0, 0, 0 }, /* IDSEL 17 - unused */
{ 0, 0, 0, 0 }, /* IDSEL 18 - unused */
{ 0, 0, 0, 0 }, /* IDSEL 19 - unused */
{ 24, 25, 26, 27 }, /* IDSEL 20 - P2P bridge (to cPCI 1) */
{ 0, 0, 0, 0 }, /* IDSEL 21 - unused */
{ 28, 29, 30, 31 } /* IDSEL 22 - P2P bridge (to cPCI 2) */
{18, 0, 0, 0}, /* IDSEL 14 - Enet 0 */
{ 0, 0, 0, 0}, /* IDSEL 15 - unused */
{19, 19, 19, 19}, /* IDSEL 16 - PMC Slot 1 */
{ 0, 0, 0, 0}, /* IDSEL 17 - unused */
{ 0, 0, 0, 0}, /* IDSEL 18 - unused */
{ 0, 0, 0, 0}, /* IDSEL 19 - unused */
{24, 25, 26, 27}, /* IDSEL 20 - P2P bridge (to cPCI 1) */
{ 0, 0, 0, 0}, /* IDSEL 21 - unused */
{28, 29, 30, 31} /* IDSEL 22 - P2P bridge (to cPCI 2) */
};
const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
......@@ -76,13 +97,13 @@ sitka_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
* A B C D
*/
{
{ 18, 0, 0, 0 }, /* IDSEL 14 - Enet 0 */
{ 0, 0, 0, 0 }, /* IDSEL 15 - unused */
{ 25, 26, 27, 28 }, /* IDSEL 16 - PMC Slot 1 */
{ 28, 25, 26, 27 }, /* IDSEL 17 - PMC Slot 2 */
{ 0, 0, 0, 0 }, /* IDSEL 18 - unused */
{ 0, 0, 0, 0 }, /* IDSEL 19 - unused */
{ 20, 0, 0, 0 } /* IDSEL 20 - P2P bridge (to cPCI) */
{18, 0, 0, 0}, /* IDSEL 14 - Enet 0 */
{ 0, 0, 0, 0}, /* IDSEL 15 - unused */
{25, 26, 27, 28}, /* IDSEL 16 - PMC Slot 1 */
{28, 25, 26, 27}, /* IDSEL 17 - PMC Slot 2 */
{ 0, 0, 0, 0}, /* IDSEL 18 - unused */
{ 0, 0, 0, 0}, /* IDSEL 19 - unused */
{20, 0, 0, 0} /* IDSEL 20 - P2P bridge (to cPCI) */
};
const long min_idsel = 14, max_idsel = 20, irqs_per_slot = 4;
......@@ -101,13 +122,13 @@ MTX_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
* A B C D
*/
{
{ 19, 0, 0, 0 }, /* IDSEL 12 - SCSI */
{ 0, 0, 0, 0 }, /* IDSEL 13 - unused */
{ 18, 0, 0, 0 }, /* IDSEL 14 - Enet */
{ 0, 0, 0, 0 }, /* IDSEL 15 - unused */
{ 25, 26, 27, 28 }, /* IDSEL 16 - PMC Slot 1 */
{ 26, 27, 28, 25 }, /* IDSEL 17 - PMC Slot 2 */
{ 27, 28, 25, 26 } /* IDSEL 18 - PCI Slot 3 */
{19, 0, 0, 0}, /* IDSEL 12 - SCSI */
{ 0, 0, 0, 0}, /* IDSEL 13 - unused */
{18, 0, 0, 0}, /* IDSEL 14 - Enet */
{ 0, 0, 0, 0}, /* IDSEL 15 - unused */
{25, 26, 27, 28}, /* IDSEL 16 - PMC Slot 1 */
{26, 27, 28, 25}, /* IDSEL 17 - PMC Slot 2 */
{27, 28, 25, 26} /* IDSEL 18 - PCI Slot 3 */
};
const long min_idsel = 12, max_idsel = 18, irqs_per_slot = 4;
......@@ -127,15 +148,15 @@ MTXplus_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
* A B C D
*/
{
{ 19, 0, 0, 0 }, /* IDSEL 12 - SCSI */
{ 0, 0, 0, 0 }, /* IDSEL 13 - unused */
{ 18, 0, 0, 0 }, /* IDSEL 14 - Enet 1 */
{ 0, 0, 0, 0 }, /* IDSEL 15 - unused */
{ 25, 26, 27, 28 }, /* IDSEL 16 - PCI Slot 1P */
{ 26, 27, 28, 25 }, /* IDSEL 17 - PCI Slot 2P */
{ 27, 28, 25, 26 }, /* IDSEL 18 - PCI Slot 3P */
{ 26, 0, 0, 0 }, /* IDSEL 19 - Enet 2 */
{ 0, 0, 0, 0 } /* IDSEL 20 - P2P Bridge */
{19, 0, 0, 0}, /* IDSEL 12 - SCSI */
{ 0, 0, 0, 0}, /* IDSEL 13 - unused */
{18, 0, 0, 0}, /* IDSEL 14 - Enet 1 */
{ 0, 0, 0, 0}, /* IDSEL 15 - unused */
{25, 26, 27, 28}, /* IDSEL 16 - PCI Slot 1P */
{26, 27, 28, 25}, /* IDSEL 17 - PCI Slot 2P */
{27, 28, 25, 26}, /* IDSEL 18 - PCI Slot 3P */
{26, 0, 0, 0}, /* IDSEL 19 - Enet 2 */
{ 0, 0, 0, 0} /* IDSEL 20 - P2P Bridge */
};
const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
......@@ -186,15 +207,15 @@ Genesis2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
* A B C D
*/
{
{ 19, 0, 0, 0 }, /* IDSEL 12 - SCSI */
{ 0, 0, 0, 0 }, /* IDSEL 13 - Universe PCI - VME */
{ 18, 0, 0, 0 }, /* IDSEL 14 - Enet 1 */
{ 0, 0, 0, 0 }, /* IDSEL 15 - unused */
{ 25, 26, 27, 28 }, /* IDSEL 16 - PCI/PMC Slot 1P */
{ 28, 25, 26, 27 }, /* IDSEL 17 - PCI/PMC Slot 2P */
{ 27, 28, 25, 26 }, /* IDSEL 18 - PCI Slot 3P */
{ 26, 0, 0, 0 }, /* IDSEL 19 - Enet 2 */
{ 25, 26, 27, 28 } /* IDSEL 20 - P2P Bridge */
{19, 0, 0, 0}, /* IDSEL 12 - SCSI */
{ 0, 0, 0, 0}, /* IDSEL 13 - Universe PCI - VME */
{18, 0, 0, 0}, /* IDSEL 14 - Enet 1 */
{ 0, 0, 0, 0}, /* IDSEL 15 - unused */
{25, 26, 27, 28}, /* IDSEL 16 - PCI/PMC Slot 1P */
{28, 25, 26, 27}, /* IDSEL 17 - PCI/PMC Slot 2P */
{27, 28, 25, 26}, /* IDSEL 18 - PCI Slot 3P */
{26, 0, 0, 0}, /* IDSEL 19 - Enet 2 */
{25, 26, 27, 28} /* IDSEL 20 - P2P Bridge */
};
const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
......@@ -208,65 +229,38 @@ Genesis2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
#define MOT_PROC2_BIT 0x800
static u_char pplus_openpic_initsenses[] __initdata = {
1, /* MVME2600_INT_SIO */
0, /* MVME2600_INT_FALCN_ECC_ERR */
1, /* MVME2600_INT_PCI_ETHERNET */
1, /* MVME2600_INT_PCI_SCSI */
1, /* MVME2600_INT_PCI_GRAPHICS */
1, /* MVME2600_INT_PCI_VME0 */
1, /* MVME2600_INT_PCI_VME1 */
1, /* MVME2600_INT_PCI_VME2 */
1, /* MVME2600_INT_PCI_VME3 */
1, /* MVME2600_INT_PCI_INTA */
1, /* MVME2600_INT_PCI_INTB */
1, /* MVME2600_INT_PCI_INTC */
1, /* MVME2600_INT_PCI_INTD */
1, /* MVME2600_INT_LM_SIG0 */
1, /* MVME2600_INT_LM_SIG1 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */
(IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_FALCN_ECC_ERR */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_ETHERNET */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_GRAPHICS */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),
};
int mot_entry = -1;
int prep_keybd_present = 1;
int mot_multi = 0;
int __init raven_init(void)
{
unsigned short devid;
unsigned char base_mod;
/* set the MPIC base address */
early_write_config_dword(0, 0, 0, PCI_BASE_ADDRESS_1, 0x3cfc0000);
pplus_mpic_init(PREP_ISA_MEM_BASE);
OpenPIC_InitSenses = pplus_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(pplus_openpic_initsenses);
ppc_md.get_irq = openpic_get_irq;
/* This is a hack. If this is a 2300 or 2400 mot board then there is
* no keyboard controller and we have to indicate that.
*/
early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
base_mod = inb(MOTOROLA_BASETYPE_REG);
if ((devid == PCI_DEVICE_ID_MOTOROLA_HAWK) ||
(base_mod == 0xF9) ||
(base_mod == 0xFA) || (base_mod == 0xE1))
prep_keybd_present = 0;
return 1;
}
struct brd_info {
int cpu_type; /* 0x100 mask assumes for Raven and Hawk boards that the level/edge are set */
/* 0x100 mask assumes for Raven and Hawk boards that the level/edge
* are set */
int cpu_type;
/* 0x200 if this board has a Hawk chip. */
int base_type;
int max_cpu; /* ored with 0x80 if this board should be checked for multi CPU */
/* or'ed with 0x80 if this board should be checked for multi CPU */
int max_cpu;
const char *name;
int (*map_irq)(struct pci_dev *,
unsigned char,
unsigned char);
int (*map_irq) (struct pci_dev *, unsigned char, unsigned char);
};
struct brd_info mot_info[] = {
{0x300, 0x00, 0x00, "MVME 2400", Genesis2_map_irq},
......@@ -303,14 +297,14 @@ void __init pplus_set_board_type(void)
early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
for (entry = 0; mot_info[entry].cpu_type != 0; entry++) {
/* Check for Hawk chip */
if (mot_info[entry].cpu_type & 0x200) {
if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK)
continue;
} else {
/* store the system config register for later use. */
ProcInfo = (unsigned long *)ioremap(0xfef80400, 4);
ProcInfo =
(unsigned long *)ioremap(PPLUS_SYS_CONFIG_REG, 4);
/* Check non hawk boards */
if ((mot_info[entry].cpu_type & 0xff) != cpu_type)
......@@ -331,33 +325,32 @@ void __init pplus_set_board_type(void)
}
/* processor 1 not present and max processor zero indicated */
if ((*ProcInfo & MOT_PROC2_BIT) && !(mot_info[entry].max_cpu & 0x7f)) {
if ((*ProcInfo & MOT_PROC2_BIT)
&& !(mot_info[entry].max_cpu & 0x7f)) {
mot_entry = entry;
break;
}
/* processor 1 present and max processor zero indicated */
if (!(*ProcInfo & MOT_PROC2_BIT) && (mot_info[entry].max_cpu & 0x7f)) {
if (!(*ProcInfo & MOT_PROC2_BIT)
&& (mot_info[entry].max_cpu & 0x7f)) {
mot_entry = entry;
break;
}
/* Indicate to system if this is a multiprocessor board */
if (!(*ProcInfo & MOT_PROC2_BIT)) {
if (!(*ProcInfo & MOT_PROC2_BIT))
mot_multi = 1;
}
}
if (mot_entry == -1)
/* No particular cpu type found - assume Mesquite (MCP750) */
mot_entry = 1;
Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name;
ppc_md.pci_map_irq = mot_info[mot_entry].map_irq;
}
void __init
pplus_pib_init(void)
void __init pplus_pib_init(void)
{
unsigned char reg;
unsigned short short_reg;
......@@ -379,15 +372,15 @@ pplus_pib_init(void)
reg |= 0x03; /* IDE: Chip Enable Bits */
pci_write_config_byte(dev, 0x40, reg);
}
if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_82C586_2,
dev)) && (dev->devfn = 0x5a)) {
/* Force correct USB interrupt */
dev->irq = 11;
pci_write_config_byte(dev,
PCI_INTERRUPT_LINE,
dev->irq);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
}
if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
PCI_DEVICE_ID_WINBOND_83C553, dev))) {
/* Clear PCI Interrupt Routing Control Register. */
......@@ -399,7 +392,7 @@ pplus_pib_init(void)
}
if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
PCI_DEVICE_ID_WINBOND_82C105, dev))){
PCI_DEVICE_ID_WINBOND_82C105, dev))) {
/*
* Disable LEGIRQ mode so PCI INTS are routed
* directly to the 8259 and enable both channels
......@@ -408,14 +401,11 @@ pplus_pib_init(void)
/* Force correct IDE interrupt */
dev->irq = 14;
pci_write_config_byte(dev,
PCI_INTERRUPT_LINE,
dev->irq);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
}
}
void __init
pplus_set_VIA_IDE_legacy(void)
void __init pplus_set_VIA_IDE_legacy(void)
{
unsigned short vend, dev;
......@@ -424,7 +414,6 @@ pplus_set_VIA_IDE_legacy(void)
if ((vend == PCI_VENDOR_ID_VIA) &&
(dev == PCI_DEVICE_ID_VIA_82C586_1)) {
unsigned char temp;
/* put back original "standard" port base addresses */
......@@ -448,8 +437,7 @@ pplus_set_VIA_IDE_legacy(void)
}
}
void
pplus_set_VIA_IDE_native(void)
void pplus_set_VIA_IDE_native(void)
{
unsigned short vend, dev;
......@@ -458,7 +446,6 @@ pplus_set_VIA_IDE_native(void)
if ((vend == PCI_VENDOR_ID_VIA) &&
(dev == PCI_DEVICE_ID_VIA_82C586_1)) {
unsigned char temp;
/* put into native mode */
......@@ -470,33 +457,40 @@ pplus_set_VIA_IDE_native(void)
}
}
void __init
pplus_pcibios_fixup(void)
void __init pplus_pcibios_fixup(void)
{
printk("Setting PCI interrupts for a \"%s\"\n", Motherboard_map_name);
unsigned char reg;
unsigned short devid;
unsigned char base_mod;
printk(KERN_INFO "Setting PCI interrupts for a \"%s\"\n",
Motherboard_map_name);
/* Setup the Winbond or Via PIB */
pplus_pib_init();
}
static void __init
pplus_init_resource(struct resource *res, unsigned long start,
unsigned long end, int flags)
{
res->flags = flags;
res->start = start;
res->end = end;
res->name = "PCI host bridge";
res->parent = NULL;
res->sibling = NULL;
res->child = NULL;
/* Set up floppy in PS/2 mode */
outb(0x09, SIO_CONFIG_RA);
reg = inb(SIO_CONFIG_RD);
reg = (reg & 0x3F) | 0x40;
outb(reg, SIO_CONFIG_RD);
outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
/* This is a hack. If this is a 2300 or 2400 mot board then there is
* no keyboard controller and we have to indicate that.
*/
early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
base_mod = inb(MOTOROLA_BASETYPE_REG);
if ((devid == PCI_DEVICE_ID_MOTOROLA_HAWK) ||
(base_mod == 0xF9) || (base_mod == 0xFA) || (base_mod == 0xE1))
prep_keybd_present = 0;
}
void __init
pplus_setup_hose(void)
void __init pplus_find_bridges(void)
{
struct pci_controller* hose;
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
......@@ -508,17 +502,25 @@ pplus_setup_hose(void)
hose->pci_mem_offset = PREP_ISA_MEM_BASE;
hose->io_base_virt = (void *)PREP_ISA_IO_BASE;
pplus_init_resource(&hose->io_resource, 0x00000000, 0x0fffffff,
IORESOURCE_IO);
pplus_init_resource(&hose->mem_resources[0], 0xc0000000, 0xfdffffff,
IORESOURCE_MEM);
pci_init_resource(&hose->io_resource, PPLUS_PCI_IO_START,
PPLUS_PCI_IO_END, IORESOURCE_IO, "PCI host bridge");
pci_init_resource(&hose->mem_resources[0], PPLUS_PROC_PCI_MEM_START,
PPLUS_PROC_PCI_MEM_END, IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = PPLUS_PCI_IO_START;
hose->io_space.end = PPLUS_PCI_IO_END;
hose->mem_space.start = PPLUS_PCI_MEM_START;
hose->mem_space.end = PPLUS_PCI_MEM_END - HAWK_MPIC_SIZE;
hose->io_space.start = 0x00000000;
hose->io_space.end = 0x0fffffff;
hose->mem_space.start = 0x00000000;
hose->mem_space.end = 0x3cfbffff; /* MPIC at 0x3cfc0000-0x3dffffff */
if (pplus_init(hose, PPLUS_HAWK_PPC_REG_BASE, PPLUS_PROC_PCI_MEM_START,
PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
PPLUS_PROC_PCI_IO_START, PPLUS_PROC_PCI_IO_END,
PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1)
!= 0) {
printk(KERN_CRIT "Could not initialize host bridge\n");
setup_indirect_pci(hose, 0x80000cf8, 0x80000cfc);
}
pplus_set_VIA_IDE_legacy();
......@@ -526,5 +528,391 @@ pplus_setup_hose(void)
ppc_md.pcibios_fixup = pplus_pcibios_fixup;
ppc_md.pci_swizzle = common_swizzle;
}
static int pplus_show_cpuinfo(struct seq_file *m)
{
seq_printf(m, "vendor\t\t: Motorola MCG\n");
seq_printf(m, "machine\t\t: %s\n", Motherboard_map_name);
return 0;
}
static void __init pplus_setup_arch(void)
{
struct pci_controller *hose;
if (ppc_md.progress)
ppc_md.progress("pplus_setup_arch: enter", 0);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000;
if (ppc_md.progress)
ppc_md.progress("pplus_setup_arch: find_bridges", 0);
/* Setup PCI host bridge */
pplus_find_bridges();
hose = pci_bus_to_hose(0);
isa_io_base = (ulong) hose->io_base_virt;
if (ppc_md.progress)
ppc_md.progress("pplus_setup_arch: set_board_type", 0);
pplus_set_board_type();
/* Enable L2. Assume we don't need to flush -- Cort */
*(unsigned char *)(PPLUS_L2_CONTROL_REG) |= 3;
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_SDA2;
#endif
printk(KERN_INFO "Motorola PowerPlus Platform\n");
printk(KERN_INFO
"Port by MontaVista Software, Inc. (source@mvista.com)\n");
#ifdef CONFIG_VGA_CONSOLE
/* remap the VGA memory */
vgacon_remap_base = (unsigned long)ioremap(PPLUS_ISA_MEM_BASE,
0x08000000);
conswitchp = &vga_con;
#elif defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
#endif
#ifdef CONFIG_PPCBUG_NVRAM
/* Read in NVRAM data */
init_prep_nvram();
/* if no bootargs, look in NVRAM */
if (cmd_line[0] == '\0') {
char *bootargs;
bootargs = prep_nvram_get_var("bootargs");
if (bootargs != NULL) {
strcpy(cmd_line, bootargs);
/* again.. */
strcpy(saved_command_line, cmd_line);
}
}
#endif
if (ppc_md.progress)
ppc_md.progress("pplus_setup_arch: exit", 0);
}
static void pplus_restart(char *cmd)
{
unsigned long i = 10000;
local_irq_disable();
/* set VIA IDE controller into native mode */
pplus_set_VIA_IDE_native();
/* set exception prefix high - to the prom */
_nmask_and_or_msr(0, MSR_IP);
/* make sure bit 0 (reset) is a 0 */
outb(inb(0x92) & ~1L, 0x92);
/* signal a reset to system control port A - soft reset */
outb(inb(0x92) | 1, 0x92);
while (i != 0)
i++;
panic("restart failed\n");
}
static void pplus_halt(void)
{
/* set exception prefix high - to the prom */
_nmask_and_or_msr(MSR_EE, MSR_IP);
/* make sure bit 0 (reset) is a 0 */
outb(inb(0x92) & ~1L, 0x92);
/* signal a reset to system control port A - soft reset */
outb(inb(0x92) | 1, 0x92);
while (1) ;
/*
* Not reached
*/
}
static void pplus_power_off(void)
{
pplus_halt();
}
static unsigned int pplus_irq_canonicalize(u_int irq)
{
if (irq == 2)
return 9;
else
return irq;
}
static void __init pplus_init_IRQ(void)
{
int i;
if (ppc_md.progress)
ppc_md.progress("init_irq: enter", 0);
OpenPIC_InitSenses = pplus_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(pplus_openpic_initsenses);
if (OpenPIC_Addr != NULL) {
openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
openpic_init(NUM_8259_INTERRUPTS);
ppc_md.get_irq = openpic_get_irq;
}
for (i = 0; i < NUM_8259_INTERRUPTS; i++)
irq_desc[i].handler = &i8259_pic;
i8259_init(0);
if (ppc_md.progress)
ppc_md.progress("init_irq: exit", 0);
}
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
/*
* IDE stuff.
*/
static int pplus_ide_default_irq(unsigned long base)
{
switch (base) {
case 0x1f0:
return 14;
case 0x170:
return 15;
default:
return 0;
}
}
static unsigned long pplus_ide_default_io_base(int index)
{
switch (index) {
case 0:
return 0x1f0;
case 1:
return 0x170;
default:
return 0;
}
}
static void __init
pplus_ide_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
unsigned long ctrl_port, int *irq)
{
unsigned long reg = data_port;
int i;
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw->io_ports[i] = reg;
reg += 1;
}
if (ctrl_port)
hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
else
hw->io_ports[IDE_CONTROL_OFFSET] =
hw->io_ports[IDE_DATA_OFFSET] + 0x206;
if (irq != NULL)
*irq = pplus_ide_default_irq(data_port);
}
#endif
#ifdef CONFIG_SMP
/* PowerPlus (MTX) support */
static int __init smp_pplus_probe(void)
{
extern int mot_multi;
if (mot_multi) {
openpic_request_IPIs();
smp_hw_index[1] = 1;
return 2;
}
return 1;
}
static void __init smp_pplus_kick_cpu(int nr)
{
*(unsigned long *)KERNELBASE = nr;
asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
printk(KERN_INFO "CPU1 reset, waiting\n");
}
static void __init smp_pplus_setup_cpu(int cpu_nr)
{
if (OpenPIC_Addr)
do_openpic_setup_cpu();
}
static struct smp_ops_t pplus_smp_ops = {
smp_openpic_message_pass,
smp_pplus_probe,
smp_pplus_kick_cpu,
smp_pplus_setup_cpu,
.give_timebase = smp_generic_give_timebase,
.take_timebase = smp_generic_take_timebase,
};
#endif /* CONFIG_SMP */
#ifdef DUMP_DBATS
static void print_dbat(int idx, u32 bat)
{
char str[64];
sprintf(str, "DBAT%c%c = 0x%08x\n",
(char)((idx - DBAT0U) / 2) + '0', (idx & 1) ? 'L' : 'U', bat);
ppc_md.progress(str, 0);
}
#define DUMP_DBAT(x) \
do { \
u32 __temp = mfspr(x);\
print_dbat(x, __temp); \
} while (0)
static void dump_dbats(void)
{
if (ppc_md.progress) {
DUMP_DBAT(DBAT0U);
DUMP_DBAT(DBAT0L);
DUMP_DBAT(DBAT1U);
DUMP_DBAT(DBAT1L);
DUMP_DBAT(DBAT2U);
DUMP_DBAT(DBAT2L);
DUMP_DBAT(DBAT3U);
DUMP_DBAT(DBAT3L);
}
}
#endif
static unsigned long __init pplus_find_end_of_memory(void)
{
unsigned long total;
if (ppc_md.progress)
ppc_md.progress("pplus_find_end_of_memory", 0);
#ifdef DUMP_DBATS
dump_dbats();
#endif
total = pplus_get_mem_size(PPLUS_HAWK_SMC_BASE);
return (total);
}
static void __init pplus_map_io(void)
{
io_block_mapping(PPLUS_ISA_IO_BASE, PPLUS_ISA_IO_BASE, 0x10000000,
_PAGE_IO);
io_block_mapping(0xfef80000, 0xfef80000, 0x00080000, _PAGE_IO);
}
static void __init pplus_init2(void)
{
#ifdef CONFIG_NVRAM
request_region(PREP_NVRAM_AS0, 0x8, "nvram");
#endif
request_region(0x20, 0x20, "pic1");
request_region(0xa0, 0x20, "pic2");
request_region(0x00, 0x20, "dma1");
request_region(0x40, 0x20, "timer");
request_region(0x80, 0x10, "dma page reg");
request_region(0xc0, 0x20, "dma2");
}
/*
* Set BAT 2 to access 0x8000000 so progress messages will work and set BAT 3
* to 0xf0000000 to access Falcon/Raven or Hawk registers
*/
static __inline__ void pplus_set_bat(void)
{
/* wait for all outstanding memory accesses to complete */
mb();
/* setup DBATs */
mtspr(DBAT2U, 0x80001ffe);
mtspr(DBAT2L, 0x8000002a);
mtspr(DBAT3U, 0xf0001ffe);
mtspr(DBAT3L, 0xf000002a);
/* wait for updates */
mb();
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
/* Map in board regs, etc. */
pplus_set_bat();
isa_io_base = PREP_ISA_IO_BASE;
isa_mem_base = PREP_ISA_MEM_BASE;
pci_dram_offset = PREP_PCI_DRAM_OFFSET;
ISA_DMA_THRESHOLD = 0x00ffffff;
DMA_MODE_READ = 0x44;
DMA_MODE_WRITE = 0x48;
ppc_md.setup_arch = pplus_setup_arch;
ppc_md.show_cpuinfo = pplus_show_cpuinfo;
ppc_md.irq_canonicalize = pplus_irq_canonicalize;
ppc_md.init_IRQ = pplus_init_IRQ;
/* this gets changed later on if we have an OpenPIC -- Cort */
ppc_md.get_irq = i8259_irq;
ppc_md.init = pplus_init2;
ppc_md.restart = pplus_restart;
ppc_md.power_off = pplus_power_off;
ppc_md.halt = pplus_halt;
TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
PREP_NVRAM_DATA, 8);
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.calibrate_decr = todc_calibrate_decr;
ppc_md.nvram_read_val = todc_m48txx_read_val;
ppc_md.nvram_write_val = todc_m48txx_write_val;
ppc_md.find_end_of_memory = pplus_find_end_of_memory;
ppc_md.setup_io_mappings = pplus_map_io;
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
ppc_ide_md.default_irq = pplus_ide_default_irq;
ppc_ide_md.default_io_base = pplus_ide_default_io_base;
ppc_ide_md.ide_init_hwif = pplus_ide_init_hwif_ports;
#endif
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = gen550_progress;
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
#ifdef CONFIG_KGDB
ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
#endif
#ifdef CONFIG_SMP
ppc_md.smp_ops = &pplus_smp_ops;
#endif /* CONFIG_SMP */
}
arch/ppc/platforms/pplus.h 0 → 100644
View file @ 2a790ca1
/*
* arch/ppc/platforms/pplus.h
*
* Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greerinclude/asm-ppc/hawk.h
* mgreer@mvista.com
*
* Modified by Randy Vinson (rvinson@mvista.com)
*
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __PPC_PPLUS_H
#define __PPC_PPLUS_H
#include <asm/io.h>
/*
* Due to limiations imposed by legacy hardware (primaryily IDE controllers),
* the PPLUS boards operate using a PReP address map.
*
* From Processor (physical) -> PCI:
* PCI Mem Space: 0xc0000000 - 0xfe000000 -> 0x00000000 - 0x3e000000 (768 MB)
* PCI I/O Space: 0x80000000 - 0x90000000 -> 0x00000000 - 0x10000000 (256 MB)
* Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
*
* From PCI -> Processor (physical):
* System Memory: 0x80000000 -> 0x00000000
*/
#define PPLUS_ISA_MEM_BASE PREP_ISA_MEM_BASE
#define PPLUS_ISA_IO_BASE PREP_ISA_IO_BASE
/* PCI Memory space mapping info */
#define PPLUS_PCI_MEM_SIZE 0x30000000U
#define PPLUS_PROC_PCI_MEM_START PPLUS_ISA_MEM_BASE
#define PPLUS_PROC_PCI_MEM_END (PPLUS_PROC_PCI_MEM_START + \
PPLUS_PCI_MEM_SIZE - 1)
#define PPLUS_PCI_MEM_START 0x00000000U
#define PPLUS_PCI_MEM_END (PPLUS_PCI_MEM_START + \
PPLUS_PCI_MEM_SIZE - 1)
/* PCI I/O space mapping info */
#define PPLUS_PCI_IO_SIZE 0x10000000U
#define PPLUS_PROC_PCI_IO_START PPLUS_ISA_IO_BASE
#define PPLUS_PROC_PCI_IO_END (PPLUS_PROC_PCI_IO_START + \
PPLUS_PCI_IO_SIZE - 1)
#define PPLUS_PCI_IO_START 0x00000000U
#define PPLUS_PCI_IO_END (PPLUS_PCI_IO_START + \
PPLUS_PCI_IO_SIZE - 1)
/* System memory mapping info */
#define PPLUS_PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET
#define PPLUS_PCI_PHY_MEM_OFFSET (PPLUS_ISA_MEM_BASE-PPLUS_PCI_MEM_START)
/* Define base addresses for important sets of registers */
#define PPLUS_HAWK_SMC_BASE 0xfef80000U
#define PPLUS_HAWK_PPC_REG_BASE 0xfeff0000U
#define PPLUS_SYS_CONFIG_REG 0xfef80400U
#define PPLUS_L2_CONTROL_REG 0x8000081cU
#define PPLUS_VGA_MEM_BASE 0xf0000000U
extern int pplus_init(struct pci_controller *hose,
unsigned int ppc_reg_base, unsigned long processor_pci_mem_start,
unsigned long processor_pci_mem_end,
unsigned long processor_pci_io_start,
unsigned long processor_pci_io_end,
unsigned long processor_mpic_base);
extern unsigned long pplus_get_mem_size(unsigned int smc_base);
extern int pplus_mpic_init(unsigned int pci_mem_offset);
#endif /* __PPC_PPLUS_H */
arch/ppc/platforms/pplus_setup.c deleted 100644 → 0
View file @ bddd7645
/*
* arch/ppc/platforms/pplus_setup.c
*
* Board setup routines for MCG PowerPlus
*
* Author: Randy Vinson <rvinson@mvista.com>
*
* Derived from original PowerPlus PReP work by
* Cort Dougan, Johnnie Peters, Matt Porter, and
* Troy Benjegerdes.
*
* 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/config.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/user.h>
#include <linux/a.out.h>
#include <linux/tty.h>
#include <linux/major.h>
#include <linux/interrupt.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/initrd.h>
#include <linux/ioport.h>
#include <linux/console.h>
#include <linux/timex.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/ide.h>
#include <linux/kdev_t.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <asm/sections.h>
#include <asm/mmu.h>
#include <asm/system.h>
#include <asm/residual.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/cache.h>
#include <asm/dma.h>
#include <asm/machdep.h>
#include <asm/mk48t59.h>
#include <asm/prep_nvram.h>
#include <asm/raven.h>
#include <asm/vga.h>
#include <asm/time.h>
#include <asm/i8259.h>
#include <asm/open_pic.h>
#include <asm/pplus.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#undef DUMP_DBATS
TODC_ALLOC();
extern char saved_command_line[];
extern void pplus_setup_hose(void);
extern void pplus_set_VIA_IDE_native(void);
extern unsigned long loops_per_jiffy;
static int
pplus_show_cpuinfo(struct seq_file *m)
{
extern char *Motherboard_map_name;
seq_printf(m, "vendor\t\t: Motorola MCG\n");
seq_printf(m, "machine\t\t: %s\n", Motherboard_map_name);
return 0;
}
static void __init
pplus_setup_arch(void)
{
unsigned char reg;
if ( ppc_md.progress )
ppc_md.progress("pplus_setup_arch: enter\n", 0);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000;
if ( ppc_md.progress )
ppc_md.progress("pplus_setup_arch: find_bridges\n", 0);
/* Setup PCI host bridge */
pplus_setup_hose();
/* Set up floppy in PS/2 mode */
outb(0x09, SIO_CONFIG_RA);
reg = inb(SIO_CONFIG_RD);
reg = (reg & 0x3F) | 0x40;
outb(reg, SIO_CONFIG_RD);
outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
/* Enable L2. Assume we don't need to flush -- Cort*/
*(unsigned char *)(0x8000081c) |= 3;
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_SDA2;
#endif
printk(KERN_INFO "Motorola PowerPlus Platform\n");
printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
if ( ppc_md.progress )
ppc_md.progress("pplus_setup_arch: raven_init\n", 0);
raven_init();
#ifdef CONFIG_VGA_CONSOLE
/* remap the VGA memory */
vgacon_remap_base = 0xf0000000;
conswitchp = &vga_con;
#elif defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
#endif
#ifdef CONFIG_PPCBUG_NVRAM
/* Read in NVRAM data */
init_prep_nvram();
/* if no bootargs, look in NVRAM */
if ( cmd_line[0] == '\0' ) {
char *bootargs;
bootargs = prep_nvram_get_var("bootargs");
if (bootargs != NULL) {
strcpy(cmd_line, bootargs);
/* again.. */
strcpy(saved_command_line, cmd_line);
}
}
#endif
if ( ppc_md.progress )
ppc_md.progress("pplus_setup_arch: exit\n", 0);
}
static void
pplus_restart(char *cmd)
{
unsigned long i = 10000;
local_irq_disable();
/* set VIA IDE controller into native mode */
pplus_set_VIA_IDE_native();
/* set exception prefix high - to the prom */
_nmask_and_or_msr(0, MSR_IP);
/* make sure bit 0 (reset) is a 0 */
outb( inb(0x92) & ~1L , 0x92 );
/* signal a reset to system control port A - soft reset */
outb( inb(0x92) | 1 , 0x92 );
while ( i != 0 ) i++;
panic("restart failed\n");
}
static void
pplus_halt(void)
{
/* set exception prefix high - to the prom */
_nmask_and_or_msr(MSR_EE, MSR_IP);
/* make sure bit 0 (reset) is a 0 */
outb( inb(0x92) & ~1L , 0x92 );
/* signal a reset to system control port A - soft reset */
outb( inb(0x92) | 1 , 0x92 );
while ( 1 ) ;
/*
* Not reached
*/
}
static void
pplus_power_off(void)
{
pplus_halt();
}
static unsigned int
pplus_irq_canonicalize(u_int irq)
{
if (irq == 2)
{
return 9;
}
else
{
return irq;
}
}
static void __init
pplus_init_IRQ(void)
{
int i;
if (OpenPIC_Addr != NULL)
openpic_init(1, NUM_8259_INTERRUPTS, 0, -1);
for ( i = 0 ; i < NUM_8259_INTERRUPTS ; i++ )
irq_desc[i].handler = &i8259_pic;
i8259_init(NULL);
}
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
/*
* IDE stuff.
*/
static int
pplus_ide_default_irq(unsigned long base)
{
switch (base) {
case 0x1f0: return 14;
case 0x170: return 15;
default: return 0;
}
}
static unsigned long
pplus_ide_default_io_base(int index)
{
switch (index) {
case 0: return 0x1f0;
case 1: return 0x170;
default:
return 0;
}
}
static void __init
pplus_ide_init_hwif_ports (hw_regs_t *hw, unsigned long data_port, unsigned long ctrl_port, int *irq)
{
unsigned long reg = data_port;
int i;
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw->io_ports[i] = reg;
reg += 1;
}
if (ctrl_port) {
hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
} else {
hw->io_ports[IDE_CONTROL_OFFSET] = hw->io_ports[IDE_DATA_OFFSET] + 0x206;
}
if (irq != NULL)
*irq = pplus_ide_default_irq(data_port);
}
#endif
#ifdef CONFIG_SMP
/* PowerPlus (MTX) support */
static int __init
smp_pplus_probe(void)
{
extern int mot_multi;
if (mot_multi) {
openpic_request_IPIs();
smp_hw_index[1] = 1;
return 2;
}
return 1;
}
static void __init
smp_pplus_kick_cpu(int nr)
{
*(unsigned long *)KERNELBASE = nr;
asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory");
printk("CPU1 reset, waiting\n");
}
static void __init
smp_pplus_setup_cpu(int cpu_nr)
{
if (OpenPIC_Addr)
do_openpic_setup_cpu();
}
static struct smp_ops_t pplus_smp_ops = {
smp_openpic_message_pass,
smp_pplus_probe,
smp_pplus_kick_cpu,
smp_pplus_setup_cpu,
.give_timebase = smp_generic_give_timebase,
.take_timebase = smp_generic_take_timebase,
};
#endif /* CONFIG_SMP */
#ifdef DUMP_DBATS
static void print_dbat(int idx, u32 bat) {
char str[64];
sprintf(str, "DBAT%c%c = 0x%08x\n",
(char)((idx - DBAT0U) / 2) + '0',
(idx & 1) ? 'L' : 'U', bat);
ppc_md.progress(str, 0);
}
#define DUMP_DBAT(x) \
do { \
u32 __temp = mfspr(x);\
print_dbat(x, __temp); \
} while (0)
static void dump_dbats(void) {
if (ppc_md.progress) {
DUMP_DBAT(DBAT0U);
DUMP_DBAT(DBAT0L);
DUMP_DBAT(DBAT1U);
DUMP_DBAT(DBAT1L);
DUMP_DBAT(DBAT2U);
DUMP_DBAT(DBAT2L);
DUMP_DBAT(DBAT3U);
DUMP_DBAT(DBAT3L);
}
}
#endif
static unsigned long __init
pplus_find_end_of_memory(void)
{
unsigned long total;
if (ppc_md.progress)
ppc_md.progress("pplus_find_end_of_memory\n",0);
#ifdef DUMP_DBATS
dump_dbats();
#endif
total = pplus_get_mem_size(0xfef80000);
return (total);
}
static void __init
pplus_map_io(void)
{
io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO);
io_block_mapping(0xf0000000, 0xc0000000, 0x08000000, _PAGE_IO);
}
static void __init
pplus_init2(void)
{
#ifdef CONFIG_NVRAM
request_region(PREP_NVRAM_AS0, 0x8, "nvram");
#endif
request_region(0x20,0x20,"pic1");
request_region(0xa0,0x20,"pic2");
request_region(0x00,0x20,"dma1");
request_region(0x40,0x20,"timer");
request_region(0x80,0x10,"dma page reg");
request_region(0xc0,0x20,"dma2");
}
/*
* Set BAT 2 to access 0x8000000 so progress messages will work and set BAT 3
* to 0xf0000000 to access Falcon/Raven or Hawk registers
*/
static __inline__ void
pplus_set_bat(void)
{
static int mapping_set = 0;
if (!mapping_set) {
/* wait for all outstanding memory accesses to complete */
mb();
/* setup DBATs */
mtspr(DBAT2U, 0x80001ffe);
mtspr(DBAT2L, 0x8000002a);
mtspr(DBAT3U, 0xf0001ffe);
mtspr(DBAT3L, 0xf000002a);
/* wait for updates */
mb();
mapping_set = 1;
}
return;
}
#ifdef CONFIG_SERIAL_TEXT_DEBUG
#include <linux/serial.h>
#include <linux/serialP.h>
#include <linux/serial_reg.h>
#include <asm/serial.h>
static struct serial_state rs_table[RS_TABLE_SIZE] = {
SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
};
void
pplus_progress(char *s, unsigned short hex)
{
volatile char c;
volatile unsigned long com_port;
u16 shift;
com_port = rs_table[0].port + isa_io_base;
shift = rs_table[0].iomem_reg_shift;
while ((c = *s++) != 0) {
while ((*((volatile unsigned char *)com_port +
(UART_LSR << shift)) & UART_LSR_THRE) == 0)
;
*(volatile unsigned char *)com_port = c;
if (c == '\n') {
while ((*((volatile unsigned char *)com_port +
(UART_LSR << shift)) & UART_LSR_THRE) == 0)
;
*(volatile unsigned char *)com_port = '\r';
}
}
}
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
/* Map in board regs, etc. */
pplus_set_bat();
isa_io_base = PREP_ISA_IO_BASE;
isa_mem_base = PREP_ISA_MEM_BASE;
pci_dram_offset = PREP_PCI_DRAM_OFFSET;
ISA_DMA_THRESHOLD = 0x00ffffff;
DMA_MODE_READ = 0x44;
DMA_MODE_WRITE = 0x48;
ppc_md.setup_arch = pplus_setup_arch;
ppc_md.show_percpuinfo = NULL;
ppc_md.show_cpuinfo = pplus_show_cpuinfo;
ppc_md.irq_canonicalize = pplus_irq_canonicalize;
ppc_md.init_IRQ = pplus_init_IRQ;
/* this gets changed later on if we have an OpenPIC -- Cort */
ppc_md.get_irq = i8259_irq;
ppc_md.init = pplus_init2;
ppc_md.restart = pplus_restart;
ppc_md.power_off = pplus_power_off;
ppc_md.halt = pplus_halt;
TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
PREP_NVRAM_DATA, 8);
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.calibrate_decr = todc_calibrate_decr;
ppc_md.nvram_read_val = todc_m48txx_read_val;
ppc_md.nvram_write_val = todc_m48txx_write_val;
ppc_md.find_end_of_memory = pplus_find_end_of_memory;
ppc_md.setup_io_mappings = pplus_map_io;
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = pplus_progress;
#endif
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
ppc_ide_md.default_irq = pplus_ide_default_irq;
ppc_ide_md.default_io_base = pplus_ide_default_io_base;
ppc_ide_md.ide_init_hwif = pplus_ide_init_hwif_ports;
#endif
#ifdef CONFIG_SMP
ppc_md.smp_ops = &pplus_smp_ops;
#endif /* CONFIG_SMP */
}
arch/ppc/syslib/pplus_common.c
View file @ 2a790ca1
......@@ -21,7 +21,7 @@
#include <asm/pci.h>
#include <asm/pci-bridge.h>
#include <asm/open_pic.h>
#include <asm/pplus.h>
#include <asm/hawk.h>
/*
* The Falcon/Raven and HAWK has 4 sets of registers:
......@@ -95,10 +95,10 @@ pplus_init(struct pci_controller *hose,
/*
* Disable previous PPC->PCI mappings.
*/
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF0_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF1_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF2_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF3_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF2_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), 0x00000000);
/*
* Program the XSADD/XSOFF registers to set up the PCI Mem & I/O
......@@ -113,21 +113,23 @@ pplus_init(struct pci_controller *hose,
/* Set up PPC->PCI Mem mapping */
addr = processor_pci_mem_start | (processor_pci_mem_end >> 16);
offset = (hose->mem_space.start - processor_pci_mem_start) | 0xd2;
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD0_OFF), addr);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF0_OFF), offset);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD0_OFF), addr);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), offset);
/* Set up PPC->MPIC mapping on the bridge */
addr = processor_mpic_base |
(((processor_mpic_base + PPLUS_MPIC_SIZE) >> 16) - 1);
offset = 0xc2; /* No write posting for this PCI Mem space */
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD1_OFF), addr);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF1_OFF), offset);
(((processor_mpic_base + HAWK_MPIC_SIZE) >> 16) - 1);
/* No write posting for this PCI Mem space */
offset = (hose->mem_space.start - processor_pci_mem_start) | 0xc2;
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD1_OFF), addr);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), offset);
/* Set up PPC->PCI I/O mapping -- Contiguous I/O space */
addr = processor_pci_io_start | (processor_pci_io_end >> 16);
offset = (hose->io_space.start - processor_pci_io_start) | 0xc0;
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD3_OFF), addr);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF3_OFF), offset);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD3_OFF), addr);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), offset);
hose->io_base_virt = (void *)ioremap(processor_pci_io_start,
(processor_pci_io_end - processor_pci_io_start + 1));
......@@ -137,8 +139,8 @@ pplus_init(struct pci_controller *hose,
* The PCI config addr/data pair based on start addr of PCI I/O space.
*/
setup_indirect_pci(hose,
processor_pci_io_start + PPLUS_PCI_CONFIG_ADDR_OFF,
processor_pci_io_start + PPLUS_PCI_CONFIG_DATA_OFF);
processor_pci_io_start + HAWK_PCI_CONFIG_ADDR_OFF,
processor_pci_io_start + HAWK_PCI_CONFIG_DATA_OFF);
/*
* Disable previous PCI->PPC mappings.
......@@ -161,10 +163,12 @@ pplus_init(struct pci_controller *hose,
0,
PCI_DEVFN(0,0),
PCI_BASE_ADDRESS_1,
processor_mpic_base | 0x0);
(processor_mpic_base -
processor_pci_mem_start +
hose->mem_space.start) | 0x0);
/* Map MPIC into vitual memory */
OpenPIC_Addr = ioremap(processor_mpic_base, PPLUS_MPIC_SIZE);
OpenPIC_Addr = ioremap(processor_mpic_base, HAWK_MPIC_SIZE);
return 0;
}
......@@ -181,14 +185,14 @@ pplus_init(struct pci_controller *hose,
#define MB (1024*1024)
static uint reg_offset_table[] __initdata = {
PPLUS_SMC_RAM_A_SIZE_REG_OFF,
PPLUS_SMC_RAM_B_SIZE_REG_OFF,
PPLUS_SMC_RAM_C_SIZE_REG_OFF,
PPLUS_SMC_RAM_D_SIZE_REG_OFF,
PPLUS_SMC_RAM_E_SIZE_REG_OFF,
PPLUS_SMC_RAM_F_SIZE_REG_OFF,
PPLUS_SMC_RAM_G_SIZE_REG_OFF,
PPLUS_SMC_RAM_H_SIZE_REG_OFF
HAWK_SMC_RAM_A_SIZE_REG_OFF,
HAWK_SMC_RAM_B_SIZE_REG_OFF,
HAWK_SMC_RAM_C_SIZE_REG_OFF,
HAWK_SMC_RAM_D_SIZE_REG_OFF,
HAWK_SMC_RAM_E_SIZE_REG_OFF,
HAWK_SMC_RAM_F_SIZE_REG_OFF,
HAWK_SMC_RAM_G_SIZE_REG_OFF,
HAWK_SMC_RAM_H_SIZE_REG_OFF
};
static uint falcon_size_table[] __initdata = {
......@@ -246,13 +250,13 @@ pplus_get_mem_size(uint smc_base)
size_table_entries = sizeof(falcon_size_table) /
sizeof(falcon_size_table[0]);
reg_limit = PPLUS_FALCON_SMC_REG_COUNT;
reg_limit = FALCON_SMC_REG_COUNT;
}
else if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HAWK) {
size_table = hawk_size_table;
size_table_entries = sizeof(hawk_size_table) /
sizeof(hawk_size_table[0]);
reg_limit = PPLUS_HAWK_SMC_REG_COUNT;
reg_limit = HAWK_SMC_REG_COUNT;
}
else {
printk("pplus_get_mem_size: %s (0x%x)\n",
......
include/asm-ppc/hawk.h 0 → 100644
View file @ 2a790ca1
/*
* include/asm-ppc/hawk.h
*
* Support functions for MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greer
* mgreer@mvista.com
*
* Modified by Randy Vinson (rvinson@mvista.com)
*
* 2001,2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASMPPC_HAWK_H
#define __ASMPPC_HAWK_H
#include <asm/pci-bridge.h>
#include <asm/hawk_defs.h>
extern int hawk_init(struct pci_controller *hose,
unsigned int ppc_reg_base, unsigned long processor_pci_mem_start,
unsigned long processor_pci_mem_end,
unsigned long processor_pci_io_start,
unsigned long processor_pci_io_end,
unsigned long processor_mpic_base);
extern unsigned long hawk_get_mem_size(unsigned int smc_base);
extern int hawk_mpic_init(unsigned int pci_mem_offset);
#endif /* __ASMPPC_PPLUS_H */
include/asm-ppc/pplus.h → include/asm-ppc/hawk_defs.h
View file @ 2a790ca1
/*
* include/asm-ppc/pplus.h
* include/asm-ppc/hawk_defs.h
*
* Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greer
* mgreer@mvista.com
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* Modified by Randy Vinson (rvinson@mvista.com)
*
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASMPPC_PPLUS_H
#define __ASMPPC_PPLUS_H
#ifndef __ASMPPC_HAWK_DEFS_H
#define __ASMPPC_HAWK_DEFS_H
#include <asm/pci-bridge.h>
......@@ -27,66 +29,48 @@
* 4) System Memory Controller (SMC) registers.
*/
#define PPLUS_RAVEN_VEND_DEV_ID 0x48011057
#define PPLUS_HAWK_VEND_DEV_ID 0x48031057
#define PPLUS_PCI_CONFIG_ADDR_OFF 0x00000cf8
#define PPLUS_PCI_CONFIG_DATA_OFF 0x00000cfc
#define HAWK_PCI_CONFIG_ADDR_OFF 0x00000cf8
#define HAWK_PCI_CONFIG_DATA_OFF 0x00000cfc
#define PPLUS_MPIC_SIZE 0x00040000U
#define PPLUS_SMC_SIZE 0x00001000U
#define HAWK_MPIC_SIZE 0x00040000U
#define HAWK_SMC_SIZE 0x00001000U
/*
* Define PPC register offsets.
*/
#define PPLUS_PPC_XSADD0_OFF 0x40
#define PPLUS_PPC_XSOFF0_OFF 0x44
#define PPLUS_PPC_XSADD1_OFF 0x48
#define PPLUS_PPC_XSOFF1_OFF 0x4c
#define PPLUS_PPC_XSADD2_OFF 0x50
#define PPLUS_PPC_XSOFF2_OFF 0x54
#define PPLUS_PPC_XSADD3_OFF 0x58
#define PPLUS_PPC_XSOFF3_OFF 0x5c
#define HAWK_PPC_XSADD0_OFF 0x40
#define HAWK_PPC_XSOFF0_OFF 0x44
#define HAWK_PPC_XSADD1_OFF 0x48
#define HAWK_PPC_XSOFF1_OFF 0x4c
#define HAWK_PPC_XSADD2_OFF 0x50
#define HAWK_PPC_XSOFF2_OFF 0x54
#define HAWK_PPC_XSADD3_OFF 0x58
#define HAWK_PPC_XSOFF3_OFF 0x5c
/*
* Define PCI register offsets.
*/
#define PPLUS_PCI_PSADD0_OFF 0x80
#define PPLUS_PCI_PSOFF0_OFF 0x84
#define PPLUS_PCI_PSADD1_OFF 0x88
#define PPLUS_PCI_PSOFF1_OFF 0x8c
#define PPLUS_PCI_PSADD2_OFF 0x90
#define PPLUS_PCI_PSOFF2_OFF 0x94
#define PPLUS_PCI_PSADD3_OFF 0x98
#define PPLUS_PCI_PSOFF3_OFF 0x9c
#define HAWK_PCI_PSADD0_OFF 0x80
#define HAWK_PCI_PSOFF0_OFF 0x84
#define HAWK_PCI_PSADD1_OFF 0x88
#define HAWK_PCI_PSOFF1_OFF 0x8c
#define HAWK_PCI_PSADD2_OFF 0x90
#define HAWK_PCI_PSOFF2_OFF 0x94
#define HAWK_PCI_PSADD3_OFF 0x98
#define HAWK_PCI_PSOFF3_OFF 0x9c
/*
* Define the System Memory Controller (SMC) register offsets.
*/
#define PPLUS_SMC_RAM_A_SIZE_REG_OFF 0x10
#define PPLUS_SMC_RAM_B_SIZE_REG_OFF 0x11
#define PPLUS_SMC_RAM_C_SIZE_REG_OFF 0x12
#define PPLUS_SMC_RAM_D_SIZE_REG_OFF 0x13
#define PPLUS_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */
#define PPLUS_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */
#define PPLUS_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */
#define PPLUS_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */
#define PPLUS_FALCON_SMC_REG_COUNT 4
#define PPLUS_HAWK_SMC_REG_COUNT 8
int pplus_init(struct pci_controller *hose,
uint ppc_reg_base,
ulong processor_pci_mem_start,
ulong processor_pci_mem_end,
ulong processor_pci_io_start,
ulong processor_pci_io_end,
ulong processor_mpic_base);
unsigned long pplus_get_mem_size(uint smc_base);
int pplus_mpic_init(unsigned int pci_mem_offset);
#endif /* __ASMPPC_PPLUS_H */
#define HAWK_SMC_RAM_A_SIZE_REG_OFF 0x10
#define HAWK_SMC_RAM_B_SIZE_REG_OFF 0x11
#define HAWK_SMC_RAM_C_SIZE_REG_OFF 0x12
#define HAWK_SMC_RAM_D_SIZE_REG_OFF 0x13
#define HAWK_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */
#define HAWK_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */
#define HAWK_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */
#define HAWK_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */
#define FALCON_SMC_REG_COUNT 4
#define HAWK_SMC_REG_COUNT 8
#endif /* __ASMPPC_HAWK_DEFS_H */
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7