Commit 2a8d04d7 authored by Ralf Bächle's avatar Ralf Bächle Committed by Linus Torvalds

[PATCH] Add support for SGI IP32

This adds support for SGI's O2 workstation aka IP32.
parent 17017b3a
......@@ -3,11 +3,7 @@
# under Linux.
#
extra-y := ip32-irq-glue.o
obj-y += ip32-irq.o ip32-rtc.o ip32-setup.o ip32-irq-glue.o \
ip32-berr.o ip32-timer.o crime.o
obj-$(CONFIG_PCI) += ip32-pci.o ip32-pci-dma.o
obj-y += ip32-berr.o ip32-rtc.o ip32-setup.o ip32-irq.o ip32-irq-glue.o \
ip32-timer.o crime.o ip32-reset.o
EXTRA_AFLAGS := $(CFLAGS)
......@@ -10,7 +10,6 @@
#include <linux/kernel.h>
#include <asm/ip32/crime.h>
#include <asm/ptrace.h>
#include <asm/promlib.h>
void __init crime_init (void)
{
......
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 1995, 1996, 1999, 2000 by Ralf Baechle
* Copyright (C) 1999, 2000 by Silicon Graphics
* Copyright (C) 2002 Maciej W. Rozycki
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/traps.h>
#include <asm/uaccess.h>
#include <asm/addrspace.h>
#include <asm/ptrace.h>
#include <asm/tlbdebug.h>
int ip32_be_handler(struct pt_regs *regs, int is_fixup)
{
int data = regs->cp0_cause & 4;
if (is_fixup)
return MIPS_BE_FIXUP;
printk("Got %cbe at 0x%lx\n", data ? 'd' : 'i', regs->cp0_epc);
show_regs(regs);
dump_tlb_all();
while(1);
force_sig(SIGBUS, current);
}
void __init ip32_be_init(void)
{
board_be_handler = ip32_be_handler;
}
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001 Keith M Wesolowski
* Copyright (C) 2001 Paul Mundt
* Copyright (C) 2003 Guido Guenther <agx@sigxcpu.org>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/notifier.h>
#include <linux/delay.h>
#include <linux/ds17287rtc.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/sgialib.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <asm/system.h>
#include <asm/wbflush.h>
#include <asm/ip32/ip32_ints.h>
#define POWERDOWN_TIMEOUT 120
/*
* Blink frequency during reboot grace period and when paniced.
*/
#define POWERDOWN_FREQ (HZ / 4)
#define PANIC_FREQ (HZ / 8)
static struct timer_list power_timer, blink_timer, debounce_timer;
static int shuting_down = 0, has_paniced = 0;
static void ip32_machine_restart(char *command) __attribute__((noreturn));
static void ip32_machine_halt(void) __attribute__((noreturn));
static void ip32_machine_power_off(void) __attribute__((noreturn));
static void ip32_machine_restart(char *cmd)
{
if (shuting_down)
ip32_machine_power_off();
ArcReboot();
}
static inline void ip32_machine_halt(void)
{
if (shuting_down)
ip32_machine_power_off();
ArcEnterInteractiveMode();
}
static void ip32_machine_power_off(void)
{
volatile unsigned char reg_a, xctrl_a, xctrl_b;
disable_irq(MACEISA_RTC_IRQ);
reg_a = CMOS_READ(RTC_REG_A);
/* setup for kickstart & wake-up (DS12287 Ref. Man. p. 19) */
reg_a &= ~DS_REGA_DV2;
reg_a |= DS_REGA_DV1;
CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A);
wbflush();
xctrl_b = CMOS_READ(DS_B1_XCTRL4B)
| DS_XCTRL4B_ABE | DS_XCTRL4B_KFE;
CMOS_WRITE(xctrl_b, DS_B1_XCTRL4B);
xctrl_a = CMOS_READ(DS_B1_XCTRL4A) & ~DS_XCTRL4A_IFS;
CMOS_WRITE(xctrl_a, DS_B1_XCTRL4A);
wbflush();
/* adios amigos... */
CMOS_WRITE(xctrl_a | DS_XCTRL4A_PAB, DS_B1_XCTRL4A);
CMOS_WRITE(reg_a, RTC_REG_A);
wbflush();
while(1) {
printk(KERN_DEBUG "Power off!\n");
}
}
static void power_timeout(unsigned long data)
{
ip32_machine_power_off();
}
static void blink_timeout(unsigned long data)
{
u64 mc_led = mace_read_64(MACEISA_FLASH_NIC_REG);
mc_led ^= MACEISA_LED_RED;
mace_write_64(MACEISA_FLASH_NIC_REG, mc_led);
mod_timer(&blink_timer, jiffies+data);
}
static void debounce(unsigned long data)
{
volatile unsigned char reg_a,reg_c,xctrl_a;
reg_c = CMOS_READ(RTC_INTR_FLAGS);
CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A);
wbflush();
xctrl_a = CMOS_READ(DS_B1_XCTRL4A);
if( (xctrl_a & DS_XCTRL4A_IFS ) || ( reg_c & RTC_IRQF ) ) {
/* Interrupt still being sent. */
debounce_timer.expires = jiffies + 50;
add_timer(&debounce_timer);
/* clear interrupt source */
CMOS_WRITE( xctrl_a & ~DS_XCTRL4A_IFS, DS_B1_XCTRL4A);
CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A);
return;
}
CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A);
if (has_paniced)
ArcReboot();
enable_irq(MACEISA_RTC_IRQ);
}
static inline void ip32_power_button(void)
{
if (has_paniced)
return;
if (shuting_down || kill_proc(1, SIGINT, 1)) {
/* No init process or button pressed twice. */
ip32_machine_power_off();
}
shuting_down = 1;
blink_timer.data = POWERDOWN_FREQ;
blink_timeout(POWERDOWN_FREQ);
init_timer(&power_timer);
power_timer.function = power_timeout;
power_timer.expires = jiffies + POWERDOWN_TIMEOUT * HZ;
add_timer(&power_timer);
}
static void ip32_rtc_int(int irq, void *dev_id, struct pt_regs *regs)
{
volatile unsigned char reg_c;
reg_c = CMOS_READ(RTC_INTR_FLAGS);
if( ! (reg_c & RTC_IRQF) ) {
printk(KERN_WARNING
"%s: RTC IRQ without RTC_IRQF\n", __FUNCTION__);
}
/* Wait until interrupt goes away */
disable_irq(MACEISA_RTC_IRQ);
init_timer(&debounce_timer);
debounce_timer.function = debounce;
debounce_timer.expires = jiffies + 50;
add_timer(&debounce_timer);
printk(KERN_DEBUG "Power button pressed\n");
ip32_power_button();
}
static int panic_event(struct notifier_block *this, unsigned long event,
void *ptr)
{
u64 mc_led;
if (has_paniced)
return NOTIFY_DONE;
has_paniced = 1;
/* turn off the green LED */
mc_led = mace_read_64(MACEISA_FLASH_NIC_REG);
mc_led |= MACEISA_LED_GREEN;
mace_write_64(MACEISA_FLASH_NIC_REG, mc_led);
blink_timer.data = PANIC_FREQ;
blink_timeout(PANIC_FREQ);
return NOTIFY_DONE;
}
static struct notifier_block panic_block = {
.notifier_call = panic_event,
};
static __init int ip32_reboot_setup(void)
{
u64 mc_led = mace_read_64(MACEISA_FLASH_NIC_REG);
_machine_restart = ip32_machine_restart;
_machine_halt = ip32_machine_halt;
_machine_power_off = ip32_machine_power_off;
request_irq(MACEISA_RTC_IRQ, ip32_rtc_int, 0, "rtc", NULL);
init_timer(&blink_timer);
blink_timer.function = blink_timeout;
notifier_chain_register(&panic_notifier_list, &panic_block);
/* turn on the green led only */
mc_led |= MACEISA_LED_RED;
mc_led &= ~MACEISA_LED_GREEN;
mace_write_64(MACEISA_FLASH_NIC_REG, mc_led);
return 0;
}
subsys_initcall(ip32_reboot_setup);
......@@ -7,27 +7,60 @@
*
* Copyright (C) 2000 Harald Koerfgen
*/
#include <linux/config.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/time.h>
#include <asm/mipsregs.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
#include <asm/ip32/crime.h>
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>
#include <asm/sgialib.h>
#include <asm/traps.h>
extern struct rtc_ops ip32_rtc_ops;
extern u32 cc_interval;
void __init ip32_init (int argc, char **argv, char **envp) {
arc_meminit ();
#ifdef CONFIG_SGI_O2MACE_ETH
/*
* This is taken care of in here 'cause they say using Arc later on is
* problematic
*/
extern char o2meth_eaddr[8];
static inline unsigned char str2hexnum(unsigned char c)
{
if (c >= '0' && c <= '9')
return c - '0';
if (c >= 'a' && c <= 'f')
return c - 'a' + 10;
return 0; /* foo */
}
static inline void str2eaddr(unsigned char *ea, unsigned char *str)
{
int i;
for (i = 0; i < 6; i++) {
unsigned char num;
if(*str == ':')
str++;
num = str2hexnum(*str++) << 4;
num |= (str2hexnum(*str++));
ea[i] = num;
}
}
#endif
extern void ip32_time_init(void);
extern void ip32_reboot_setup(void);
void __init ip32_setup(void)
{
......@@ -36,6 +69,8 @@ void __init ip32_setup(void)
#endif
TLBMISS_HANDLER_SETUP ();
mips_io_port_base = UNCACHEDADDR(MACEPCI_HI_IO);;
#ifdef CONFIG_SERIAL_CONSOLE
ctype = ArcGetEnvironmentVariable("console");
if (*ctype == 'd') {
......@@ -45,12 +80,20 @@ void __init ip32_setup(void)
console_setup ("ttyS0");
}
#endif
#ifdef CONFIG_SGI_O2MACE_ETH
{
char *mac=ArcGetEnvironmentVariable("eaddr");
str2eaddr(o2meth_eaddr, mac);
}
#endif
#ifdef CONFIG_VT
conswitchp = &dummy_con;
#endif
rtc_ops = &ip32_rtc_ops;
board_be_init = ip32_be_init;
board_time_init = ip32_time_init;
crime_init ();
}
......
/*
* IP32 timer calibration
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001 Keith M Wesolowski
*/
#include <linux/bcd.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/mc146818rtc.h>
#include <linux/timex.h>
#include <asm/mipsregs.h>
#include <asm/param.h>
#include <asm/ip32/crime.h>
#include <asm/ip32/ip32_ints.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
#include <asm/irq.h>
extern volatile unsigned long wall_jiffies;
u32 cc_interval;
/* Cycle counter value at the previous timer interrupt.. */
static unsigned int timerhi, timerlo;
/* An arbitrary time; this can be decreased if reliability looks good */
#define WAIT_MS 10
#define PER_MHZ (1000000 / 2 / HZ)
/*
* Change this if you have some constant time drift
*/
#define USECS_PER_JIFFY (1000000/HZ)
void __init ip32_timer_setup (struct irqaction *irq)
{
u64 crime_time;
u32 cc_tick;
printk("Calibrating system timer... ");
crime_time = crime_read_64 (CRIME_TIME) & CRIME_TIME_MASK;
cc_tick = read_c0_count();
while ((crime_read_64 (CRIME_TIME) & CRIME_TIME_MASK) - crime_time
< WAIT_MS * 1000000 / CRIME_NS_PER_TICK)
;
cc_tick = read_c0_count() - cc_tick;
cc_interval = cc_tick / HZ * (1000 / WAIT_MS);
/* The round-off seems unnecessary; in testing, the error of the
* above procedure is < 100 ticks, which means it gets filtered
* out by the HZ adjustment.
*/
cc_interval = (cc_interval / PER_MHZ) * PER_MHZ;
printk("%d MHz CPU detected\n", (int) (cc_interval / PER_MHZ));
setup_irq (CLOCK_IRQ, irq);
}
struct irqaction irq0 = { NULL, SA_INTERRUPT, 0,
"timer", NULL, NULL};
void cc_timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
{
u32 count;
/*
* The cycle counter is only 32 bit which is good for about
* a minute at current count rates of upto 150MHz or so.
*/
count = read_c0_count();
timerhi += (count < timerlo); /* Wrap around */
timerlo = count;
write_c0_compare(
(u32) (count + cc_interval));
kstat_cpu(0).irqs[irq]++;
do_timer (regs);
if (!jiffies)
{
/*
* If jiffies has overflowed in this timer_interrupt we must
* update the timer[hi]/[lo] to make do_fast_gettimeoffset()
* quotient calc still valid. -arca
*/
timerhi = timerlo = 0;
}
}
/*
* On MIPS only R4000 and better have a cycle counter.
*
* FIXME: Does playing with the RP bit in c0_status interfere with this code?
*/
static unsigned long do_gettimeoffset(void)
{
u32 count;
unsigned long res, tmp;
/* Last jiffy when do_fast_gettimeoffset() was called. */
static unsigned long last_jiffies;
u32 quotient;
/*
* Cached "1/(clocks per usec)*2^32" value.
* It has to be recalculated once each jiffy.
*/
static u32 cached_quotient;
tmp = jiffies;
quotient = cached_quotient;
if (tmp && last_jiffies != tmp) {
last_jiffies = tmp;
__asm__(".set\tnoreorder\n\t"
".set\tnoat\n\t"
".set\tmips3\n\t"
"lwu\t%0,%2\n\t"
"dsll32\t$1,%1,0\n\t"
"or\t$1,$1,%0\n\t"
"ddivu\t$0,$1,%3\n\t"
"mflo\t$1\n\t"
"dsll32\t%0,%4,0\n\t"
"nop\n\t"
"ddivu\t$0,%0,$1\n\t"
"mflo\t%0\n\t"
".set\tmips0\n\t"
".set\tat\n\t"
".set\treorder"
:"=&r" (quotient)
:"r" (timerhi),
"m" (timerlo),
"r" (tmp),
"r" (USECS_PER_JIFFY)
:"$1");
cached_quotient = quotient;
}
/* Get last timer tick in absolute kernel time */
count = read_c0_count();
/* .. relative to previous jiffy (32 bits is enough) */
count -= timerlo;
__asm__("multu\t%1,%2\n\t"
"mfhi\t%0"
:"=r" (res)
:"r" (count),
"r" (quotient));
/*
* Due to possible jiffies inconsistencies, we need to check
* the result so that we'll get a timer that is monotonic.
*/
if (res >= USECS_PER_JIFFY)
res = USECS_PER_JIFFY-1;
return res;
}
void __init ip32_time_init(void)
{
unsigned int epoch = 0, year, mon, day, hour, min, sec;
int i;
/* The Linux interpretation of the CMOS clock register contents:
* When the Update-In-Progress (UIP) flag goes from 1 to 0, the
* RTC registers show the second which has precisely just started.
* Let's hope other operating systems interpret the RTC the same way.
*/
/* read RTC exactly on falling edge of update flag */
for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */
if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
break;
for (i = 0 ; i < 1000000 ; i++) /* must try at least 2.228 ms */
if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
break;
do { /* Isn't this overkill ? UIP above should guarantee consistency */
sec = CMOS_READ(RTC_SECONDS);
min = CMOS_READ(RTC_MINUTES);
hour = CMOS_READ(RTC_HOURS);
day = CMOS_READ(RTC_DAY_OF_MONTH);
mon = CMOS_READ(RTC_MONTH);
year = CMOS_READ(RTC_YEAR);
} while (sec != CMOS_READ(RTC_SECONDS));
if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
sec = BCD2BIN(sec);
min = BCD2BIN(min);
hour = BCD2BIN(hour);
day = BCD2BIN(day);
mon = BCD2BIN(mon);
year = BCD2BIN(year);
}
/* Attempt to guess the epoch. This is the same heuristic as in
* rtc.c so no stupid things will happen to timekeeping. Who knows,
* maybe Ultrix also uses 1952 as epoch ...
*/
if (year > 10 && year < 44)
epoch = 1980;
else if (year < 96)
epoch = 1952;
year += epoch;
write_seqlock_irq(&xtime_lock);
xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
xtime.tv_nsec = 0;
write_sequnlock_irq(&xtime_lock);
write_c0_count(0);
irq0.handler = cc_timer_interrupt;
ip32_timer_setup (&irq0);
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
/* Set ourselves up for future interrupts */
write_c0_compare(
read_c0_count()
+ cc_interval);
change_c0_status(ST0_IM, ALLINTS);
sti ();
}
This diff is collapsed.
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 1995, 1996, 1999, 2000 by Ralf Baechle
* Copyright (C) 1999, 2000 by Silicon Graphics
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/uaccess.h>
#include <asm/paccess.h>
#include <asm/addrspace.h>
#include <asm/ptrace.h>
/* XXX I have no idea what this does --kmw */
extern asmlinkage void handle_ibe(void);
extern asmlinkage void handle_dbe(void);
extern const struct exception_table_entry __start___dbe_table[];
extern const struct exception_table_entry __stop___dbe_table[];
static inline unsigned long
search_one_table(const struct exception_table_entry *first,
const struct exception_table_entry *last,
unsigned long value)
{
while (first <= last) {
const struct exception_table_entry *mid;
long diff;
mid = (last - first) / 2 + first;
diff = mid->insn - value;
if (diff == 0)
return mid->nextinsn;
else if (diff < 0)
first = mid+1;
else
last = mid-1;
}
return 0;
}
static inline unsigned long
search_dbe_table(unsigned long addr)
{
unsigned long ret;
/* There is only the kernel to search. */
ret = search_one_table(__start___dbe_table, __stop___dbe_table-1, addr);
if (ret) return ret;
return 0;
}
void do_ibe(struct pt_regs *regs)
{
printk("Got ibe at 0x%lx\n", regs->cp0_epc);
show_regs(regs);
dump_tlb_addr(regs->cp0_epc);
force_sig(SIGBUS, current);
while(1);
}
void do_dbe(struct pt_regs *regs)
{
unsigned long fixup;
fixup = search_dbe_table(regs->cp0_epc);
if (fixup) {
long new_epc;
new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc);
regs->cp0_epc = new_epc;
return;
}
printk("Got dbe at 0x%lx\n", regs->cp0_epc);
show_regs(regs);
dump_tlb_all();
while(1);
force_sig(SIGBUS, current);
}
void __init
bus_error_init(void)
{
int dummy;
set_except_vector(6, handle_ibe);
set_except_vector(7, handle_dbe);
/* At this time nothing uses the DBE protection mechanism on the
O2, so this here is needed to make the kernel link. */
get_dbe(dummy, (int *)KSEG0);
}
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com>
* Copyright (C) 2000 Ralf Baechle <ralf@gnu.org>
* swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
*/
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/pci.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/ip32/mace.h>
void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
dma_addr_t * dma_handle)
{
void *ret;
int gfp = GFP_ATOMIC;
if (hwdev == NULL || hwdev->dma_mask != 0xffffffff)
gfp |= GFP_DMA;
ret = (void *) __get_free_pages(gfp, get_order(size));
if (ret != NULL) {
memset(ret, 0, size);
dma_cache_wback_inv((unsigned long) ret, size);
*dma_handle = virt_to_bus(ret);
}
return ret;
}
void pci_free_consistent(struct pci_dev *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
free_pages((unsigned long) vaddr, get_order(size));
}
This diff is collapsed.
/*
* IP32 timer calibration
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001 Keith M Wesolowski
*/
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/mipsregs.h>
#include <asm/param.h>
#include <asm/ip32/crime.h>
#include <asm/ip32/ip32_ints.h>
extern u32 cc_interval;
/* An arbitrary time; this can be decreased if reliability looks good */
#define WAIT_MS 10
#define PER_MHZ (1000000 / 2 / HZ)
void __init ip32_timer_setup (struct irqaction *irq) {
u64 crime_time;
u32 cc_tick;
printk("Calibrating system timer... ");
crime_time = crime_read_64 (CRIME_TIME) & CRIME_TIME_MASK;
cc_tick = read_32bit_cp0_register (CP0_COUNT);
while ((crime_read_64 (CRIME_TIME) & CRIME_TIME_MASK) - crime_time
< WAIT_MS * 1000000 / CRIME_NS_PER_TICK)
;
cc_tick = read_32bit_cp0_register (CP0_COUNT) - cc_tick;
cc_interval = cc_tick / HZ * (1000 / WAIT_MS);
/* The round-off seems unnecessary; in testing, the error of the
* above procedure is < 100 ticks, which means it gets filtered
* out by the HZ adjustment.
*/
cc_interval = (cc_interval / PER_MHZ) * PER_MHZ;
printk("%d MHz CPU detected\n", (int) (cc_interval / PER_MHZ));
setup_irq (CLOCK_IRQ, irq);
}
/*
* Definitions for the SGI O2 Crime chip.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Harald Koerfgen
*/
#ifndef __ASM_CRIME_H__
#define __ASM_CRIME_H__
#include <asm/addrspace.h>
/*
* Address map
*/
#ifndef __ASSEMBLY__
#define CRIME_BASE KSEG1ADDR(0x14000000)
#else
#define CRIME_BASE 0xffffffffb4000000
#endif
#ifndef __ASSEMBLY__
static inline u64 crime_read_64 (unsigned long __offset) {
return *((volatile u64 *) (CRIME_BASE + __offset));
}
static inline void crime_write_64 (unsigned long __offset, u64 __val) {
*((volatile u64 *) (CRIME_BASE + __offset)) = __val;
}
#endif
#undef BIT
#define BIT(x) (1UL << (x))
/* All CRIME registers are 64 bits */
#define CRIME_ID 0
#define CRIME_ID_MASK 0xff
#define CRIME_ID_IDBITS 0xf0
#define CRIME_ID_IDVALUE 0xa0
#define CRIME_ID_REV 0x0f
#define CRIME_REV_PETTY 0x00
#define CRIME_REV_11 0x11
#define CRIME_REV_13 0x13
#define CRIME_REV_14 0x14
#define CRIME_CONTROL (0x00000008)
#define CRIME_CONTROL_MASK 0x3fff /* 14-bit registers */
/* CRIME_CONTROL register bits */
#define CRIME_CONTROL_TRITON_SYSADC 0x2000
#define CRIME_CONTROL_CRIME_SYSADC 0x1000
#define CRIME_CONTROL_HARD_RESET 0x0800
#define CRIME_CONTROL_SOFT_RESET 0x0400
#define CRIME_CONTROL_DOG_ENA 0x0200
#define CRIME_CONTROL_ENDIANESS 0x0100
#define CRIME_CONTROL_ENDIAN_BIG 0x0100
#define CRIME_CONTROL_ENDIAN_LITTLE 0x0000
#define CRIME_CONTROL_CQUEUE_HWM 0x000f
#define CRIME_CONTROL_CQUEUE_SHFT 0
#define CRIME_CONTROL_WBUF_HWM 0x00f0
#define CRIME_CONTROL_WBUF_SHFT 8
#define CRIME_INT_STAT (0x00000010)
#define CRIME_INT_MASK (0x00000018)
#define CRIME_SOFT_INT (0x00000020)
#define CRIME_HARD_INT (0x00000028)
/* Bits in CRIME_INT_XXX and CRIME_HARD_INT */
#define MACE_VID_IN1_INT BIT (0)
#define MACE_VID_IN2_INT BIT (1)
#define MACE_VID_OUT_INT BIT (2)
#define MACE_ETHERNET_INT BIT (3)
#define MACE_SUPERIO_INT BIT (4)
#define MACE_MISC_INT BIT (5)
#define MACE_AUDIO_INT BIT (6)
#define MACE_PCI_BRIDGE_INT BIT (7)
#define MACEPCI_SCSI0_INT BIT (8)
#define MACEPCI_SCSI1_INT BIT (9)
#define MACEPCI_SLOT0_INT BIT (10)
#define MACEPCI_SLOT1_INT BIT (11)
#define MACEPCI_SLOT2_INT BIT (12)
#define MACEPCI_SHARED0_INT BIT (13)
#define MACEPCI_SHARED1_INT BIT (14)
#define MACEPCI_SHARED2_INT BIT (15)
#define CRIME_GBE0_INT BIT (16)
#define CRIME_GBE1_INT BIT (17)
#define CRIME_GBE2_INT BIT (18)
#define CRIME_GBE3_INT BIT (19)
#define CRIME_CPUERR_INT BIT (20)
#define CRIME_MEMERR_INT BIT (21)
#define CRIME_RE_EMPTY_E_INT BIT (22)
#define CRIME_RE_FULL_E_INT BIT (23)
#define CRIME_RE_IDLE_E_INT BIT (24)
#define CRIME_RE_EMPTY_L_INT BIT (25)
#define CRIME_RE_FULL_L_INT BIT (26)
#define CRIME_RE_IDLE_L_INT BIT (27)
#define CRIME_SOFT0_INT BIT (28)
#define CRIME_SOFT1_INT BIT (29)
#define CRIME_SOFT2_INT BIT (30)
#define CRIME_SYSCORERR_INT CRIME_SOFT2_INT
#define CRIME_VICE_INT BIT (31)
/* Masks for deciding who handles the interrupt */
#define CRIME_MACE_INT_MASK 0x8f
#define CRIME_MACEISA_INT_MASK 0x70
#define CRIME_MACEPCI_INT_MASK 0xff00
#define CRIME_CRIME_INT_MASK 0xffff0000
/*
* XXX Todo
*/
#define CRIME_DOG (0x00000030)
/* We are word-play compatible but not misspelling compatible */
#define MC_GRUFF CRIME_DOG
#define CRIME_DOG_MASK (0x001fffff)
/* CRIME_DOG register bits */
#define CRIME_DOG_POWER_ON_RESET (0x00010000)
#define CRIME_DOG_WARM_RESET (0x00080000)
#define CRIME_DOG_TIMEOUT (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
#define CRIME_DOG_VALUE (0x00007fff) /* ??? */
#define CRIME_TIME (0x00000038)
#define CRIME_TIME_MASK (0x0000ffffffffffff)
#ifdef MASTER_FREQ
#undef MASTER_FREQ
#endif
#define CRIME_MASTER_FREQ 66666500 /* Crime upcounter frequency */
#define CRIME_NS_PER_TICK 15 /* for delay_calibrate */
#define CRIME_CPU_ERROR_ADDR (0x00000040)
#define CRIME_CPU_ERROR_ADDR_MASK (0x3ffffffff)
#define CRIME_CPU_ERROR_STAT (0x00000048)
/* REV_PETTY only! */
#define CRIME_CPU_ERROR_ENA (0x00000050)
/*
* bit definitions for CRIME/VICE error status and enable registers
*/
#define CRIME_CPU_ERROR_MASK 0x7UL /* cpu error stat is 3 bits */
#define CRIME_CPU_ERROR_CPU_ILL_ADDR 0x4
#define CRIME_CPU_ERROR_VICE_WRT_PRTY 0x2
#define CRIME_CPU_ERROR_CPU_WRT_PRTY 0x1
/*
* these are the definitions for the error status/enable register in
* petty crime. Note that the enable register does not exist in crime
* rev 1 and above.
*/
#define CRIME_CPU_ERROR_MASK_REV0 0x3ff /* cpu error stat is 9 bits */
#define CRIME_CPU_ERROR_CPU_INV_ADDR_RD 0x200
#define CRIME_CPU_ERROR_VICE_II 0x100
#define CRIME_CPU_ERROR_VICE_SYSAD 0x80
#define CRIME_CPU_ERROR_VICE_SYSCMD 0x40
#define CRIME_CPU_ERROR_VICE_INV_ADDR 0x20
#define CRIME_CPU_ERROR_CPU_II 0x10
#define CRIME_CPU_ERROR_CPU_SYSAD 0x8
#define CRIME_CPU_ERROR_CPU_SYSCMD 0x4
#define CRIME_CPU_ERROR_CPU_INV_ADDR_WR 0x2
#define CRIME_CPU_ERROR_CPU_INV_REG_ADDR 0x1
#define CRIME_VICE_ERROR_ADDR (0x00000058)
#define CRIME_VICE_ERROR_ADDR_MASK (0x3fffffff)
#define CRIME_MEM_CONTROL (0x00000200)
#define CRIME_MEM_CONTROL_MASK 0x3 /* 25 cent register */
#define CRIME_MEM_CONTROL_ECC_ENA 0x1
#define CRIME_MEM_CONTROL_USE_ECC_REPL 0x2
/*
* macros for CRIME memory bank control registers.
*/
#define CRIME_MEM_BANK_CONTROL(__bank) (0x00000208 + ((__bank) << 3))
#define CRIME_MEM_BANK_CONTROL_MSK 0x11f /* 9 bits 7:5 reserved */
#define CRIME_MEM_BANK_CONTROL_ADDR 0x01f
#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE 0x100
#define CRIME_MEM_BANK_CONTROL_BANK_TO_ADDR(__bank) \
(((__bank) & CRIME_MEM_BANK_CONTROL_ADDR) << 25)
#define CRIME_MEM_REFRESH_COUNTER (0x00000248)
#define CRIME_MEM_REFRESH_COUNTER_MASK 0x7ff /* 11-bit register */
#define CRIME_MAXBANKS 8
/*
* CRIME Memory error status register bit definitions
*/
#define CRIME_MEM_ERROR_STAT (0x00000250)
#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */
#define CRIME_MEM_ERROR_MACE_ID 0x0000007f
#define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080
#define CRIME_MEM_ERROR_RE_ID 0x00007f00
#define CRIME_MEM_ERROR_RE_ACCESS 0x00008000
#define CRIME_MEM_ERROR_GBE_ACCESS 0x00010000
#define CRIME_MEM_ERROR_VICE_ACCESS 0x00020000
#define CRIME_MEM_ERROR_CPU_ACCESS 0x00040000
#define CRIME_MEM_ERROR_RESERVED 0x00080000
#define CRIME_MEM_ERROR_SOFT_ERR 0x00100000
#define CRIME_MEM_ERROR_HARD_ERR 0x00200000
#define CRIME_MEM_ERROR_MULTIPLE 0x00400000
#define CRIME_MEM_ERROR_MEM_ECC_RD 0x00800000
#define CRIME_MEM_ERROR_MEM_ECC_RMW 0x01000000
#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000
#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000
#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
#define CRIME_MEM_ERROR_ADDR (0x00000258)
#define CRIME_MEM_ERROR_ADDR_MASK 0x3fffffff
#define CRIME_MEM_ERROR_ECC_SYN (0x00000260)
#define CRIME_MEM_ERROR_ECC_SYN_MASK 0xffffffff
#define CRIME_MEM_ERROR_ECC_CHK (0x00000268)
#define CRIME_MEM_ERROR_ECC_CHK_MASK 0xffffffff
#define CRIME_MEM_ERROR_ECC_REPL (0x00000270)
#define CRIME_MEM_ERROR_ECC_REPL_MASK 0xffffffff
#endif /* __ASM_CRIME_H__ */
#ifndef __ASM_IP32_IO_H__
#define __ASM_IP32_IO_H__
#include <asm/ip32/mace.h>
/*#ifdef CONFIG_MIPS_UNCACHED*/
#define UNCACHEDADDR(x) (0x9000000000000000UL | (u64)(x))
/*#else
#define UNCACHEDADDR(x) (x)
#endif*/
/*#define UNCACHEDADDR(x) (KSEG1ADDR (x)) */
#define IO_SPACE_BASE UNCACHEDADDR (MACEPCI_HI_MEMORY)
#define IO_SPACE_LIMIT 0xffffffffUL
#endif
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Harald Koerfgen
*/
#ifndef __ASM_IP32_INTS_H
#define __ASM_IP32_INTS_H
/*
* This list reflects the assignment of interrupt numbers to
* interrupting events. Order is fairly irrelevant to handling
* priority. This differs from irix.
*/
/* CPU */
#define CLOCK_IRQ 0
/* MACE */
#define MACE_VID_IN1_IRQ 1
#define MACE_VID_IN2_IRQ 2
#define MACE_VID_OUT_IRQ 3
#define MACE_ETHERNET_IRQ 4
/* SUPERIO, MISC, and AUDIO are MACEISA */
#define MACE_PCI_BRIDGE_IRQ 8
/* MACEPCI */
#define MACEPCI_SCSI0_IRQ 9
#define MACEPCI_SCSI1_IRQ 10
#define MACEPCI_SLOT0_IRQ 11
#define MACEPCI_SLOT1_IRQ 12
#define MACEPCI_SLOT2_IRQ 13
#define MACEPCI_SHARED0_IRQ 14
#define MACEPCI_SHARED1_IRQ 15
#define MACEPCI_SHARED2_IRQ 16
/* CRIME */
#define CRIME_GBE0_IRQ 17
#define CRIME_GBE1_IRQ 18
#define CRIME_GBE2_IRQ 19
#define CRIME_GBE3_IRQ 20
#define CRIME_CPUERR_IRQ 21
#define CRIME_MEMERR_IRQ 22
#define CRIME_RE_EMPTY_E_IRQ 23
#define CRIME_RE_FULL_E_IRQ 24
#define CRIME_RE_IDLE_E_IRQ 25
#define CRIME_RE_EMPTY_L_IRQ 26
#define CRIME_RE_FULL_L_IRQ 27
#define CRIME_RE_IDLE_L_IRQ 28
#define CRIME_SOFT0_IRQ 29
#define CRIME_SOFT1_IRQ 30
#define CRIME_SOFT2_IRQ 31
#define CRIME_SYSCORERR_IRQ CRIME_SOFT2_IRQ
#define CRIME_VICE_IRQ 32
/* MACEISA */
#define MACEISA_AUDIO_SW_IRQ 33
#define MACEISA_AUDIO_SC_IRQ 34
#define MACEISA_AUDIO1_DMAT_IRQ 35
#define MACEISA_AUDIO1_OF_IRQ 36
#define MACEISA_AUDIO2_DMAT_IRQ 37
#define MACEISA_AUDIO2_MERR_IRQ 38
#define MACEISA_AUDIO3_DMAT_IRQ 39
#define MACEISA_AUDIO3_MERR_IRQ 40
#define MACEISA_RTC_IRQ 41
#define MACEISA_KEYB_IRQ 42
/* MACEISA_KEYB_POLL is not an IRQ */
#define MACEISA_MOUSE_IRQ 44
/* MACEISA_MOUSE_POLL is not an IRQ */
#define MACEISA_TIMER0_IRQ 46
#define MACEISA_TIMER1_IRQ 47
#define MACEISA_TIMER2_IRQ 48
#define MACEISA_PARALLEL_IRQ 49
#define MACEISA_PAR_CTXA_IRQ 50
#define MACEISA_PAR_CTXB_IRQ 51
#define MACEISA_PAR_MERR_IRQ 52
#define MACEISA_SERIAL1_IRQ 53
#define MACEISA_SERIAL1_TDMAT_IRQ 54
#define MACEISA_SERIAL1_TDMAPR_IRQ 55
#define MACEISA_SERIAL1_TDMAME_IRQ 56
#define MACEISA_SERIAL1_RDMAT_IRQ 57
#define MACEISA_SERIAL1_RDMAOR_IRQ 58
#define MACEISA_SERIAL2_IRQ 59
#define MACEISA_SERIAL2_TDMAT_IRQ 60
#define MACEISA_SERIAL2_TDMAPR_IRQ 61
#define MACEISA_SERIAL2_TDMAME_IRQ 62
#define MACEISA_SERIAL2_RDMAT_IRQ 63
#define MACEISA_SERIAL2_RDMAOR_IRQ 64
#define IP32_IRQ_MAX MACEISA_SERIAL2_RDMAOR_IRQ
#endif /* __ASM_IP32_INTS_H */
/*
* Definitions for the SGI O2 Mace chip.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Harald Koerfgen
*/
#ifndef __ASM_MACE_H__
#define __ASM_MACE_H__
#include <asm/addrspace.h>
/*
* Address map
*/
#define MACE_BASE KSEG1ADDR(0x1f000000)
#define MACE_PCI (0x00080000)
#define MACE_VIN1 (0x00100000)
#define MACE_VIN2 (0x00180000)
#define MACE_VOUT (0x00200000)
#define MACE_ENET (0x00280000)
#define MACE_PERIF (0x00300000)
#define MACE_ISA_EXT (0x00380000)
#define MACE_AUDIO_BASE (MACE_PERIF )
#define MACE_ISA_BASE (MACE_PERIF + 0x00010000)
#define MACE_KBDMS_BASE (MACE_PERIF + 0x00020000)
#define MACE_I2C_BASE (MACE_PERIF + 0x00030000)
#define MACE_UST_BASE (MACE_PERIF + 0x00040000)
#undef BIT
#define BIT(__bit_offset) (1UL << (__bit_offset))
/*
* Mace MACEPCI interface, 32 bit regs
*/
#define MACEPCI_ERROR_ADDR (MACE_PCI )
#define MACEPCI_ERROR_FLAGS (MACE_PCI + 0x00000004)
#define MACEPCI_CONTROL (MACE_PCI + 0x00000008)
#define MACEPCI_REV (MACE_PCI + 0x0000000c)
#define MACEPCI_WFLUSH (MACE_PCI + 0x0000000c) /* ??? --IV !!! It's for flushing read buffers on PCI MEMORY accesses!!! */
#define MACEPCI_CONFIG_ADDR (MACE_PCI + 0x00000cf8)
#define MACEPCI_CONFIG_DATA (MACE_PCI + 0x00000cfc)
#define MACEPCI_LOW_MEMORY 0x1a000000
#define MACEPCI_LOW_IO 0x18000000
#define MACEPCI_SWAPPED_VIEW 0
#define MACEPCI_NATIVE_VIEW 0x40000000
#define MACEPCI_IO 0x80000000
/*#define MACEPCI_HI_MEMORY 0x0000000280000000UL * This mipght be just 0x0000000200000000UL 2G more :) (or maybe it is different between 1.1 & 1.5 */
#define MACEPCI_HI_MEMORY 0x0000000200000000UL /* This mipght be just 0x0000000200000000UL 2G more :) (or maybe it is different between 1.1 & 1.5 */
#define MACEPCI_HI_IO 0x0000000100000000UL
/*
* Bits in the MACEPCI_CONTROL register
*/
#define MACEPCI_CONTROL_INT(x) BIT(x)
#define MACEPCI_CONTROL_INT_MASK 0xff
#define MACEPCI_CONTROL_SERR_ENA BIT(8)
#define MACEPCI_CONTROL_ARB_N6 BIT(9)
#define MACEPCI_CONTROL_PARITY_ERR BIT(10)
#define MACEPCI_CONTROL_MRMRA_ENA BIT(11)
#define MACEPCI_CONTROL_ARB_N3 BIT(12)
#define MACEPCI_CONTROL_ARB_N4 BIT(13)
#define MACEPCI_CONTROL_ARB_N5 BIT(14)
#define MACEPCI_CONTROL_PARK_LIU BIT(15)
#define MACEPCI_CONTROL_INV_INT(x) BIT(16+x)
#define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000
#define MACEPCI_CONTROL_OVERRUN_INT BIT(24)
#define MACEPCI_CONTROL_PARITY_INT BIT(25)
#define MACEPCI_CONTROL_SERR_INT BIT(26)
#define MACEPCI_CONTROL_IT_INT BIT(27)
#define MACEPCI_CONTROL_RE_INT BIT(28)
#define MACEPCI_CONTROL_DPED_INT BIT(29)
#define MACEPCI_CONTROL_TAR_INT BIT(30)
#define MACEPCI_CONTROL_MAR_INT BIT(31)
/*
* Bits in the MACE_PCI error register
*/
#define MACEPCI_ERROR_MASTER_ABORT BIT(31)
#define MACEPCI_ERROR_TARGET_ABORT BIT(30)
#define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29)
#define MACEPCI_ERROR_RETRY_ERR BIT(28)
#define MACEPCI_ERROR_ILLEGAL_CMD BIT(27)
#define MACEPCI_ERROR_SYSTEM_ERR BIT(26)
#define MACEPCI_ERROR_INTERRUPT_TEST BIT(25)
#define MACEPCI_ERROR_PARITY_ERR BIT(24)
#define MACEPCI_ERROR_OVERRUN BIT(23)
#define MACEPCI_ERROR_RSVD BIT(22)
#define MACEPCI_ERROR_MEMORY_ADDR BIT(21)
#define MACEPCI_ERROR_CONFIG_ADDR BIT(20)
#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID BIT(19)
#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID BIT(18)
#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID BIT(17)
#define MACEPCI_ERROR_RETRY_ADDR_VALID BIT(16)
#define MACEPCI_ERROR_SIG_TABORT BIT(4)
#define MACEPCI_ERROR_DEVSEL_MASK 0xc0
#define MACEPCI_ERROR_DEVSEL_FAST 0
#define MACEPCI_ERROR_DEVSEL_MED 0x40
#define MACEPCI_ERROR_DEVSEL_SLOW 0x80
#define MACEPCI_ERROR_FBB BIT(1)
#define MACEPCI_ERROR_66MHZ BIT(0)
/*
* Mace timer registers - 64 bit regs (63:32 are UST, 31:0 are MSC)
*/
#define MSC_PART(__reg) ((__reg) & 0x00000000ffffffff)
#define UST_PART(__reg) (((__reg) & 0xffffffff00000000) >> 32)
#define MACE_UST_UST (MACE_UST_BASE ) /* Universial system time */
#define MACE_UST_COMPARE1 (MACE_UST_BASE + 0x00000008) /* Interrupt compare reg 1 */
#define MACE_UST_COMPARE2 (MACE_UST_BASE + 0x00000010) /* Interrupt compare reg 2 */
#define MACE_UST_COMPARE3 (MACE_UST_BASE + 0x00000018) /* Interrupt compare reg 3 */
#define MACE_UST_PERIOD_NS 960 /* UST Period in ns */
#define MACE_UST_AIN_MSC (MACE_UST_BASE + 0x00000020) /* Audio in MSC/UST pair */
#define MACE_UST_AOUT1_MSC (MACE_UST_BASE + 0x00000028) /* Audio out 1 MSC/UST pair */
#define MACE_UST_AOUT2_MSC (MACE_UST_BASE + 0x00000030) /* Audio out 2 MSC/UST pair */
#define MACE_VIN1_MSC_UST (MACE_UST_BASE + 0x00000038) /* Video In 1 MSC/UST pair */
#define MACE_VIN2_MSC_UST (MACE_UST_BASE + 0x00000040) /* Video In 2 MSC/UST pair */
#define MACE_VOUT_MSC_UST (MACE_UST_BASE + 0x00000048) /* Video out MSC/UST pair */
/*
* Mace "ISA" peripherals
*/
#define MACEISA_EPP_BASE (MACE_ISA_EXT )
#define MACEISA_ECP_BASE (MACE_ISA_EXT + 0x00008000)
#define MACEISA_SER1_BASE (MACE_ISA_EXT + 0x00010000)
#define MACEISA_SER2_BASE (MACE_ISA_EXT + 0x00018000)
#define MACEISA_RTC_BASE (MACE_ISA_EXT + 0x00020000)
#define MACEISA_GAME_BASE (MACE_ISA_EXT + 0x00030000)
/*
* Ringbase address and reset register - 64 bits
*/
#define MACEISA_RINGBASE MACE_ISA_BASE
/*
* Flash-ROM/LED/DP-RAM/NIC Controller Register - 64 bits (?)
*/
#define MACEISA_FLASH_NIC_REG (MACE_ISA_BASE + 0x00000008)
/*
* Bit definitions for that
*/
#define MACEISA_FLASH_WE BIT(0) /* 1=> Enable FLASH writes */
#define MACEISA_PWD_CLEAR BIT(1) /* 1=> PWD CLEAR jumper detected */
#define MACEISA_NIC_DEASSERT BIT(2)
#define MACEISA_NIC_DATA BIT(3)
#define MACEISA_LED_RED BIT(4) /* 0=> Illuminate RED LED */
#define MACEISA_LED_GREEN BIT(5) /* 0=> Illuminate GREEN LED */
#define MACEISA_DP_RAM_ENABLE BIT(6)
/*
* ISA interrupt and status registers - 32 bit
*/
#define MACEISA_INT_STAT (MACE_ISA_BASE + 0x00000014)
#define MACEISA_INT_MASK (MACE_ISA_BASE + 0x0000001c)
/*
* Bits in the status/mask registers
*/
#define MACEISA_AUDIO_SW_INT BIT (0)
#define MACEISA_AUDIO_SC_INT BIT (1)
#define MACEISA_AUDIO1_DMAT_INT BIT (2)
#define MACEISA_AUDIO1_OF_INT BIT (3)
#define MACEISA_AUDIO2_DMAT_INT BIT (4)
#define MACEISA_AUDIO2_MERR_INT BIT (5)
#define MACEISA_AUDIO3_DMAT_INT BIT (6)
#define MACEISA_AUDIO3_MERR_INT BIT (7)
#define MACEISA_RTC_INT BIT (8)
#define MACEISA_KEYB_INT BIT (9)
#define MACEISA_KEYB_POLL_INT BIT (10)
#define MACEISA_MOUSE_INT BIT (11)
#define MACEISA_MOUSE_POLL_INT BIT (12)
#define MACEISA_TIMER0_INT BIT (13)
#define MACEISA_TIMER1_INT BIT (14)
#define MACEISA_TIMER2_INT BIT (15)
#define MACEISA_PARALLEL_INT BIT (16)
#define MACEISA_PAR_CTXA_INT BIT (17)
#define MACEISA_PAR_CTXB_INT BIT (18)
#define MACEISA_PAR_MERR_INT BIT (19)
#define MACEISA_SERIAL1_INT BIT (20)
#define MACEISA_SERIAL1_TDMAT_INT BIT (21)
#define MACEISA_SERIAL1_TDMAPR_INT BIT (22)
#define MACEISA_SERIAL1_TDMAME_INT BIT (23)
#define MACEISA_SERIAL1_RDMAT_INT BIT (24)
#define MACEISA_SERIAL1_RDMAOR_INT BIT (25)
#define MACEISA_SERIAL2_INT BIT (26)
#define MACEISA_SERIAL2_TDMAT_INT BIT (27)
#define MACEISA_SERIAL2_TDMAPR_INT BIT (28)
#define MACEISA_SERIAL2_TDMAME_INT BIT (29)
#define MACEISA_SERIAL2_RDMAT_INT BIT (30)
#define MACEISA_SERIAL2_RDMAOR_INT BIT (31)
#ifndef __ASSEMBLY__
#include <asm/types.h>
/*
* XXX Some of these are probably not needed (or even legal?)
*/
static inline u8 mace_read_8 (unsigned long __offset)
{
return *((volatile u8 *) (MACE_BASE + __offset));
}
static inline u16 mace_read_16 (unsigned long __offset)
{
return *((volatile u16 *) (MACE_BASE + __offset));
}
static inline u32 mace_read_32 (unsigned long __offset)
{
return *((volatile u32 *) (MACE_BASE + __offset));
}
static inline u64 mace_read_64 (unsigned long __offset)
{
return *((volatile u64 *) (MACE_BASE + __offset));
}
static inline void mace_write_8 (unsigned long __offset, u8 __val)
{
*((volatile u8 *) (MACE_BASE + __offset)) = __val;
}
static inline void mace_write_16 (unsigned long __offset, u16 __val)
{
*((volatile u16 *) (MACE_BASE + __offset)) = __val;
}
static inline void mace_write_32 (unsigned long __offset, u32 __val)
{
*((volatile u32 *) (MACE_BASE + __offset)) = __val;
}
static inline void mace_write_64 (unsigned long __offset, u64 __val)
{
*((volatile u64 *) (MACE_BASE + __offset)) = __val;
}
/* Call it whenever device needs to read data from main memory coherently */
static inline void mace_inv_read_buffers(void)
{
/* mace_write_32(MACEPCI_WFLUSH,0xffffffff);*/
}
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_MACE_H__ */
/*
* machine.h -- Machine/group probing for ip32
*
* Copyright (C) 2001 Keith M Wesolowski
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#ifndef _ASM_IP32_MACHINE_H
#define _ASM_IP32_MACHINE_H
#include <linux/config.h>
#ifdef CONFIG_SGI_IP32
#define SGI_MACH_O2 0x3201
#endif /* CONFIG_SGI_IP32 */
#endif /* _ASM_SGI_MACHINE_H */
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