Commit 2afa3265 authored by Slava Grigorev's avatar Slava Grigorev Committed by Alex Deucher

radeon/audio: fix DP audio on DCE6

Split DCE6 and DCE8 programming of DCCG_AUDIO_DTO1
registers to properly enable DP audio for both DCE
revisions.
Signed-off-by: default avatarSlava Grigorev <slava.grigorev@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b983a8f4
...@@ -26,6 +26,9 @@ ...@@ -26,6 +26,9 @@
#include "radeon_audio.h" #include "radeon_audio.h"
#include "sid.h" #include "sid.h"
#define DCE8_DCCG_AUDIO_DTO1_PHASE 0x05b8
#define DCE8_DCCG_AUDIO_DTO1_MODULE 0x05bc
u32 dce6_endpoint_rreg(struct radeon_device *rdev, u32 dce6_endpoint_rreg(struct radeon_device *rdev,
u32 block_offset, u32 reg) u32 block_offset, u32 reg)
{ {
...@@ -284,8 +287,13 @@ void dce6_dp_audio_set_dto(struct radeon_device *rdev, ...@@ -284,8 +287,13 @@ void dce6_dp_audio_set_dto(struct radeon_device *rdev,
* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
*/ */
if (ASIC_IS_DCE8(rdev)) {
WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
} else {
WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
WREG32(DCCG_AUDIO_DTO1_MODULE, clock); WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
}
} }
void dce6_dp_enable(struct drm_encoder *encoder, bool enable) void dce6_dp_enable(struct drm_encoder *encoder, bool enable)
......
...@@ -912,8 +912,8 @@ ...@@ -912,8 +912,8 @@
#define DCCG_AUDIO_DTO0_PHASE 0x05b0 #define DCCG_AUDIO_DTO0_PHASE 0x05b0
#define DCCG_AUDIO_DTO0_MODULE 0x05b4 #define DCCG_AUDIO_DTO0_MODULE 0x05b4
#define DCCG_AUDIO_DTO1_PHASE 0x05b8 #define DCCG_AUDIO_DTO1_PHASE 0x05c0
#define DCCG_AUDIO_DTO1_MODULE 0x05bc #define DCCG_AUDIO_DTO1_MODULE 0x05c4
#define AFMT_AUDIO_SRC_CONTROL 0x713c #define AFMT_AUDIO_SRC_CONTROL 0x713c
#define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0) #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0)
......
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