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Commit 2b889c52 authored by Andrew Morton's avatar Andrew Morton Committed by Linus Torvalds
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[PATCH] sn: Code changes for interrupt redirect 

From: Pat Gefre <pfg@sgi.com>

Code changes for interrupt redirect
parent 439ab81e
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Showing with 306 additions and 1226 deletions
arch/ia64/sn/io/sn2/ml_SN_intr.c
View file @ 2b889c52
...@@ -81,7 +81,7 @@ void intr_init_vecblk(cnodeid_t node) ...@@ -81,7 +81,7 @@ void intr_init_vecblk(cnodeid_t node)
/* Config and enable UART interrupt, all nodes. */ /* Config and enable UART interrupt, all nodes. */
local5_config.sh_local_int5_config_regval = 0; local5_config.sh_local_int5_config_regval = 0;
local5_config.sh_local_int5_config_s.idx = SGI_UART_VECTOR; local5_config.sh_local_int5_config_s.idx = SGI_UART_VECTOR;
local5_config.sh_local_int5_config_s.pid = cpu0; local5_config.sh_local_int5_config_s.pid = cpu;
HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT5_CONFIG), HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT5_CONFIG),
local5_config.sh_local_int5_config_regval); local5_config.sh_local_int5_config_regval);
...@@ -222,7 +222,7 @@ static cpuid_t intr_cpu_choose_from_node(cnodeid_t cnode) ...@@ -222,7 +222,7 @@ static cpuid_t intr_cpu_choose_from_node(cnodeid_t cnode)
int intrs; int intrs;
cpu = cnode_slice_to_cpuid(cnode, slice); cpu = cnode_slice_to_cpuid(cnode, slice);
if (cpu == num_online_cpus()) if (cpu == NR_CPUS)
continue; continue;
if (!cpu_online(cpu)) if (!cpu_online(cpu))
continue; continue;
......
arch/ia64/sn/io/sn2/pcibr/Makefile
View file @ 2b889c52
...@@ -9,5 +9,8 @@ ...@@ -9,5 +9,8 @@
# Makefile for the sn2 specific pci bridge routines. # Makefile for the sn2 specific pci bridge routines.
# #
obj-y += pcibr_ate.o pcibr_config.o pcibr_dvr.o pcibr_hints.o pcibr_intr.o pcibr_rrb.o \ obj-y += pcibr_ate.o pcibr_config.o \
pcibr_slot.o pcibr_error.o pcibr_dvr.o pcibr_hints.o \
pcibr_intr.o pcibr_rrb.o \
pcibr_slot.o pcibr_error.o \
pcibr_reg.o
arch/ia64/sn/io/sn2/shub_intr.c
View file @ 2b889c52
...@@ -25,10 +25,8 @@ ...@@ -25,10 +25,8 @@
#include <asm/sn/klconfig.h> #include <asm/sn/klconfig.h>
#include <asm/sn/sn2/shub_mmr.h> #include <asm/sn/sn2/shub_mmr.h>
#include <asm/sn/sn_cpuid.h> #include <asm/sn/sn_cpuid.h>
#include <asm/sn/pci/pcibr.h>
#include <asm/sn/pci/pcibr_private.h>
typedef void pci_bridge_t;
/* ARGSUSED */ /* ARGSUSED */
void void
...@@ -39,11 +37,15 @@ hub_intr_init(vertex_hdl_t hubv) ...@@ -39,11 +37,15 @@ hub_intr_init(vertex_hdl_t hubv)
xwidgetnum_t xwidgetnum_t
hub_widget_id(nasid_t nasid) hub_widget_id(nasid_t nasid)
{ {
hubii_wcr_t ii_wcr; /* the control status register */
if (!(nasid & 1)) {
hubii_wcr_t ii_wcr; /* the control status register */
ii_wcr.wcr_reg_value = REMOTE_HUB_L(nasid,IIO_WCR); ii_wcr.wcr_reg_value = REMOTE_HUB_L(nasid,IIO_WCR);
return ii_wcr.wcr_fields_s.wcr_widget_id; return ii_wcr.wcr_fields_s.wcr_widget_id;
} else {
/* ICE does not have widget id. */
return(-1);
}
} }
static hub_intr_t static hub_intr_t
...@@ -52,7 +54,7 @@ do_hub_intr_alloc(vertex_hdl_t dev, ...@@ -52,7 +54,7 @@ do_hub_intr_alloc(vertex_hdl_t dev,
vertex_hdl_t owner_dev, vertex_hdl_t owner_dev,
int uncond_nothread) int uncond_nothread)
{ {
cpuid_t cpu = 0; cpuid_t cpu;
int vector; int vector;
hub_intr_t intr_hdl; hub_intr_t intr_hdl;
cnodeid_t cnode; cnodeid_t cnode;
...@@ -97,7 +99,7 @@ do_hub_intr_alloc(vertex_hdl_t dev, ...@@ -97,7 +99,7 @@ do_hub_intr_alloc(vertex_hdl_t dev,
intr_hdl->i_bit = vector; intr_hdl->i_bit = vector;
intr_hdl->i_flags |= HUB_INTR_IS_ALLOCED; intr_hdl->i_flags |= HUB_INTR_IS_ALLOCED;
return(intr_hdl); return intr_hdl;
} }
hub_intr_t hub_intr_t
...@@ -187,3 +189,73 @@ hub_intr_disconnect(hub_intr_t intr_hdl) ...@@ -187,3 +189,73 @@ hub_intr_disconnect(hub_intr_t intr_hdl)
ASSERT(rv == 0); ASSERT(rv == 0);
intr_hdl->i_flags &= ~HUB_INTR_IS_CONNECTED; intr_hdl->i_flags &= ~HUB_INTR_IS_CONNECTED;
} }
/*
* Redirect an interrupt to another cpu.
*/
void
sn_shub_redirect_intr(pcibr_intr_t intr, unsigned long cpu)
{
unsigned long bit;
int cpuphys, slice;
nasid_t nasid;
unsigned long xtalk_addr;
void *bridge = intr->bi_soft->bs_base;
int irq;
int i;
int old_cpu;
int new_cpu;
cpuphys = cpu_physical_id(cpu);
slice = cpu_physical_id_to_slice(cpuphys);
nasid = cpu_physical_id_to_nasid(cpuphys);
for (i = CPUS_PER_NODE - 1; i >= 0; i--) {
new_cpu = nasid_slice_to_cpuid(nasid, i);
if (new_cpu == NR_CPUS) {
continue;
}
if (!cpu_online(new_cpu)) {
continue;
}
break;
}
if (enable_shub_wars_1_1() && slice != i) {
printk("smp_affinity WARNING: SHUB 1.1 present: cannot target cpu %d, targeting cpu %d instead.\n",(int)cpu, new_cpu);
cpu = new_cpu;
slice = i;
}
if (slice) {
xtalk_addr = SH_II_INT1 | ((unsigned long)nasid << 36) | (1UL << 47);
} else {
xtalk_addr = SH_II_INT0 | ((unsigned long)nasid << 36) | (1UL << 47);
}
for (bit = 0; bit < 8; bit++) {
if (intr->bi_ibits & (1 << bit) ) {
/* Disable interrupts. */
pcireg_intr_enable_bit_clr(bridge, bit);
/* Reset Host address (Interrupt destination) */
pcireg_intr_addr_addr_set(bridge, bit, xtalk_addr);
/* Enable interrupt */
pcireg_intr_enable_bit_set(bridge, bit);
/* Force an interrupt, just in case. */
pcireg_force_intr_set(bridge, bit);
}
}
irq = intr->bi_irq;
old_cpu = intr->bi_cpu;
if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq) {
pdacpu(cpu)->sn_first_irq = irq;
}
if (pdacpu(cpu)->sn_last_irq < irq) {
pdacpu(cpu)->sn_last_irq = irq;
}
pdacpu(old_cpu)->sn_num_irqs--;
pdacpu(cpu)->sn_num_irqs++;
intr->bi_cpu = (int)cpu;
}
arch/ia64/sn/kernel/irq.c
View file @ 2b889c52
...@@ -121,6 +121,7 @@ sn_set_affinity_irq(unsigned int irq, cpumask_t mask) ...@@ -121,6 +121,7 @@ sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
pcibr_intr_list_t p = pcibr_intr_list[irq]; pcibr_intr_list_t p = pcibr_intr_list[irq];
pcibr_intr_t intr; pcibr_intr_t intr;
int cpu; int cpu;
extern void sn_shub_redirect_intr(pcibr_intr_t intr, unsigned long cpu);
extern void sn_tio_redirect_intr(pcibr_intr_t intr, unsigned long cpu); extern void sn_tio_redirect_intr(pcibr_intr_t intr, unsigned long cpu);
if (p == NULL) if (p == NULL)
...@@ -132,6 +133,11 @@ sn_set_affinity_irq(unsigned int irq, cpumask_t mask) ...@@ -132,6 +133,11 @@ sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
return; return;
cpu = first_cpu(mask); cpu = first_cpu(mask);
if (IS_PIC_SOFT(intr->bi_soft) ) {
sn_shub_redirect_intr(intr, cpu);
} else {
return;
}
(void) set_irq_affinity_info(irq, cpu_physical_id(intr->bi_cpu), redir); (void) set_irq_affinity_info(irq, cpu_physical_id(intr->bi_cpu), redir);
#endif /* CONFIG_SMP */ #endif /* CONFIG_SMP */
} }
......
arch/ia64/sn/kernel/setup.c
View file @ 2b889c52
...@@ -58,6 +58,7 @@ extern void bte_init_node (nodepda_t *, cnodeid_t); ...@@ -58,6 +58,7 @@ extern void bte_init_node (nodepda_t *, cnodeid_t);
extern void bte_init_cpu (void); extern void bte_init_cpu (void);
extern void sn_timer_init(void); extern void sn_timer_init(void);
extern unsigned long last_time_offset; extern unsigned long last_time_offset;
extern void init_platform_hubinfo(nodepda_t **nodepdaindr);
extern void (*ia64_mark_idle)(int); extern void (*ia64_mark_idle)(int);
extern void snidle(int); extern void snidle(int);
...@@ -220,6 +221,8 @@ sn_setup(char **cmdline_p) ...@@ -220,6 +221,8 @@ sn_setup(char **cmdline_p)
int major = sn_sal_rev_major(), minor = sn_sal_rev_minor(); int major = sn_sal_rev_major(), minor = sn_sal_rev_minor();
extern nasid_t snia_get_master_baseio_nasid(void); extern nasid_t snia_get_master_baseio_nasid(void);
extern void sn_cpu_init(void); extern void sn_cpu_init(void);
extern nasid_t snia_get_console_nasid(void);
MAX_DMA_ADDRESS = PAGE_OFFSET + MAX_PHYS_MEMORY; MAX_DMA_ADDRESS = PAGE_OFFSET + MAX_PHYS_MEMORY;
......
include/asm-ia64/sn/pci/pcibr_private.h
View file @ 2b889c52
...@@ -43,6 +43,10 @@ cfg_p pcibr_slot_config_addr(bridge_t *, pciio_slot_t, int); ...@@ -43,6 +43,10 @@ cfg_p pcibr_slot_config_addr(bridge_t *, pciio_slot_t, int);
cfg_p pcibr_func_config_addr(bridge_t *, pciio_bus_t bus, pciio_slot_t, pciio_function_t, int); cfg_p pcibr_func_config_addr(bridge_t *, pciio_bus_t bus, pciio_slot_t, pciio_function_t, int);
unsigned pcibr_slot_config_get(bridge_t *, pciio_slot_t, int); unsigned pcibr_slot_config_get(bridge_t *, pciio_slot_t, int);
unsigned pcibr_func_config_get(bridge_t *, pciio_slot_t, pciio_function_t, int); unsigned pcibr_func_config_get(bridge_t *, pciio_slot_t, pciio_function_t, int);
extern void pcireg_intr_enable_bit_clr(void *, uint64_t);
extern void pcireg_intr_enable_bit_set(void *, uint64_t);
extern void pcireg_intr_addr_addr_set(void *, int, uint64_t);
extern void pcireg_force_intr_set(void *, int);
void pcibr_debug(uint32_t, vertex_hdl_t, char *, ...); void pcibr_debug(uint32_t, vertex_hdl_t, char *, ...);
void pcibr_slot_config_set(bridge_t *, pciio_slot_t, int, unsigned); void pcibr_slot_config_set(bridge_t *, pciio_slot_t, int, unsigned);
void pcibr_func_config_set(bridge_t *, pciio_slot_t, pciio_function_t, int, void pcibr_func_config_set(bridge_t *, pciio_slot_t, pciio_function_t, int,
...@@ -304,6 +308,9 @@ struct pcibr_intr_wrap_s { ...@@ -304,6 +308,9 @@ struct pcibr_intr_wrap_s {
#define PV862253 (1 << 1) /* PIC: don't enable write req RAM parity checking */ #define PV862253 (1 << 1) /* PIC: don't enable write req RAM parity checking */
#define PV867308 (3 << 1) /* PIC: make LLP error interrupts FATAL for PIC */ #define PV867308 (3 << 1) /* PIC: make LLP error interrupts FATAL for PIC */
/* Bridgetype macros given a pcibr_soft structure */
#define IS_PIC_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_PIC)
/* defines for pcibr_soft_s->bs_bridge_mode */ /* defines for pcibr_soft_s->bs_bridge_mode */
#define PCIBR_BRIDGEMODE_PCI_33 0x0 #define PCIBR_BRIDGEMODE_PCI_33 0x0
......
include/asm-ia64/sn/pci/pic.h
View file @ 2b889c52
...@@ -775,1216 +775,204 @@ extern pciio_provider_t pci_pic_provider; ...@@ -775,1216 +775,204 @@ extern pciio_provider_t pci_pic_provider;
* *
*/ */
typedef uint64_t picreg_t; typedef uint64_t picreg_t;
typedef uint64_t picate_t;
/*********************************************************************
* PIC register structures /*****************************************************************************
* *********************** PIC MMR structure mapping ***************************
*/ *****************************************************************************/
/* /* NOTE: PIC WAR. PV#854697. PIC does not allow writes just to [31:0]
* Identification Register * of a 64-bit register. When writing PIC registers, always write the
* * entire 64 bits.
* The Identification register is a read only register used by the host CPU */
* during configuration to determine the type of the widget. The format is
* the same as defined in IEEE 1149.1 JTAG Device Identification Register. typedef volatile struct pic_s {
*/
typedef union pic_id_reg_u { /* 0x000000-0x00FFFF -- Local Registers */
picreg_t pic_id_reg_regval;
struct { /* 0x000000-0x000057 -- Standard Widget Configuration */
picreg_t : 32; /* 63:32 */ picreg_t p_wid_id; /* 0x000000 */
picreg_t rev_num : 4; /* 31:28 */ picreg_t p_wid_stat; /* 0x000008 */
picreg_t part_num : 16; /* 27:12 */ picreg_t p_wid_err_upper; /* 0x000010 */
picreg_t mfg_num : 11; /* 11:1 */ picreg_t p_wid_err_lower; /* 0x000018 */
picreg_t : 1; /* 0:0 */ #define p_wid_err p_wid_err_lower
} pic_id_reg_fld_s; picreg_t p_wid_control; /* 0x000020 */
} pic_id_reg_u_t; picreg_t p_wid_req_timeout; /* 0x000028 */
/* picreg_t p_wid_int_upper; /* 0x000030 */
* Status Register picreg_t p_wid_int_lower; /* 0x000038 */
* #define p_wid_int p_wid_int_lower
* The status register is a read register which holds status information of the picreg_t p_wid_err_cmdword; /* 0x000040 */
* Bus Subsection. picreg_t p_wid_llp; /* 0x000048 */
*/ picreg_t p_wid_tflush; /* 0x000050 */
typedef union pic_stat_reg_u {
picreg_t pic_stat_reg_regval; /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
struct { picreg_t p_wid_aux_err; /* 0x000058 */
picreg_t : 28; /* 63:36 */ picreg_t p_wid_resp_upper; /* 0x000060 */
picreg_t pci_x_speed : 2; /* 35:34 */ picreg_t p_wid_resp_lower; /* 0x000068 */
picreg_t pci_x_active : 1; /* 33:33 */ #define p_wid_resp p_wid_resp_lower
picreg_t : 1; /* 32:32 */ picreg_t p_wid_tst_pin_ctrl; /* 0x000070 */
picreg_t llp_rec_cnt : 8; /* 31:24 */ picreg_t p_wid_addr_lkerr; /* 0x000078 */
picreg_t llp_tx_cnt : 8; /* 23:16 */
picreg_t rx_credit_cnt : 4; /* 15:12 */ /* 0x000080-0x00008F -- PMU & MAP */
picreg_t tx_credit_cnt : 4; /* 11:8 */ picreg_t p_dir_map; /* 0x000080 */
picreg_t pci_misc_input : 8; /* 7:0 */ picreg_t _pad_000088; /* 0x000088 */
} pic_stat_reg_fld_s;
} pic_stat_reg_u_t; /* 0x000090-0x00009F -- SSRAM */
/* picreg_t p_map_fault; /* 0x000090 */
* Upper Address Holding Register Bus Side Errors picreg_t _pad_000098; /* 0x000098 */
*
* The upper address holding register is a read only register which contains /* 0x0000A0-0x0000AF -- Arbitration */
* the upper 16-bits of the address when certain error occurs (see error cases picreg_t p_arb; /* 0x0000A0 */
* chapter). Subsequent errors are not logged until the error is cleared. The picreg_t _pad_0000A8; /* 0x0000A8 */
* last logged value is held until the group is cleared and enabled.
*/ /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
typedef union pic_upper_bus_err_u { picreg_t p_ate_parity_err; /* 0x0000B0 */
picreg_t pic_upper_bus_err_regval; picreg_t _pad_0000B8; /* 0x0000B8 */
struct {
picreg_t : 32; /* 63:32 */ /* 0x0000C0-0x0000FF -- PCI/GIO */
picreg_t : 16; /* 31:16 */ picreg_t p_bus_timeout; /* 0x0000C0 */
picreg_t upp_addr : 16; /* 15:0 */ picreg_t p_pci_cfg; /* 0x0000C8 */
} pic_upper_bus_err_fld_s; picreg_t p_pci_err_upper; /* 0x0000D0 */
} pic_upper_bus_err_u_t; picreg_t p_pci_err_lower; /* 0x0000D8 */
/* #define p_pci_err p_pci_err_lower
* Lower Address Holding Register Bus Side Errors picreg_t _pad_0000E0[4]; /* 0x0000{E0..F8} */
*
* The lower address holding register is a read only register which contains /* 0x000100-0x0001FF -- Interrupt */
* the address which either can be accessed as a word or double word. Sub- picreg_t p_int_status; /* 0x000100 */
* sequent errors are not logged until the error is cleared. The last logged picreg_t p_int_enable; /* 0x000108 */
* value is held until the group is cleared and enabled. picreg_t p_int_rst_stat; /* 0x000110 */
*/ picreg_t p_int_mode; /* 0x000118 */
typedef union pic_lower_bus_err_u { picreg_t p_int_device; /* 0x000120 */
picreg_t pic_lower_bus_err_regval; picreg_t p_int_host_err; /* 0x000128 */
struct { picreg_t p_int_addr[8]; /* 0x0001{30,,,68} */
picreg_t : 16; /* 63:48 */ picreg_t p_err_int_view; /* 0x000170 */
picreg_t upp_addr : 16; /* 47:32 */ picreg_t p_mult_int; /* 0x000178 */
picreg_t low_addr : 32; /* 31:0 */ picreg_t p_force_always[8]; /* 0x0001{80,,,B8} */
} pic_lower_bus_err_fld_s; picreg_t p_force_pin[8]; /* 0x0001{C0,,,F8} */
} pic_lower_bus_err_u_t;
/* /* 0x000200-0x000298 -- Device */
* Control Register picreg_t p_device[4]; /* 0x0002{00,,,18} */
* picreg_t _pad_000220[4]; /* 0x0002{20,,,38} */
* The control register is a read/write register which holds control informa- picreg_t p_wr_req_buf[4]; /* 0x0002{40,,,58} */
* tion for the bus subsection. picreg_t _pad_000260[4]; /* 0x0002{60,,,78} */
*/ picreg_t p_rrb_map[2]; /* 0x0002{80,,,88} */
typedef union pic_control_reg_u { #define p_even_resp p_rrb_map[0] /* 0x000280 */
picreg_t pic_control_reg_regval; #define p_odd_resp p_rrb_map[1] /* 0x000288 */
struct { picreg_t p_resp_status; /* 0x000290 */
picreg_t : 32; /* 63:32 */ picreg_t p_resp_clear; /* 0x000298 */
picreg_t : 4; /* 31:28 */
picreg_t rst_pin_n : 4; /* 27:24 */ picreg_t _pad_0002A0[12]; /* 0x0002{A0..F8} */
picreg_t : 1; /* 23:23 */
picreg_t mem_swap : 1; /* 22:22 */ /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
picreg_t page_size : 1; /* 21:21 */ struct {
picreg_t : 4; /* 20:17 */ picreg_t upper; /* 0x0003{00,,,F0} */
picreg_t f_bad_pkt : 1; /* 16:16 */ picreg_t lower; /* 0x0003{08,,,F8} */
picreg_t llp_xbar_crd : 4; /* 15:12 */ } p_buf_addr_match[16];
picreg_t clr_rllp_cnt : 1; /* 11:11 */
picreg_t clr_tllp_cnt : 1; /* 10:10 */ /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
picreg_t sys_end : 1; /* 9:9 */ struct {
picreg_t : 3; /* 8:6 */ picreg_t flush_w_touch; /* 0x000{400,,,5C0} */
picreg_t pci_speed : 2; /* 5:4 */ picreg_t flush_wo_touch; /* 0x000{408,,,5C8} */
picreg_t widget_id : 4; /* 3:0 */ picreg_t inflight; /* 0x000{410,,,5D0} */
} pic_control_reg_fld_s; picreg_t prefetch; /* 0x000{418,,,5D8} */
} pic_control_reg_u_t; picreg_t total_pci_retry; /* 0x000{420,,,5E0} */
/* picreg_t max_pci_retry; /* 0x000{428,,,5E8} */
* PCI/PCI-X Request Time-out Value Register picreg_t max_latency; /* 0x000{430,,,5F0} */
* picreg_t clear_all; /* 0x000{438,,,5F8} */
* This register contains the reload value for the response timer. The request } p_buf_count[8];
* timer counts every 960 nS (32 PCI clocks)
*/
typedef union pic_pci_req_to_u { /* 0x000600-0x0009FF -- PCI/X registers */
picreg_t pic_pci_req_to_regval; picreg_t p_pcix_bus_err_addr; /* 0x000600 */
struct { picreg_t p_pcix_bus_err_attr; /* 0x000608 */
picreg_t : 32; /* 63:32 */ picreg_t p_pcix_bus_err_data; /* 0x000610 */
picreg_t : 12; /* 31:20 */ picreg_t p_pcix_pio_split_addr; /* 0x000618 */
picreg_t time_out : 20; /* 19:0 */ picreg_t p_pcix_pio_split_attr; /* 0x000620 */
} pic_pci_req_to_fld_s; picreg_t p_pcix_dma_req_err_attr; /* 0x000628 */
} pic_pci_req_to_u_t; picreg_t p_pcix_dma_req_err_addr; /* 0x000630 */
/* picreg_t p_pcix_timeout; /* 0x000638 */
* Interrupt Destination Upper Address Register
* picreg_t _pad_000640[120]; /* 0x000{640,,,9F8} */
* The interrupt destination upper address register is a read/write register
* containing the upper 16-bits of address of the host to which the interrupt /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
* is targeted. In addition the target ID is also contained in this register for struct {
* use in Crosstalk mode. picreg_t p_buf_addr; /* 0x000{A00,,,AF0} */
*/ picreg_t p_buf_attr; /* 0X000{A08,,,AF8} */
typedef union pic_int_desc_upper_u { } p_pcix_read_buf_64[16];
picreg_t pic_int_desc_upper_regval;
struct { struct {
picreg_t : 32; /* 63:32 */ picreg_t p_buf_addr; /* 0x000{B00,,,BE0} */
picreg_t : 12; /* 31:20 */ picreg_t p_buf_attr; /* 0x000{B08,,,BE8} */
picreg_t target_id : 4; /* 19:16 */ picreg_t p_buf_valid; /* 0x000{B10,,,BF0} */
picreg_t upp_addr : 16; /* 15:0 */ picreg_t __pad1; /* 0x000{B18,,,BF8} */
} pic_int_desc_upper_fld_s; } p_pcix_write_buf_64[8];
} pic_int_desc_upper_u_t;
/* /* End of Local Registers -- Start of Address Map space */
* Interrupt Destination Lower Address Register
* char _pad_000c00[0x010000 - 0x000c00];
* The interrupt destination lower address register is a read/write register
* which contains the entire address of the host to which the interrupt is tar- /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
* geted. In addition the target ID is also contained in this register for use in picate_t p_int_ate_ram[1024]; /* 0x010000-0x011fff */
* Crosstalk mode.
*/ /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
typedef union pic_int_desc_lower_u { picate_t p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */
picreg_t pic_int_desc_lower_regval;
struct { char _pad_014000[0x18000 - 0x014000];
picreg_t : 12; /* 63:52 */
picreg_t target_id : 4; /* 51:48 */ /* 0x18000-0x197F8 -- PIC Write Request Ram */
picreg_t upp_addr : 16; /* 47:32 */ picreg_t p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
picreg_t low_addr : 32; /* 31:0 */ picreg_t p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
} pic_int_desc_lower_fld_s; picreg_t p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
} pic_int_desc_lower_u_t;
/* char _pad_019800[0x20000 - 0x019800];
* Command Word Holding Register Bus Side Errors
* /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
* The command word holding is a read register that holds the command union {
* word of a Crosstalk packet when errors occur on the link side (see error uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
* chapter). Errors are indicated with error bits in the interrupt status regis- uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
* ter. Subsequent errors are not logged until the interrupt is cleared.. uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
*/ uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
typedef union pic_cmd_word_bus_err_u { union {
picreg_t pic_cmd_word_bus_err_regval; uint8_t c[0x100 / 1];
struct { uint16_t s[0x100 / 2];
picreg_t : 32; /* 63:32 */ uint32_t l[0x100 / 4];
picreg_t didn : 4; /* 31:28 */ uint64_t d[0x100 / 8];
picreg_t sidn : 4; /* 27:24 */ } f[8];
picreg_t pactyp : 4; /* 23:20 */ } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */
picreg_t tnum : 5; /* 19:15 */
picreg_t coherent : 1; /* 14:14 */ /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
picreg_t ds : 2; /* 13:12 */ union {
picreg_t gbr : 1; /* 11:11 */ uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */
picreg_t vbpm : 1; /* 10:10 */ uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */
picreg_t error : 1; /* 9:9 */ uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */
picreg_t barrier : 1; /* 8:8 */ uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */
picreg_t : 8; /* 7:0 */ union {
} pic_cmd_word_bus_err_fld_s; uint8_t c[0x100 / 1];
} pic_cmd_word_bus_err_u_t; uint16_t s[0x100 / 2];
/* uint32_t l[0x100 / 4];
* LLP Configuration Register uint64_t d[0x100 / 8];
* } f[8];
* This register contains the configuration information for the LLP modules } p_type1_cfg; /* 0x028000-0x029000 */
* and is only valid on bus 0 side.
*/ char _pad_029000[0x030000-0x029000];
typedef union pic_llp_cfg_u {
picreg_t pic_llp_cfg_regval; /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
struct { union {
picreg_t : 32; /* 63:32 */ uint8_t c[8 / 1];
picreg_t : 6; /* 31:26 */ uint16_t s[8 / 2];
picreg_t llp_maxretry : 10; /* 25:16 */ uint32_t l[8 / 4];
picreg_t llp_nulltimeout : 6; /* 15:10 */ uint64_t d[8 / 8];
picreg_t llp_maxburst : 10; /* 9:0 */ } p_pci_iack; /* 0x030000-0x030007 */
} pic_llp_cfg_fld_s;
} pic_llp_cfg_u_t; char _pad_030007[0x040000-0x030008];
/*
* PCI/PCI-X Target Flush Register /* 0x040000-0x030007 -- PCIX Special Cycle */
* union {
* When read, this register will return a 0x00 after all previous transfers to uint8_t c[8 / 1];
* the PCI bus subsection have completed. uint16_t s[8 / 2];
*/ uint32_t l[8 / 4];
uint64_t d[8 / 8];
/* } p_pcix_cycle; /* 0x040000-0x040007 */
* Command Word Holding Register Link Side Errors } pic_t;
*
* The command word holding is a read-only register that holds the com-
* mand word of a Crosstalk packet when request fifo overflow or unexpect-
* ed response errors occur. Errors are indicated with error bits in the
* interrupt status register. Subsequent errors are not logged until this inter-
* rupt is cleared.
*/
typedef union pic_cmd_word_link_err_u {
picreg_t pic_cmd_word_link_err_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t didn : 4; /* 31:28 */
picreg_t sidn : 4; /* 27:24 */
picreg_t pactyp : 4; /* 23:20 */
picreg_t tnum : 5; /* 19:15 */
picreg_t coherent : 1; /* 14:14 */
picreg_t ds : 2; /* 13:12 */
picreg_t gbr : 1; /* 11:11 */
picreg_t vbpm : 1; /* 10:10 */
picreg_t error : 1; /* 9:9 */
picreg_t barrier : 1; /* 8:8 */
picreg_t : 8; /* 7:0 */
} pic_cmd_word_link_err_fld_s;
} pic_cmd_word_link_err_u_t;
/*
* PCI Response Buffer Error Upper Address Holding Reg
*
* The response buffer error upper address holding register is a read only
* register which contains the upper 16-bits of the address when error asso-
* ciated with response buffer entries occur. Subsequent errors are not
* logged until the interrupt is cleared.
*/
typedef union pic_pci_rbuf_err_upper_u {
picreg_t pic_pci_rbuf_err_upper_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 9; /* 31:23 */
picreg_t dev_num : 3; /* 22:20 */
picreg_t buff_num : 4; /* 19:16 */
picreg_t upp_addr : 16; /* 15:0 */
} pic_pci_rbuf_err_upper_fld_s;
} pic_pci_rbuf_err_upper_u_t;
/*
* PCI Response Buffer Error Lower Address Holding Reg
*
* The response buffer error lower address holding register is a read only
* register which contains the address of the error associated with response
* buffer entries. Subsequent errors are not logged until the interrupt is
* cleared.
*/
typedef union pic_pci_rbuf_err_lower_u {
picreg_t pic_pci_rbuf_err_lower_regval;
struct {
picreg_t : 9; /* 63:55 */
picreg_t dev_num : 3; /* 54:52 */
picreg_t buff_num : 4; /* 51:48 */
picreg_t upp_addr : 16; /* 47:32 */
picreg_t low_addr : 32; /* 31:0 */
} pic_pci_rbuf_err_lower_fld_s;
} pic_pci_rbuf_err_lower_u_t;
/*
* Test Pin Control Register
*
* This register selects the output function and value to the four test pins on
* the PIC .
*/
typedef union pic_test_pin_cntl_u {
picreg_t pic_test_pin_cntl_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 8; /* 31:24 */
picreg_t tdata_out : 8; /* 23:16 */
picreg_t sel_tpin_7 : 2; /* 15:14 */
picreg_t sel_tpin_6 : 2; /* 13:12 */
picreg_t sel_tpin_5 : 2; /* 11:10 */
picreg_t sel_tpin_4 : 2; /* 9:8 */
picreg_t sel_tpin_3 : 2; /* 7:6 */
picreg_t sel_tpin_2 : 2; /* 5:4 */
picreg_t sel_tpin_1 : 2; /* 3:2 */
picreg_t sel_tpin_0 : 2; /* 1:0 */
} pic_test_pin_cntl_fld_s;
} pic_test_pin_cntl_u_t;
/*
* Address Holding Register Link Side Errors
*
* The address holding register is a read only register which contains the ad-
* dress which either can be accessed as a word or double word. Subsequent
* errors are not logged until the error is cleared. The last logged value is
* held until the group is cleared and enabled.
*/
typedef union pic_p_addr_lkerr_u {
picreg_t pic_p_addr_lkerr_regval;
struct {
picreg_t : 16; /* 63:48 */
picreg_t upp_addr : 16; /* 47:32 */
picreg_t low_addr : 32; /* 31:0 */
} pic_p_addr_lkerr_fld_s;
} pic_p_addr_lkerr_u_t;
/*
* PCI Direct Mapping Register
*
* This register is used to relocate a 2 GByte region for PCI to Crosstalk
* transfers.
*/
typedef union pic_p_dir_map_u {
picreg_t pic_p_dir_map_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 8; /* 31:24 */
picreg_t dir_w_id : 4; /* 23:20 */
picreg_t : 2; /* 19:18 */
picreg_t dir_add512 : 1; /* 17:17 */
picreg_t dir_off : 17; /* 16:0 */
} pic_p_dir_map_fld_s;
} pic_p_dir_map_u_t;
/*
* PCI Page Map Fault Address Register
*
* This register contains the address and device number when a page map
* fault occurred.
*/
typedef union pic_p_map_fault_u {
picreg_t pic_p_map_fault_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 10; /* 31:22 */
picreg_t pci_addr : 18; /* 21:4 */
picreg_t : 1; /* 3:3 */
picreg_t pci_dev_num : 3; /* 2:0 */
} pic_p_map_fault_fld_s;
} pic_p_map_fault_u_t;
/*
* Arbitration Register
*
* This register defines the priority and bus time out timing in PCI bus arbi-
* tration.
*/
typedef union pic_p_arb_u {
picreg_t pic_p_arb_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 8; /* 31:24 */
picreg_t dev_broke : 4; /* 23:20 */
picreg_t : 2; /* 19:18 */
picreg_t req_wait_tick : 2; /* 17:16 */
picreg_t : 4; /* 15:12 */
picreg_t req_wait_en : 4; /* 11:8 */
picreg_t disarb : 1; /* 7:7 */
picreg_t freeze_gnt : 1; /* 6:6 */
picreg_t : 1; /* 5:5 */
picreg_t en_bridge_hi : 2; /* 4:3 */
picreg_t : 1; /* 2:2 */
picreg_t en_bridge_lo : 2; /* 1:0 */
} pic_p_arb_fld_s;
} pic_p_arb_u_t;
/*
* Internal Ram Parity Error Register
*
* This register logs information about parity errors on internal ram access.
*/
typedef union pic_p_ram_perr_u {
picreg_t pic_p_ram_perr_regval;
struct {
picreg_t : 6; /* 63:58 */
picreg_t ate_err_addr : 10; /* 57:48 */
picreg_t : 7; /* 47:41 */
picreg_t rd_resp_err_addr : 9; /* 40:32 */
picreg_t wrt_resp_err_addr : 8; /* 31:24 */
picreg_t : 2; /* 23:22 */
picreg_t ate_err : 1; /* 21:21 */
picreg_t rd_resp_err : 1; /* 20:20 */
picreg_t wrt_resp_err : 1; /* 19:19 */
picreg_t dbe_ate : 3; /* 18:16 */
picreg_t dbe_rd : 8; /* 15:8 */
picreg_t dbe_wrt : 8; /* 7:0 */
} pic_p_ram_perr_fld_s;
} pic_p_ram_perr_u_t;
/*
* Time-out Register
*
* This register determines retry hold off and max retries allowed for PIO
* accesses to PCI/PCI-X.
*/
typedef union pic_p_bus_timeout_u {
picreg_t pic_p_bus_timeout_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 11; /* 31:21 */
picreg_t pci_retry_hld : 5; /* 20:16 */
picreg_t : 6; /* 15:10 */
picreg_t pci_retry_cnt : 10; /* 9:0 */
} pic_p_bus_timeout_fld_s;
} pic_p_bus_timeout_u_t;
/*
* PCI/PCI-X Type 1 Configuration Register
*
* This register is use during accesses to the PCI/PCI-X type 1 configuration
* space. The bits in this register are used to supplement the address during
* the configuration cycle to select the correct secondary bus and device.
*/
typedef union pic_type1_cfg_u {
picreg_t pic_type1_cfg_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 8; /* 31:24 */
picreg_t bus_num : 8; /* 23:16 */
picreg_t dev_num : 5; /* 15:11 */
picreg_t : 11; /* 10:0 */
} pic_type1_cfg_fld_s;
} pic_type1_cfg_u_t;
/*
* PCI Bus Error Upper Address Holding Register
*
* This register holds the value of the upper address on the PCI Bus when an
* error occurs.
*/
typedef union pic_p_pci_err_upper_u {
picreg_t pic_p_pci_err_upper_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 4; /* 31:28 */
picreg_t pci_xtalk_did : 4; /* 27:24 */
picreg_t : 2; /* 23:22 */
picreg_t pci_dac : 1; /* 21:21 */
picreg_t pci_dev_master : 1; /* 20:20 */
picreg_t pci_vdev : 1; /* 19:19 */
picreg_t pci_dev_num : 3; /* 18:16 */
picreg_t pci_uaddr_err : 16; /* 15:0 */
} pic_p_pci_err_upper_fld_s;
} pic_p_pci_err_upper_u_t;
/*
* PCI Bus Error Lower Address Holding Register
*
* This register holds the value of the lower address on the PCI Bus when an
* error occurs.
*/
typedef union pic_p_pci_err_lower_u {
picreg_t pic_p_pci_err_lower_regval;
struct {
picreg_t : 4; /* 63:60 */
picreg_t pci_xtalk_did : 4; /* 59:56 */
picreg_t : 2; /* 55:54 */
picreg_t pci_dac : 1; /* 53:53 */
picreg_t pci_dev_master : 1; /* 52:52 */
picreg_t pci_vdev : 1; /* 51:51 */
picreg_t pci_dev_num : 3; /* 50:48 */
picreg_t pci_uaddr_err : 16; /* 47:32 */
picreg_t pci_laddr_err : 32; /* 31:0 */
} pic_p_pci_err_lower_fld_s;
} pic_p_pci_err_lower_u_t;
/*
* PCI-X Error Address Register
*
* This register contains the address on the PCI-X bus when an error oc-
* curred.
*/
typedef union pic_p_pcix_err_addr_u {
picreg_t pic_p_pcix_err_addr_regval;
struct {
picreg_t pcix_err_addr : 64; /* 63:0 */
} pic_p_pcix_err_addr_fld_s;
} pic_p_pcix_err_addr_u_t;
/*
* PCI-X Error Attribute Register
*
* This register contains the attribute data on the PCI-X bus when an error
* occurred.
*/
typedef union pic_p_pcix_err_attr_u {
picreg_t pic_p_pcix_err_attr_regval;
struct {
picreg_t : 16; /* 63:48 */
picreg_t bus_cmd : 4; /* 47:44 */
picreg_t byte_cnt : 12; /* 43:32 */
picreg_t : 1; /* 31:31 */
picreg_t ns : 1; /* 30:30 */
picreg_t ro : 1; /* 29:29 */
picreg_t tag : 5; /* 28:24 */
picreg_t bus_num : 8; /* 23:16 */
picreg_t dev_num : 5; /* 15:11 */
picreg_t fun_num : 3; /* 10:8 */
picreg_t l_byte_cnt : 8; /* 7:0 */
} pic_p_pcix_err_attr_fld_s;
} pic_p_pcix_err_attr_u_t;
/*
* PCI-X Error Data Register
*
* This register contains the Data on the PCI-X bus when an error occurred.
*/
typedef union pic_p_pcix_err_data_u {
picreg_t pic_p_pcix_err_data_regval;
struct {
picreg_t pcix_err_data : 64; /* 63:0 */
} pic_p_pcix_err_data_fld_s;
} pic_p_pcix_err_data_u_t;
/*
* PCI-X Read Request Timeout Error Register
*
* This register contains a pointer into the PCI-X read data structure.
*/
typedef union pic_p_pcix_read_req_to_u {
picreg_t pic_p_pcix_read_req_to_regval;
struct {
picreg_t : 55; /* 63:9 */
picreg_t rd_buff_loc : 5; /* 8:4 */
picreg_t rd_buff_struct : 4; /* 3:0 */
} pic_p_pcix_read_req_to_fld_s;
} pic_p_pcix_read_req_to_u_t;
/*
* INT_STATUS Register
*
* This is the current interrupt status register which maintains the current
* status of all the interrupting devices which generated a n interrupt. This
* register is read only and all the bits are active high. A high bit at
* INT_STATE means the corresponding INT_N pin has been asserted
* (low).
*/
typedef union pic_p_int_status_u {
picreg_t pic_p_int_status_regval;
struct {
picreg_t : 22; /* 63:42 */
picreg_t int_ram_perr : 1; /* 41:41 */
picreg_t bus_arb_broke : 1; /* 40:40 */
picreg_t pci_x_req_tout : 1; /* 39:39 */
picreg_t pci_x_tabort : 1; /* 38:38 */
picreg_t pci_x_perr : 1; /* 37:37 */
picreg_t pci_x_serr : 1; /* 36:36 */
picreg_t pci_x_mretry : 1; /* 35:35 */
picreg_t pci_x_mtout : 1; /* 34:34 */
picreg_t pci_x_da_parity : 1; /* 33:33 */
picreg_t pci_x_ad_parity : 1; /* 32:32 */
picreg_t : 1; /* 31:31 */
picreg_t pmu_page_fault : 1; /* 30:30 */
picreg_t unexpected_resp : 1; /* 29:29 */
picreg_t bad_xresp_packet : 1; /* 28:28 */
picreg_t bad_xreq_packet : 1; /* 27:27 */
picreg_t resp_xtalk_error : 1; /* 26:26 */
picreg_t req_xtalk_error : 1; /* 25:25 */
picreg_t invalid_access : 1; /* 24:24 */
picreg_t unsupported_xop : 1; /* 23:23 */
picreg_t xreq_fifo_oflow : 1; /* 22:22 */
picreg_t llp_rec_snerror : 1; /* 21:21 */
picreg_t llp_rec_cberror : 1; /* 20:20 */
picreg_t llp_rcty : 1; /* 19:19 */
picreg_t llp_tx_retry : 1; /* 18:18 */
picreg_t llp_tcty : 1; /* 17:17 */
picreg_t : 1; /* 16:16 */
picreg_t pci_abort : 1; /* 15:15 */
picreg_t pci_parity : 1; /* 14:14 */
picreg_t pci_serr : 1; /* 13:13 */
picreg_t pci_perr : 1; /* 12:12 */
picreg_t pci_master_tout : 1; /* 11:11 */
picreg_t pci_retry_cnt : 1; /* 10:10 */
picreg_t xread_req_tout : 1; /* 9:9 */
picreg_t : 1; /* 8:8 */
picreg_t int_state : 8; /* 7:0 */
} pic_p_int_status_fld_s;
} pic_p_int_status_u_t;
/*
* Interrupt Enable Register
*
* This register enables the reporting of interrupt to the host. Each bit in this
* register corresponds to the same bit in Interrupt Status register. All bits
* are zero after reset.
*/
typedef union pic_p_int_enable_u {
picreg_t pic_p_int_enable_regval;
struct {
picreg_t : 22; /* 63:42 */
picreg_t en_int_ram_perr : 1; /* 41:41 */
picreg_t en_bus_arb_broke : 1; /* 40:40 */
picreg_t en_pci_x_req_tout : 1; /* 39:39 */
picreg_t en_pci_x_tabort : 1; /* 38:38 */
picreg_t en_pci_x_perr : 1; /* 37:37 */
picreg_t en_pci_x_serr : 1; /* 36:36 */
picreg_t en_pci_x_mretry : 1; /* 35:35 */
picreg_t en_pci_x_mtout : 1; /* 34:34 */
picreg_t en_pci_x_da_parity : 1; /* 33:33 */
picreg_t en_pci_x_ad_parity : 1; /* 32:32 */
picreg_t : 1; /* 31:31 */
picreg_t en_pmu_page_fault : 1; /* 30:30 */
picreg_t en_unexpected_resp : 1; /* 29:29 */
picreg_t en_bad_xresp_packet : 1; /* 28:28 */
picreg_t en_bad_xreq_packet : 1; /* 27:27 */
picreg_t en_resp_xtalk_error : 1; /* 26:26 */
picreg_t en_req_xtalk_error : 1; /* 25:25 */
picreg_t en_invalid_access : 1; /* 24:24 */
picreg_t en_unsupported_xop : 1; /* 23:23 */
picreg_t en_xreq_fifo_oflow : 1; /* 22:22 */
picreg_t en_llp_rec_snerror : 1; /* 21:21 */
picreg_t en_llp_rec_cberror : 1; /* 20:20 */
picreg_t en_llp_rcty : 1; /* 19:19 */
picreg_t en_llp_tx_retry : 1; /* 18:18 */
picreg_t en_llp_tcty : 1; /* 17:17 */
picreg_t : 1; /* 16:16 */
picreg_t en_pci_abort : 1; /* 15:15 */
picreg_t en_pci_parity : 1; /* 14:14 */
picreg_t en_pci_serr : 1; /* 13:13 */
picreg_t en_pci_perr : 1; /* 12:12 */
picreg_t en_pci_master_tout : 1; /* 11:11 */
picreg_t en_pci_retry_cnt : 1; /* 10:10 */
picreg_t en_xread_req_tout : 1; /* 9:9 */
picreg_t : 1; /* 8:8 */
picreg_t en_int_state : 8; /* 7:0 */
} pic_p_int_enable_fld_s;
} pic_p_int_enable_u_t;
/*
* Reset Interrupt Register
*
* A write of a "1" clears the bit and rearms the error registers. Writes also
* clear the error view register.
*/
typedef union pic_p_int_rst_u {
picreg_t pic_p_int_rst_regval;
struct {
picreg_t : 22; /* 63:42 */
picreg_t logv_int_ram_perr : 1; /* 41:41 */
picreg_t logv_bus_arb_broke : 1; /* 40:40 */
picreg_t logv_pci_x_req_tout : 1; /* 39:39 */
picreg_t logv_pci_x_tabort : 1; /* 38:38 */
picreg_t logv_pci_x_perr : 1; /* 37:37 */
picreg_t logv_pci_x_serr : 1; /* 36:36 */
picreg_t logv_pci_x_mretry : 1; /* 35:35 */
picreg_t logv_pci_x_mtout : 1; /* 34:34 */
picreg_t logv_pci_x_da_parity : 1; /* 33:33 */
picreg_t logv_pci_x_ad_parity : 1; /* 32:32 */
picreg_t : 1; /* 31:31 */
picreg_t logv_pmu_page_fault : 1; /* 30:30 */
picreg_t logv_unexpected_resp : 1; /* 29:29 */
picreg_t logv_bad_xresp_packet : 1; /* 28:28 */
picreg_t logv_bad_xreq_packet : 1; /* 27:27 */
picreg_t logv_resp_xtalk_error : 1; /* 26:26 */
picreg_t logv_req_xtalk_error : 1; /* 25:25 */
picreg_t logv_invalid_access : 1; /* 24:24 */
picreg_t logv_unsupported_xop : 1; /* 23:23 */
picreg_t logv_xreq_fifo_oflow : 1; /* 22:22 */
picreg_t logv_llp_rec_snerror : 1; /* 21:21 */
picreg_t logv_llp_rec_cberror : 1; /* 20:20 */
picreg_t logv_llp_rcty : 1; /* 19:19 */
picreg_t logv_llp_tx_retry : 1; /* 18:18 */
picreg_t logv_llp_tcty : 1; /* 17:17 */
picreg_t : 1; /* 16:16 */
picreg_t logv_pci_abort : 1; /* 15:15 */
picreg_t logv_pci_parity : 1; /* 14:14 */
picreg_t logv_pci_serr : 1; /* 13:13 */
picreg_t logv_pci_perr : 1; /* 12:12 */
picreg_t logv_pci_master_tout : 1; /* 11:11 */
picreg_t logv_pci_retry_cnt : 1; /* 10:10 */
picreg_t logv_xread_req_tout : 1; /* 9:9 */
picreg_t : 2; /* 8:7 */
picreg_t multi_clr : 1; /* 6:6 */
picreg_t : 6; /* 5:0 */
} pic_p_int_rst_fld_s;
} pic_p_int_rst_u_t;
/*
* Interrupt Mode Register
*
* This register defines the interrupting mode of the INT_N pins.
*/
typedef union pic_p_int_mode_u {
picreg_t pic_p_int_mode_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 24; /* 31:8 */
picreg_t en_clr_pkt : 8; /* 7:0 */
} pic_p_int_mode_fld_s;
} pic_p_int_mode_u_t;
/*
* Interrupt Device Select Register
*
* This register associates interrupt pins with devices thus allowing buffer
* management (flushing) when a device interrupt occurs.
*/
typedef union pic_p_int_device_u {
picreg_t pic_p_int_device_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 8; /* 31:24 */
picreg_t int7_dev : 3; /* 23:21 */
picreg_t int6_dev : 3; /* 20:18 */
picreg_t int5_dev : 3; /* 17:15 */
picreg_t int4_dev : 3; /* 14:12 */
picreg_t int3_dev : 3; /* 11:9 */
picreg_t int2_dev : 3; /* 8:6 */
picreg_t int1_dev : 3; /* 5:3 */
picreg_t int0_dev : 3; /* 2:0 */
} pic_p_int_device_fld_s;
} pic_p_int_device_u_t;
/*
* Host Error Interrupt Field Register
*
* This register tells which bit location in the host's Interrupt Status register
* to set or reset when any error condition happens.
*/
typedef union pic_p_int_host_err_u {
picreg_t pic_p_int_host_err_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 24; /* 31:8 */
picreg_t bridge_err_fld : 8; /* 7:0 */
} pic_p_int_host_err_fld_s;
} pic_p_int_host_err_u_t;
/*
* Interrupt (x) Host Address Register
*
* This register allow different host address to be assigned to each interrupt
* pin and the bit in the host.
*/
typedef union pic_p_int_addr_u {
picreg_t pic_p_int_addr_regval;
struct {
picreg_t : 8; /* 63:56 */
picreg_t int_fld : 8; /* 55:48 */
picreg_t int_addr : 48; /* 47:0 */
} pic_p_int_addr_fld_s;
} pic_p_int_addr_u_t;
/*
* Error Interrupt View Register
*
* This register contains the view of which interrupt occur even if they are
* not currently enabled. The group clear is used to clear these bits just like
* the interrupt status register bits.
*/
typedef union pic_p_err_int_view_u {
picreg_t pic_p_err_int_view_regval;
struct {
picreg_t : 22; /* 63:42 */
picreg_t int_ram_perr : 1; /* 41:41 */
picreg_t bus_arb_broke : 1; /* 40:40 */
picreg_t pci_x_req_tout : 1; /* 39:39 */
picreg_t pci_x_tabort : 1; /* 38:38 */
picreg_t pci_x_perr : 1; /* 37:37 */
picreg_t pci_x_serr : 1; /* 36:36 */
picreg_t pci_x_mretry : 1; /* 35:35 */
picreg_t pci_x_mtout : 1; /* 34:34 */
picreg_t pci_x_da_parity : 1; /* 33:33 */
picreg_t pci_x_ad_parity : 1; /* 32:32 */
picreg_t : 1; /* 31:31 */
picreg_t pmu_page_fault : 1; /* 30:30 */
picreg_t unexpected_resp : 1; /* 29:29 */
picreg_t bad_xresp_packet : 1; /* 28:28 */
picreg_t bad_xreq_packet : 1; /* 27:27 */
picreg_t resp_xtalk_error : 1; /* 26:26 */
picreg_t req_xtalk_error : 1; /* 25:25 */
picreg_t invalid_access : 1; /* 24:24 */
picreg_t unsupported_xop : 1; /* 23:23 */
picreg_t xreq_fifo_oflow : 1; /* 22:22 */
picreg_t llp_rec_snerror : 1; /* 21:21 */
picreg_t llp_rec_cberror : 1; /* 20:20 */
picreg_t llp_rcty : 1; /* 19:19 */
picreg_t llp_tx_retry : 1; /* 18:18 */
picreg_t llp_tcty : 1; /* 17:17 */
picreg_t : 1; /* 16:16 */
picreg_t pci_abort : 1; /* 15:15 */
picreg_t pci_parity : 1; /* 14:14 */
picreg_t pci_serr : 1; /* 13:13 */
picreg_t pci_perr : 1; /* 12:12 */
picreg_t pci_master_tout : 1; /* 11:11 */
picreg_t pci_retry_cnt : 1; /* 10:10 */
picreg_t xread_req_tout : 1; /* 9:9 */
picreg_t : 9; /* 8:0 */
} pic_p_err_int_view_fld_s;
} pic_p_err_int_view_u_t;
/*
* Multiple Interrupt Register
*
* This register indicates if any interrupt occurs more than once without be-
* ing cleared.
*/
typedef union pic_p_mult_int_u {
picreg_t pic_p_mult_int_regval;
struct {
picreg_t : 22; /* 63:42 */
picreg_t int_ram_perr : 1; /* 41:41 */
picreg_t bus_arb_broke : 1; /* 40:40 */
picreg_t pci_x_req_tout : 1; /* 39:39 */
picreg_t pci_x_tabort : 1; /* 38:38 */
picreg_t pci_x_perr : 1; /* 37:37 */
picreg_t pci_x_serr : 1; /* 36:36 */
picreg_t pci_x_mretry : 1; /* 35:35 */
picreg_t pci_x_mtout : 1; /* 34:34 */
picreg_t pci_x_da_parity : 1; /* 33:33 */
picreg_t pci_x_ad_parity : 1; /* 32:32 */
picreg_t : 1; /* 31:31 */
picreg_t pmu_page_fault : 1; /* 30:30 */
picreg_t unexpected_resp : 1; /* 29:29 */
picreg_t bad_xresp_packet : 1; /* 28:28 */
picreg_t bad_xreq_packet : 1; /* 27:27 */
picreg_t resp_xtalk_error : 1; /* 26:26 */
picreg_t req_xtalk_error : 1; /* 25:25 */
picreg_t invalid_access : 1; /* 24:24 */
picreg_t unsupported_xop : 1; /* 23:23 */
picreg_t xreq_fifo_oflow : 1; /* 22:22 */
picreg_t llp_rec_snerror : 1; /* 21:21 */
picreg_t llp_rec_cberror : 1; /* 20:20 */
picreg_t llp_rcty : 1; /* 19:19 */
picreg_t llp_tx_retry : 1; /* 18:18 */
picreg_t llp_tcty : 1; /* 17:17 */
picreg_t : 1; /* 16:16 */
picreg_t pci_abort : 1; /* 15:15 */
picreg_t pci_parity : 1; /* 14:14 */
picreg_t pci_serr : 1; /* 13:13 */
picreg_t pci_perr : 1; /* 12:12 */
picreg_t pci_master_tout : 1; /* 11:11 */
picreg_t pci_retry_cnt : 1; /* 10:10 */
picreg_t xread_req_tout : 1; /* 9:9 */
picreg_t : 1; /* 8:8 */
picreg_t int_state : 8; /* 7:0 */
} pic_p_mult_int_fld_s;
} pic_p_mult_int_u_t;
/*
* Force Always Interrupt (x) Register
*
* A write to this data independent write only register will force a set inter-
* rupt to occur as if the interrupt line had transitioned. If the interrupt line
* is already active an addition set interrupt packet is set. All buffer flush op-
* erations also occur on this operation.
*/
/*
* Force Interrupt (x) Register
*
* A write to this data independent write only register in conjunction with
* the assertion of the corresponding interrupt line will force a set interrupt
* to occur as if the interrupt line had transitioned. The interrupt line must
* be active for this operation to generate a set packet, otherwise the write
* PIO is ignored. All buffer flush operations also occur when the set packet
* is sent on this operation.
*/
/*
* Device Registers
*
* The Device registers contain device specific and mapping information.
*/
typedef union pic_device_reg_u {
picreg_t pic_device_reg_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 2; /* 31:30 */
picreg_t en_virtual1 : 1; /* 29:29 */
picreg_t en_error_lock : 1; /* 28:28 */
picreg_t en_page_chk : 1; /* 27:27 */
picreg_t force_pci_par : 1; /* 26:26 */
picreg_t en_virtual0 : 1; /* 25:25 */
picreg_t : 1; /* 24:24 */
picreg_t dir_wrt_gen : 1; /* 23:23 */
picreg_t dev_size : 1; /* 22:22 */
picreg_t real_time : 1; /* 21:21 */
picreg_t : 1; /* 20:20 */
picreg_t swap_direct : 1; /* 19:19 */
picreg_t prefetch : 1; /* 18:18 */
picreg_t precise : 1; /* 17:17 */
picreg_t coherent : 1; /* 16:16 */
picreg_t barrier : 1; /* 15:15 */
picreg_t gbr : 1; /* 14:14 */
picreg_t dev_swap : 1; /* 13:13 */
picreg_t dev_io_mem : 1; /* 12:12 */
picreg_t dev_off : 12; /* 11:0 */
} pic_device_reg_fld_s;
} pic_device_reg_u_t;
/*
* Device (x) Write Request Buffer Flush
*
* When read, this register will return a 0x00 after the write buffer associat-
* ed with the device has been flushed. (PCI Only)
*/
/*
* Even Device Read Response Buffer Register (PCI Only)
*
* This register is use to allocate the read response buffers for the even num-
* bered devices. (0,2)
*/
typedef union pic_p_even_resp_u {
picreg_t pic_p_even_resp_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t buff_14_en : 1; /* 31:31 */
picreg_t buff_14_vdev : 2; /* 30:29 */
picreg_t buff_14_pdev : 1; /* 28:28 */
picreg_t buff_12_en : 1; /* 27:27 */
picreg_t buff_12_vdev : 2; /* 26:25 */
picreg_t buff_12_pdev : 1; /* 24:24 */
picreg_t buff_10_en : 1; /* 23:23 */
picreg_t buff_10_vdev : 2; /* 22:21 */
picreg_t buff_10_pdev : 1; /* 20:20 */
picreg_t buff_8_en : 1; /* 19:19 */
picreg_t buff_8_vdev : 2; /* 18:17 */
picreg_t buff_8_pdev : 1; /* 16:16 */
picreg_t buff_6_en : 1; /* 15:15 */
picreg_t buff_6_vdev : 2; /* 14:13 */
picreg_t buff_6_pdev : 1; /* 12:12 */
picreg_t buff_4_en : 1; /* 11:11 */
picreg_t buff_4_vdev : 2; /* 10:9 */
picreg_t buff_4_pdev : 1; /* 8:8 */
picreg_t buff_2_en : 1; /* 7:7 */
picreg_t buff_2_vdev : 2; /* 6:5 */
picreg_t buff_2_pdev : 1; /* 4:4 */
picreg_t buff_0_en : 1; /* 3:3 */
picreg_t buff_0_vdev : 2; /* 2:1 */
picreg_t buff_0_pdev : 1; /* 0:0 */
} pic_p_even_resp_fld_s;
} pic_p_even_resp_u_t;
/*
* Odd Device Read Response Buffer Register (PCI Only)
*
* This register is use to allocate the read response buffers for the odd num-
* bered devices. (1,3))
*/
typedef union pic_p_odd_resp_u {
picreg_t pic_p_odd_resp_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t buff_15_en : 1; /* 31:31 */
picreg_t buff_15_vdev : 2; /* 30:29 */
picreg_t buff_15_pdev : 1; /* 28:28 */
picreg_t buff_13_en : 1; /* 27:27 */
picreg_t buff_13_vdev : 2; /* 26:25 */
picreg_t buff_13_pdev : 1; /* 24:24 */
picreg_t buff_11_en : 1; /* 23:23 */
picreg_t buff_11_vdev : 2; /* 22:21 */
picreg_t buff_11_pdev : 1; /* 20:20 */
picreg_t buff_9_en : 1; /* 19:19 */
picreg_t buff_9_vdev : 2; /* 18:17 */
picreg_t buff_9_pdev : 1; /* 16:16 */
picreg_t buff_7_en : 1; /* 15:15 */
picreg_t buff_7_vdev : 2; /* 14:13 */
picreg_t buff_7_pdev : 1; /* 12:12 */
picreg_t buff_5_en : 1; /* 11:11 */
picreg_t buff_5_vdev : 2; /* 10:9 */
picreg_t buff_5_pdev : 1; /* 8:8 */
picreg_t buff_3_en : 1; /* 7:7 */
picreg_t buff_3_vdev : 2; /* 6:5 */
picreg_t buff_3_pdev : 1; /* 4:4 */
picreg_t buff_1_en : 1; /* 3:3 */
picreg_t buff_1_vdev : 2; /* 2:1 */
picreg_t buff_1_pdev : 1; /* 0:0 */
} pic_p_odd_resp_fld_s;
} pic_p_odd_resp_u_t;
/*
* Read Response Buffer Status Register (PCI Only)
*
* This read only register contains the current response buffer status.
*/
typedef union pic_p_resp_status_u {
picreg_t pic_p_resp_status_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t rrb_valid : 16; /* 31:16 */
picreg_t rrb_inuse : 16; /* 15:0 */
} pic_p_resp_status_fld_s;
} pic_p_resp_status_u_t;
/*
* Read Response Buffer Clear Register (PCI Only)
*
* A write to this register clears the current contents of the buffer.
*/
typedef union pic_p_resp_clear_u {
picreg_t pic_p_resp_clear_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 16; /* 31:16 */
picreg_t rrb_clear : 16; /* 15:0 */
} pic_p_resp_clear_fld_s;
} pic_p_resp_clear_u_t;
/*
* PCI Read Response Buffer (x) Upper Address Match
*
* The PCI Bridge read response buffer upper address register is a read only
* register which contains the upper 16-bits of the address and status used to
* select the buffer for a PCI transaction.
*/
typedef union pic_p_buf_upper_addr_match_u {
picreg_t pic_p_buf_upper_addr_match_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t filled : 1; /* 31:31 */
picreg_t armed : 1; /* 30:30 */
picreg_t flush : 1; /* 29:29 */
picreg_t xerr : 1; /* 28:28 */
picreg_t pkterr : 1; /* 27:27 */
picreg_t timeout : 1; /* 26:26 */
picreg_t prefetch : 1; /* 25:25 */
picreg_t precise : 1; /* 24:24 */
picreg_t dw_be : 8; /* 23:16 */
picreg_t upp_addr : 16; /* 15:0 */
} pic_p_buf_upper_addr_match_fld_s;
} pic_p_buf_upper_addr_match_u_t;
/*
* PCI Read Response Buffer (x) Lower Address Match
*
* The PCI Bridge read response buffer lower address Match register is a
* read only register which contains the address and status used to select the
* buffer for a PCI transaction.
*/
typedef union pic_p_buf_lower_addr_match_u {
picreg_t pic_p_buf_lower_addr_match_regval;
struct {
picreg_t filled : 1; /* 63:63 */
picreg_t armed : 1; /* 62:62 */
picreg_t flush : 1; /* 61:61 */
picreg_t xerr : 1; /* 60:60 */
picreg_t pkterr : 1; /* 59:59 */
picreg_t timeout : 1; /* 58:58 */
picreg_t prefetch : 1; /* 57:57 */
picreg_t precise : 1; /* 56:56 */
picreg_t dw_be : 8; /* 55:48 */
picreg_t upp_addr : 16; /* 47:32 */
picreg_t low_addr : 32; /* 31:0 */
} pic_p_buf_lower_addr_match_fld_s;
} pic_p_buf_lower_addr_match_u_t;
/*
* PCI Buffer (x) Flush Count with Data Touch Register
*
* This counter is incremented each time the corresponding response buffer
* is flushed after at least a single data element in the buffer is used. A word
* write to this address clears the count.
*/
typedef union pic_flush_w_touch_u {
picreg_t pic_flush_w_touch_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 16; /* 31:16 */
picreg_t touch_cnt : 16; /* 15:0 */
} pic_flush_w_touch_fld_s;
} pic_flush_w_touch_u_t;
/*
* PCI Buffer (x) Flush Count w/o Data Touch Register
*
* This counter is incremented each time the corresponding response buffer
* is flushed without any data element in the buffer being used. A word
* write to this address clears the count.
*/
typedef union pic_flush_wo_touch_u {
picreg_t pic_flush_wo_touch_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 16; /* 31:16 */
picreg_t notouch_cnt : 16; /* 15:0 */
} pic_flush_wo_touch_fld_s;
} pic_flush_wo_touch_u_t;
/*
* PCI Buffer (x) Request in Flight Count Register
*
* This counter is incremented on each bus clock while the request is in-
* flight. A word write to this address clears the count. ]
*/
typedef union pic_inflight_u {
picreg_t pic_inflight_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 16; /* 31:16 */
picreg_t inflight_cnt : 16; /* 15:0 */
} pic_inflight_fld_s;
} pic_inflight_u_t;
/*
* PCI Buffer (x) Prefetch Request Count Register
*
* This counter is incremented each time the request using this buffer was
* generated from the prefetcher. A word write to this address clears the
* count.
*/
typedef union pic_prefetch_u {
picreg_t pic_prefetch_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 16; /* 31:16 */
picreg_t prefetch_cnt : 16; /* 15:0 */
} pic_prefetch_fld_s;
} pic_prefetch_u_t;
/*
* PCI Buffer (x) Total PCI Retry Count Register
*
* This counter is incremented each time a PCI bus retry occurs and the ad-
* dress matches the tag for the selected buffer. The buffer must also has this
* request in-flight. A word write to this address clears the count.
*/
typedef union pic_total_pci_retry_u {
picreg_t pic_total_pci_retry_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 16; /* 31:16 */
picreg_t retry_cnt : 16; /* 15:0 */
} pic_total_pci_retry_fld_s;
} pic_total_pci_retry_u_t;
/*
* PCI Buffer (x) Max PCI Retry Count Register
*
* This counter is contains the maximum retry count for a single request
* which was in-flight for this buffer. A word write to this address clears the
* count.
*/
typedef union pic_max_pci_retry_u {
picreg_t pic_max_pci_retry_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 16; /* 31:16 */
picreg_t max_retry_cnt : 16; /* 15:0 */
} pic_max_pci_retry_fld_s;
} pic_max_pci_retry_u_t;
/*
* PCI Buffer (x) Max Latency Count Register
*
* This counter is contains the maximum count (in bus clocks) for a single
* request which was in-flight for this buffer. A word write to this address
* clears the count.
*/
typedef union pic_max_latency_u {
picreg_t pic_max_latency_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t : 16; /* 31:16 */
picreg_t max_latency_cnt : 16; /* 15:0 */
} pic_max_latency_fld_s;
} pic_max_latency_u_t;
/*
* PCI Buffer (x) Clear All Register
*
* Any access to this register clears all the count values for the (x) registers.
*/
/*
* PCI-X Registers
*
* This register contains the address in the read buffer structure. There are
* 16 read buffer structures.
*/
typedef union pic_rd_buf_addr_u {
picreg_t pic_rd_buf_addr_regval;
struct {
picreg_t pcix_err_addr : 64; /* 63:0 */
} pic_rd_buf_addr_fld_s;
} pic_rd_buf_addr_u_t;
/*
* PCI-X Read Buffer (x) Attribute Register
*
* This register contains the attribute data in the read buffer structure. There
* are 16 read buffer structures.
*/
typedef union pic_px_read_buf_attr_u {
picreg_t pic_px_read_buf_attr_regval;
struct {
picreg_t : 16; /* 63:48 */
picreg_t bus_cmd : 4; /* 47:44 */
picreg_t byte_cnt : 12; /* 43:32 */
picreg_t entry_valid : 1; /* 31:31 */
picreg_t ns : 1; /* 30:30 */
picreg_t ro : 1; /* 29:29 */
picreg_t tag : 5; /* 28:24 */
picreg_t bus_num : 8; /* 23:16 */
picreg_t dev_num : 5; /* 15:11 */
picreg_t fun_num : 3; /* 10:8 */
picreg_t : 2; /* 7:6 */
picreg_t f_buffer_index : 6; /* 5:0 */
} pic_px_read_buf_attr_fld_s;
} pic_px_read_buf_attr_u_t;
/*
* PCI-X Write Buffer (x) Address Register
*
* This register contains the address in the write buffer structure. There are
* 8 write buffer structures.
*/
typedef union pic_px_write_buf_addr_u {
picreg_t pic_px_write_buf_addr_regval;
struct {
picreg_t pcix_err_addr : 64; /* 63:0 */
} pic_px_write_buf_addr_fld_s;
} pic_px_write_buf_addr_u_t;
/*
* PCI-X Write Buffer (x) Attribute Register
*
* This register contains the attribute data in the write buffer structure.
* There are 8 write buffer structures.
*/
typedef union pic_px_write_buf_attr_u {
picreg_t pic_px_write_buf_attr_regval;
struct {
picreg_t : 16; /* 63:48 */
picreg_t bus_cmd : 4; /* 47:44 */
picreg_t byte_cnt : 12; /* 43:32 */
picreg_t entry_valid : 1; /* 31:31 */
picreg_t ns : 1; /* 30:30 */
picreg_t ro : 1; /* 29:29 */
picreg_t tag : 5; /* 28:24 */
picreg_t bus_num : 8; /* 23:16 */
picreg_t dev_num : 5; /* 15:11 */
picreg_t fun_num : 3; /* 10:8 */
picreg_t : 2; /* 7:6 */
picreg_t f_buffer_index : 6; /* 5:0 */
} pic_px_write_buf_attr_fld_s;
} pic_px_write_buf_attr_u_t;
/*
* PCI-X Write Buffer (x) Valid Register
*
* This register contains the valid or inuse cache lines for this buffer struc-
* ture.
*/
typedef union pic_px_write_buf_valid_u {
picreg_t pic_px_write_buf_valid_regval;
struct {
picreg_t : 32; /* 63:32 */
picreg_t wrt_valid_buff : 32; /* 31:0 */
} pic_px_write_buf_valid_fld_s;
} pic_px_write_buf_valid_u_t;
#endif /* _ASM_IA64_SN_PCI_PIC_H */ #endif /* _ASM_IA64_SN_PCI_PIC_H */
include/asm-ia64/sn/pda.h
View file @ 2b889c52
...@@ -60,6 +60,7 @@ typedef struct pda_s { ...@@ -60,6 +60,7 @@ typedef struct pda_s {
int sn_lb_int_war_ticks; int sn_lb_int_war_ticks;
int sn_last_irq; int sn_last_irq;
int sn_first_irq; int sn_first_irq;
int sn_num_irqs; /* number of irqs targeted for this cpu */
} pda_t; } pda_t;
......
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