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Commit 2dd8cc90 authored by Mark A. Greer's avatar Mark A. Greer Committed by Linus Torvalds
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[PATCH] mpsc updates 

This patch:
- replaces several macros with the actual code
- change the type of pointer variables from u32 to void *
- removes unecessary casts
- puts the contents of mpsc_defs.h into mpsc.h and removes the mpsc_defs.h
- reflects the new names of some structs
- cleans up some whitespace
Signed-off-by: default avatarMark A. Greer <mgreer@mvista.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 7fe83ffc
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Showing with 425 additions and 413 deletions
drivers/serial/mpsc.c
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drivers/serial/mpsc.h
View file @ 2dd8cc90
...@@ -22,9 +22,11 @@ ...@@ -22,9 +22,11 @@
#include <linux/console.h> #include <linux/console.h>
#include <linux/sysrq.h> #include <linux/sysrq.h>
#include <linux/serial.h> #include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/device.h> #include <linux/device.h>
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
#include <linux/mv643xx.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/irq.h> #include <asm/irq.h>
...@@ -33,8 +35,7 @@ ...@@ -33,8 +35,7 @@
#define SUPPORT_SYSRQ #define SUPPORT_SYSRQ
#endif #endif
#include <linux/serial_core.h> #define MPSC_NUM_CTLRS 2
#include "mpsc_defs.h"
/* /*
* Descriptors and buffers must be cache line aligned. * Descriptors and buffers must be cache line aligned.
...@@ -79,11 +80,11 @@ struct mpsc_tx_desc { ...@@ -79,11 +80,11 @@ struct mpsc_tx_desc {
* between the two MPSC controllers. This struct contains those shared regs. * between the two MPSC controllers. This struct contains those shared regs.
*/ */
struct mpsc_shared_regs { struct mpsc_shared_regs {
u32 mpsc_routing_base_p; phys_addr_t mpsc_routing_base_p;
u32 sdma_intr_base_p; phys_addr_t sdma_intr_base_p;
u32 mpsc_routing_base; void *mpsc_routing_base;
u32 sdma_intr_base; void *sdma_intr_base;
u32 MPSC_MRR_m; u32 MPSC_MRR_m;
u32 MPSC_RCRR_m; u32 MPSC_RCRR_m;
...@@ -114,14 +115,14 @@ struct mpsc_port_info { ...@@ -114,14 +115,14 @@ struct mpsc_port_info {
int default_flow; int default_flow;
/* Physical addresses of various blocks of registers (from platform) */ /* Physical addresses of various blocks of registers (from platform) */
u32 mpsc_base_p; phys_addr_t mpsc_base_p;
u32 sdma_base_p; phys_addr_t sdma_base_p;
u32 brg_base_p; phys_addr_t brg_base_p;
/* Virtual addresses of various blocks of registers (from platform) */ /* Virtual addresses of various blocks of registers (from platform) */
u32 mpsc_base; void *mpsc_base;
u32 sdma_base; void *sdma_base;
u32 brg_base; void *brg_base;
/* Descriptor ring and buffer allocations */ /* Descriptor ring and buffer allocations */
void *dma_region; void *dma_region;
...@@ -149,135 +150,6 @@ struct mpsc_port_info { ...@@ -149,135 +150,6 @@ struct mpsc_port_info {
struct mpsc_shared_regs *shared_regs; struct mpsc_shared_regs *shared_regs;
}; };
#if defined(CONFIG_PPC32)
#if defined(CONFIG_NOT_COHERENT_CACHE)
/* No-ops when coherency is off b/c dma_cache_sync() does that work */
#define MPSC_CACHE_INVALIDATE(pi, s, e)
#define MPSC_CACHE_FLUSH(pi, s, e)
#else /* defined(CONFIG_NOT_COHERENT_CACHE) */
/* Coherency is on so dma_cache_sync() is no-op so must do manually */
#define MPSC_CACHE_INVALIDATE(pi, s, e) { \
if (pi->cache_mgmt) { \
invalidate_dcache_range((ulong)s, (ulong)e); \
} \
}
#define MPSC_CACHE_FLUSH(pi, s, e) { \
if (pi->cache_mgmt) { \
flush_dcache_range((ulong)s, (ulong)e); \
} \
}
#endif /* defined(CONFIG_NOT_COHERENT_CACHE) */
#else /* defined(CONFIG_PPC32) */
/* Other architectures need to fill this in */
#define MPSC_CACHE_INVALIDATE(pi, s, e) BUG()
#define MPSC_CACHE_FLUSH(pi, s, e) BUG()
#endif /* defined(CONFIG_PPC32) */
/*
* 'MASK_INSERT' takes the low-order 'n' bits of 'i', shifts it 'b' bits to
* the left, and inserts it into the target 't'. The corresponding bits in
* 't' will have been cleared before the bits in 'i' are inserted.
*/
#ifdef CONFIG_PPC32
#define MASK_INSERT(t, i, n, b) ({ \
u32 rval = (t); \
__asm__ __volatile__( \
"rlwimi %0,%2,%4,32-(%3+%4),31-%4\n" \
: "=r" (rval) \
: "0" (rval), "r" (i), "i" (n), "i" (b)); \
rval; \
})
#else
/* These macros are really just examples. Feel free to change them --MAG */
#define GEN_MASK(n, b) \
({ \
u32 m, sl, sr; \
sl = 32 - (n); \
sr = sl - (b); \
m = (0xffffffff << sl) >> sr; \
})
#define MASK_INSERT(t, i, n, b) \
({ \
u32 m, rval = (t); \
m = GEN_MASK((n), (b)); \
rval &= ~m; \
rval |= (((i) << (b)) & m); \
})
#endif
/* I/O macros for regs that you can read */
#define MPSC_READ(pi, unit, offset) \
readl((volatile void *)((pi)->unit##_base + (offset)))
#define MPSC_WRITE(pi, unit, offset, v) \
writel(v, (volatile void *)((pi)->unit##_base + (offset)))
#define MPSC_MOD_FIELD(pi, unit, offset, num_bits, shift, val) \
{ \
u32 v; \
v = readl((volatile void *)((pi)->unit##_base + (offset))); \
writel(MASK_INSERT(v,val,num_bits,shift), \
(volatile void *)((pi)->unit##_base+(offset))); \
}
/* Macros for regs with erratum that are not shared between MPSC ctlrs */
#define MPSC_READ_M(pi, unit, offset) \
({ \
u32 v; \
if ((pi)->mirror_regs) v = (pi)->offset##_m; \
else v = readl((volatile void *)((pi)->unit##_base + (offset)));\
v; \
})
#define MPSC_WRITE_M(pi, unit, offset, v) \
({ \
if ((pi)->mirror_regs) (pi)->offset##_m = v; \
writel(v, (volatile void *)((pi)->unit##_base + (offset))); \
})
#define MPSC_MOD_FIELD_M(pi, unit, offset, num_bits, shift, val) \
({ \
u32 v; \
if ((pi)->mirror_regs) v = (pi)->offset##_m; \
else v = readl((volatile void *)((pi)->unit##_base + (offset)));\
v = MASK_INSERT(v, val, num_bits, shift); \
if ((pi)->mirror_regs) (pi)->offset##_m = v; \
writel(v, (volatile void *)((pi)->unit##_base + (offset))); \
})
/* Macros for regs with erratum that are shared between MPSC ctlrs */
#define MPSC_READ_S(pi, unit, offset) \
({ \
u32 v; \
if ((pi)->mirror_regs) v = (pi)->shared_regs->offset##_m; \
else v = readl((volatile void *)((pi)->shared_regs->unit##_base + \
(offset))); \
v; \
})
#define MPSC_WRITE_S(pi, unit, offset, v) \
({ \
if ((pi)->mirror_regs) (pi)->shared_regs->offset##_m = v; \
writel(v, (volatile void *)((pi)->shared_regs->unit##_base + \
(offset))); \
})
#define MPSC_MOD_FIELD_S(pi, unit, offset, num_bits, shift, val) \
({ \
u32 v; \
if ((pi)->mirror_regs) v = (pi)->shared_regs->offset##_m; \
else v = readl((volatile void *)((pi)->shared_regs->unit##_base + \
(offset))); \
v = MASK_INSERT(v, val, num_bits, shift); \
if ((pi)->mirror_regs) (pi)->shared_regs->offset##_m = v; \
writel(v, (volatile void *)((pi)->shared_regs->unit##_base + \
(offset))); \
})
/* Hooks to platform-specific code */ /* Hooks to platform-specific code */
int mpsc_platform_register_driver(void); int mpsc_platform_register_driver(void);
void mpsc_platform_unregister_driver(void); void mpsc_platform_unregister_driver(void);
...@@ -286,4 +158,132 @@ void mpsc_platform_unregister_driver(void); ...@@ -286,4 +158,132 @@ void mpsc_platform_unregister_driver(void);
struct mpsc_port_info *mpsc_device_probe(int index); struct mpsc_port_info *mpsc_device_probe(int index);
struct mpsc_port_info *mpsc_device_remove(int index); struct mpsc_port_info *mpsc_device_remove(int index);
/*
*****************************************************************************
*
* Multi-Protocol Serial Controller Interface Registers
*
*****************************************************************************
*/
/* Main Configuratino Register Offsets */
#define MPSC_MMCRL 0x0000
#define MPSC_MMCRH 0x0004
#define MPSC_MPCR 0x0008
#define MPSC_CHR_1 0x000c
#define MPSC_CHR_2 0x0010
#define MPSC_CHR_3 0x0014
#define MPSC_CHR_4 0x0018
#define MPSC_CHR_5 0x001c
#define MPSC_CHR_6 0x0020
#define MPSC_CHR_7 0x0024
#define MPSC_CHR_8 0x0028
#define MPSC_CHR_9 0x002c
#define MPSC_CHR_10 0x0030
#define MPSC_CHR_11 0x0034
#define MPSC_MPCR_FRZ (1 << 9)
#define MPSC_MPCR_CL_5 0
#define MPSC_MPCR_CL_6 1
#define MPSC_MPCR_CL_7 2
#define MPSC_MPCR_CL_8 3
#define MPSC_MPCR_SBL_1 0
#define MPSC_MPCR_SBL_2 1
#define MPSC_CHR_2_TEV (1<<1)
#define MPSC_CHR_2_TA (1<<7)
#define MPSC_CHR_2_TTCS (1<<9)
#define MPSC_CHR_2_REV (1<<17)
#define MPSC_CHR_2_RA (1<<23)
#define MPSC_CHR_2_CRD (1<<25)
#define MPSC_CHR_2_EH (1<<31)
#define MPSC_CHR_2_PAR_ODD 0
#define MPSC_CHR_2_PAR_SPACE 1
#define MPSC_CHR_2_PAR_EVEN 2
#define MPSC_CHR_2_PAR_MARK 3
/* MPSC Signal Routing */
#define MPSC_MRR 0x0000
#define MPSC_RCRR 0x0004
#define MPSC_TCRR 0x0008
/*
*****************************************************************************
*
* Serial DMA Controller Interface Registers
*
*****************************************************************************
*/
#define SDMA_SDC 0x0000
#define SDMA_SDCM 0x0008
#define SDMA_RX_DESC 0x0800
#define SDMA_RX_BUF_PTR 0x0808
#define SDMA_SCRDP 0x0810
#define SDMA_TX_DESC 0x0c00
#define SDMA_SCTDP 0x0c10
#define SDMA_SFTDP 0x0c14
#define SDMA_DESC_CMDSTAT_PE (1<<0)
#define SDMA_DESC_CMDSTAT_CDL (1<<1)
#define SDMA_DESC_CMDSTAT_FR (1<<3)
#define SDMA_DESC_CMDSTAT_OR (1<<6)
#define SDMA_DESC_CMDSTAT_BR (1<<9)
#define SDMA_DESC_CMDSTAT_MI (1<<10)
#define SDMA_DESC_CMDSTAT_A (1<<11)
#define SDMA_DESC_CMDSTAT_AM (1<<12)
#define SDMA_DESC_CMDSTAT_CT (1<<13)
#define SDMA_DESC_CMDSTAT_C (1<<14)
#define SDMA_DESC_CMDSTAT_ES (1<<15)
#define SDMA_DESC_CMDSTAT_L (1<<16)
#define SDMA_DESC_CMDSTAT_F (1<<17)
#define SDMA_DESC_CMDSTAT_P (1<<18)
#define SDMA_DESC_CMDSTAT_EI (1<<23)
#define SDMA_DESC_CMDSTAT_O (1<<31)
#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
SDMA_DESC_CMDSTAT_EI)
#define SDMA_SDC_RFT (1<<0)
#define SDMA_SDC_SFM (1<<1)
#define SDMA_SDC_BLMR (1<<6)
#define SDMA_SDC_BLMT (1<<7)
#define SDMA_SDC_POVR (1<<8)
#define SDMA_SDC_RIFB (1<<9)
#define SDMA_SDCM_ERD (1<<7)
#define SDMA_SDCM_AR (1<<15)
#define SDMA_SDCM_STD (1<<16)
#define SDMA_SDCM_TXD (1<<23)
#define SDMA_SDCM_AT (1<<31)
#define SDMA_0_CAUSE_RXBUF (1<<0)
#define SDMA_0_CAUSE_RXERR (1<<1)
#define SDMA_0_CAUSE_TXBUF (1<<2)
#define SDMA_0_CAUSE_TXEND (1<<3)
#define SDMA_1_CAUSE_RXBUF (1<<8)
#define SDMA_1_CAUSE_RXERR (1<<9)
#define SDMA_1_CAUSE_TXBUF (1<<10)
#define SDMA_1_CAUSE_TXEND (1<<11)
#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
/* SDMA Interrupt registers */
#define SDMA_INTR_CAUSE 0x0000
#define SDMA_INTR_MASK 0x0080
/*
*****************************************************************************
*
* Baud Rate Generator Interface Registers
*
*****************************************************************************
*/
#define BRG_BCR 0x0000
#define BRG_BTR 0x0004
#endif /* __MPSC_H__ */ #endif /* __MPSC_H__ */
drivers/serial/mpsc_defs.h deleted 100644 → 0
View file @ 7fe83ffc
/*
* drivers/serial/mpsc_defs.h
*
* Register definitions for the Marvell Multi-Protocol Serial Controller (MPSC),
* Serial DMA Controller (SDMA), and Baud Rate Generator (BRG).
*
* Author: Mark A. Greer <mgreer@mvista.com>
*
* 2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __MPSC_DEFS_H__
#define __MPSC_DEFS_H__
#define MPSC_NUM_CTLRS 2
/*
*****************************************************************************
*
* Multi-Protocol Serial Controller Interface Registers
*
*****************************************************************************
*/
/* Main Configuratino Register Offsets */
#define MPSC_MMCRL 0x0000
#define MPSC_MMCRH 0x0004
#define MPSC_MPCR 0x0008
#define MPSC_CHR_1 0x000c
#define MPSC_CHR_2 0x0010
#define MPSC_CHR_3 0x0014
#define MPSC_CHR_4 0x0018
#define MPSC_CHR_5 0x001c
#define MPSC_CHR_6 0x0020
#define MPSC_CHR_7 0x0024
#define MPSC_CHR_8 0x0028
#define MPSC_CHR_9 0x002c
#define MPSC_CHR_10 0x0030
#define MPSC_CHR_11 0x0034
#define MPSC_MPCR_CL_5 0
#define MPSC_MPCR_CL_6 1
#define MPSC_MPCR_CL_7 2
#define MPSC_MPCR_CL_8 3
#define MPSC_MPCR_SBL_1 0
#define MPSC_MPCR_SBL_2 3
#define MPSC_CHR_2_TEV (1<<1)
#define MPSC_CHR_2_TA (1<<7)
#define MPSC_CHR_2_TTCS (1<<9)
#define MPSC_CHR_2_REV (1<<17)
#define MPSC_CHR_2_RA (1<<23)
#define MPSC_CHR_2_CRD (1<<25)
#define MPSC_CHR_2_EH (1<<31)
#define MPSC_CHR_2_PAR_ODD 0
#define MPSC_CHR_2_PAR_SPACE 1
#define MPSC_CHR_2_PAR_EVEN 2
#define MPSC_CHR_2_PAR_MARK 3
/* MPSC Signal Routing */
#define MPSC_MRR 0x0000
#define MPSC_RCRR 0x0004
#define MPSC_TCRR 0x0008
/*
*****************************************************************************
*
* Serial DMA Controller Interface Registers
*
*****************************************************************************
*/
#define SDMA_SDC 0x0000
#define SDMA_SDCM 0x0008
#define SDMA_RX_DESC 0x0800
#define SDMA_RX_BUF_PTR 0x0808
#define SDMA_SCRDP 0x0810
#define SDMA_TX_DESC 0x0c00
#define SDMA_SCTDP 0x0c10
#define SDMA_SFTDP 0x0c14
#define SDMA_DESC_CMDSTAT_PE (1<<0)
#define SDMA_DESC_CMDSTAT_CDL (1<<1)
#define SDMA_DESC_CMDSTAT_FR (1<<3)
#define SDMA_DESC_CMDSTAT_OR (1<<6)
#define SDMA_DESC_CMDSTAT_BR (1<<9)
#define SDMA_DESC_CMDSTAT_MI (1<<10)
#define SDMA_DESC_CMDSTAT_A (1<<11)
#define SDMA_DESC_CMDSTAT_AM (1<<12)
#define SDMA_DESC_CMDSTAT_CT (1<<13)
#define SDMA_DESC_CMDSTAT_C (1<<14)
#define SDMA_DESC_CMDSTAT_ES (1<<15)
#define SDMA_DESC_CMDSTAT_L (1<<16)
#define SDMA_DESC_CMDSTAT_F (1<<17)
#define SDMA_DESC_CMDSTAT_P (1<<18)
#define SDMA_DESC_CMDSTAT_EI (1<<23)
#define SDMA_DESC_CMDSTAT_O (1<<31)
#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
SDMA_DESC_CMDSTAT_EI)
#define SDMA_SDC_RFT (1<<0)
#define SDMA_SDC_SFM (1<<1)
#define SDMA_SDC_BLMR (1<<6)
#define SDMA_SDC_BLMT (1<<7)
#define SDMA_SDC_POVR (1<<8)
#define SDMA_SDC_RIFB (1<<9)
#define SDMA_SDCM_ERD (1<<7)
#define SDMA_SDCM_AR (1<<15)
#define SDMA_SDCM_STD (1<<16)
#define SDMA_SDCM_TXD (1<<23)
#define SDMA_SDCM_AT (1<<31)
#define SDMA_0_CAUSE_RXBUF (1<<0)
#define SDMA_0_CAUSE_RXERR (1<<1)
#define SDMA_0_CAUSE_TXBUF (1<<2)
#define SDMA_0_CAUSE_TXEND (1<<3)
#define SDMA_1_CAUSE_RXBUF (1<<8)
#define SDMA_1_CAUSE_RXERR (1<<9)
#define SDMA_1_CAUSE_TXBUF (1<<10)
#define SDMA_1_CAUSE_TXEND (1<<11)
#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
/* SDMA Interrupt registers */
#define SDMA_INTR_CAUSE 0x0000
#define SDMA_INTR_MASK 0x0080
/*
*****************************************************************************
*
* Baud Rate Generator Interface Registers
*
*****************************************************************************
*/
#define BRG_BCR 0x0000
#define BRG_BTR 0x0004
#endif /*__MPSC_DEFS_H__ */
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