Commit 2ec7752f authored by Fengwei Yin's avatar Fengwei Yin Committed by Kalle Valo

wcn36xx: handle rx skb allocation failure to avoid system crash

Lawrence reported that git clone could make system crash on a
Qualcomm ARM soc based device (DragonBoard, 1G memory without
swap) running 64bit Debian.

It's turned out the crash is related with rx skb allocation
failure. git could consume more than 600MB anonymous memory.
And system is in extremely memory shortage case.

But driver didn't handle the rx allocation failure case. This patch
doesn't submit skb to upper layer if rx skb allocation fails.
Instead, it reuse the old skb for rx DMA again. It's more like
drop the packets if system is in memory shortage case.

With this change, git clone is OOMed instead of system crash.
Reported-by: default avatarKing, Lawrence <lking@qti.qualcomm.com>
Signed-off-by: default avatarFengwei Yin <fengwei.yin@linaro.org>
Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
parent 19f2ce3f
...@@ -474,36 +474,37 @@ static int wcn36xx_rx_handle_packets(struct wcn36xx *wcn, ...@@ -474,36 +474,37 @@ static int wcn36xx_rx_handle_packets(struct wcn36xx *wcn,
struct wcn36xx_dxe_desc *dxe = ctl->desc; struct wcn36xx_dxe_desc *dxe = ctl->desc;
dma_addr_t dma_addr; dma_addr_t dma_addr;
struct sk_buff *skb; struct sk_buff *skb;
int ret = 0, int_mask;
u32 value;
if (ch->ch_type == WCN36XX_DXE_CH_RX_L) {
value = WCN36XX_DXE_CTRL_RX_L;
int_mask = WCN36XX_DXE_INT_CH1_MASK;
} else {
value = WCN36XX_DXE_CTRL_RX_H;
int_mask = WCN36XX_DXE_INT_CH3_MASK;
}
while (!(dxe->ctrl & WCN36XX_DXE_CTRL_VALID_MASK)) { while (!(dxe->ctrl & WCN36XX_DXE_CTRL_VALID_MASK)) {
skb = ctl->skb; skb = ctl->skb;
dma_addr = dxe->dst_addr_l; dma_addr = dxe->dst_addr_l;
wcn36xx_dxe_fill_skb(wcn->dev, ctl); ret = wcn36xx_dxe_fill_skb(wcn->dev, ctl);
if (0 == ret) {
switch (ch->ch_type) { /* new skb allocation ok. Use the new one and queue
case WCN36XX_DXE_CH_RX_L: * the old one to network system.
dxe->ctrl = WCN36XX_DXE_CTRL_RX_L; */
wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_ENCH_ADDR,
WCN36XX_DXE_INT_CH1_MASK);
break;
case WCN36XX_DXE_CH_RX_H:
dxe->ctrl = WCN36XX_DXE_CTRL_RX_H;
wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_ENCH_ADDR,
WCN36XX_DXE_INT_CH3_MASK);
break;
default:
wcn36xx_warn("Unknown channel\n");
}
dma_unmap_single(wcn->dev, dma_addr, WCN36XX_PKT_SIZE, dma_unmap_single(wcn->dev, dma_addr, WCN36XX_PKT_SIZE,
DMA_FROM_DEVICE); DMA_FROM_DEVICE);
wcn36xx_rx_skb(wcn, skb); wcn36xx_rx_skb(wcn, skb);
} /* else keep old skb not submitted and use it for rx DMA */
wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_ENCH_ADDR, int_mask);
dxe->ctrl = value;
ctl = ctl->next; ctl = ctl->next;
dxe = ctl->desc; dxe = ctl->desc;
} }
ch->head_blk_ctl = ctl; ch->head_blk_ctl = ctl;
return 0; return 0;
} }
......
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