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Commit 2f3cf84f authored by Jes Sorensen's avatar Jes Sorensen Committed by Greg Kroah-Hartman
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staging: rtl8723au: odm_ConfigBB_PHY_8723A() always issues 32 bit writes 

Signed-off-by: default avatarJes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 539b61bf
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Inline Side-by-side
Showing with 31 additions and 34 deletions
drivers/staging/rtl8723au/hal/HalHWImg8723A_BB.c
View file @ 2f3cf84f
...@@ -236,7 +236,7 @@ void ODM_ReadAndConfig_AGC_TAB_1T_8723A(struct dm_odm_t *pDM_Odm) ...@@ -236,7 +236,7 @@ void ODM_ReadAndConfig_AGC_TAB_1T_8723A(struct dm_odm_t *pDM_Odm)
continue; continue;
} else { } else {
if (!CheckCondition(Array[i], hex)) { if (!CheckCondition(Array[i], hex)) {
/* Discard the following (offset, data) pairs. */ /* Discard the following (offset, data) pairs */
READ_NEXT_PAIR(v1, v2, i); READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD && while (v2 != 0xDEAD &&
v2 != 0xCDEF && v2 != 0xCDEF &&
...@@ -244,7 +244,8 @@ void ODM_ReadAndConfig_AGC_TAB_1T_8723A(struct dm_odm_t *pDM_Odm) ...@@ -244,7 +244,8 @@ void ODM_ReadAndConfig_AGC_TAB_1T_8723A(struct dm_odm_t *pDM_Odm)
READ_NEXT_PAIR(v1, v2, i); READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */ i -= 2; /* prevent from for-loop += 2 */
} else { } else {
/* Configure matched pairs and skip to end of if-else. */ /* Configure matched pairs and skip to
end of if-else. */
READ_NEXT_PAIR(v1, v2, i); READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD && while (v2 != 0xDEAD &&
v2 != 0xCDEF && v2 != 0xCDEF &&
...@@ -479,11 +480,11 @@ void ODM_ReadAndConfig_PHY_REG_1T_8723A(struct dm_odm_t *pDM_Odm) ...@@ -479,11 +480,11 @@ void ODM_ReadAndConfig_PHY_REG_1T_8723A(struct dm_odm_t *pDM_Odm)
/* This (offset, data) pair meets the condition. */ /* This (offset, data) pair meets the condition. */
if (v1 < 0xCDCDCDCD) { if (v1 < 0xCDCDCDCD) {
odm_ConfigBB_PHY_8723A(pDM_Odm, v1, bMaskDWord, v2); odm_ConfigBB_PHY_8723A(pDM_Odm, v1, v2);
continue; continue;
} else { } else {
if (!CheckCondition(Array[i], hex)) { if (!CheckCondition(Array[i], hex)) {
/* Discard the following (offset, data) pairs. */ /* Discard the following (offset, data) pairs */
READ_NEXT_PAIR(v1, v2, i); READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD && while (v2 != 0xDEAD &&
v2 != 0xCDEF && v2 != 0xCDEF &&
...@@ -491,12 +492,13 @@ void ODM_ReadAndConfig_PHY_REG_1T_8723A(struct dm_odm_t *pDM_Odm) ...@@ -491,12 +492,13 @@ void ODM_ReadAndConfig_PHY_REG_1T_8723A(struct dm_odm_t *pDM_Odm)
READ_NEXT_PAIR(v1, v2, i); READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */ i -= 2; /* prevent from for-loop += 2 */
} else { } else {
/* Configure matched pairs and skip to end of if-else. */ /* Configure matched pairs and skip to
end of if-else. */
READ_NEXT_PAIR(v1, v2, i); READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD && while (v2 != 0xDEAD &&
v2 != 0xCDEF && v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen - 2) { v2 != 0xCDCD && i < ArrayLen - 2) {
odm_ConfigBB_PHY_8723A(pDM_Odm, v1, bMaskDWord, v2); odm_ConfigBB_PHY_8723A(pDM_Odm, v1, v2);
READ_NEXT_PAIR(v1, v2, i); READ_NEXT_PAIR(v1, v2, i);
} }
while (v2 != 0xDEAD && i < ArrayLen - 2) while (v2 != 0xDEAD && i < ArrayLen - 2)
...@@ -518,7 +520,7 @@ static u32 Array_PHY_REG_MP_8723A[] = { ...@@ -518,7 +520,7 @@ static u32 Array_PHY_REG_MP_8723A[] = {
void ODM_ReadAndConfig_PHY_REG_MP_8723A(struct dm_odm_t *pDM_Odm) void ODM_ReadAndConfig_PHY_REG_MP_8723A(struct dm_odm_t *pDM_Odm)
{ {
u32 hex = 0; u32 hex = 0;
u32 i = 0; u32 i;
u8 platform = 0x04; u8 platform = 0x04;
u8 board = pDM_Odm->BoardType; u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_PHY_REG_MP_8723A)/sizeof(u32); u32 ArrayLen = sizeof(Array_PHY_REG_MP_8723A)/sizeof(u32);
...@@ -534,11 +536,11 @@ void ODM_ReadAndConfig_PHY_REG_MP_8723A(struct dm_odm_t *pDM_Odm) ...@@ -534,11 +536,11 @@ void ODM_ReadAndConfig_PHY_REG_MP_8723A(struct dm_odm_t *pDM_Odm)
/* This (offset, data) pair meets the condition. */ /* This (offset, data) pair meets the condition. */
if (v1 < 0xCDCDCDCD) { if (v1 < 0xCDCDCDCD) {
odm_ConfigBB_PHY_8723A(pDM_Odm, v1, bMaskDWord, v2); odm_ConfigBB_PHY_8723A(pDM_Odm, v1, v2);
continue; continue;
} else { } else {
if (!CheckCondition(Array[i], hex)) { if (!CheckCondition(Array[i], hex)) {
/* Discard the following (offset, data) pairs. */ /* Discard the following (offset, data) pairs */
READ_NEXT_PAIR(v1, v2, i); READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD && while (v2 != 0xDEAD &&
v2 != 0xCDEF && v2 != 0xCDEF &&
...@@ -546,12 +548,13 @@ void ODM_ReadAndConfig_PHY_REG_MP_8723A(struct dm_odm_t *pDM_Odm) ...@@ -546,12 +548,13 @@ void ODM_ReadAndConfig_PHY_REG_MP_8723A(struct dm_odm_t *pDM_Odm)
READ_NEXT_PAIR(v1, v2, i); READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */ i -= 2; /* prevent from for-loop += 2 */
} else { } else {
/* Configure matched pairs and skip to end of if-else. */ /* Configure matched pairs and skip to
end of if-else. */
READ_NEXT_PAIR(v1, v2, i); READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD && while (v2 != 0xDEAD &&
v2 != 0xCDEF && v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen - 2) { v2 != 0xCDCD && i < ArrayLen - 2) {
odm_ConfigBB_PHY_8723A(pDM_Odm, v1, bMaskDWord, v2); odm_ConfigBB_PHY_8723A(pDM_Odm, v1, v2);
READ_NEXT_PAIR(v1, v2, i); READ_NEXT_PAIR(v1, v2, i);
} }
while (v2 != 0xDEAD && i < ArrayLen - 2) while (v2 != 0xDEAD && i < ArrayLen - 2)
......
drivers/staging/rtl8723au/hal/odm_RegConfig8723A.c
View file @ 2f3cf84f
...@@ -66,33 +66,27 @@ void odm_ConfigBB_AGC_8723A(struct dm_odm_t *pDM_Odm, u32 addr, u32 data) ...@@ -66,33 +66,27 @@ void odm_ConfigBB_AGC_8723A(struct dm_odm_t *pDM_Odm, u32 addr, u32 data)
} }
void void
odm_ConfigBB_PHY_8723A( odm_ConfigBB_PHY_8723A(struct dm_odm_t *pDM_Odm, u32 addr, u32 data)
struct dm_odm_t *pDM_Odm,
u32 Addr,
u32 Bitmask,
u32 Data
)
{ {
if (Addr == 0xfe) if (addr == 0xfe)
msleep(50); msleep(50);
else if (Addr == 0xfd) else if (addr == 0xfd)
mdelay(5); mdelay(5);
else if (Addr == 0xfc) else if (addr == 0xfc)
mdelay(1); mdelay(1);
else if (Addr == 0xfb) else if (addr == 0xfb)
udelay(50); udelay(50);
else if (Addr == 0xfa) else if (addr == 0xfa)
udelay(5); udelay(5);
else if (Addr == 0xf9) else if (addr == 0xf9)
udelay(1); udelay(1);
else if (Addr == 0xa24) else if (addr == 0xa24)
pDM_Odm->RFCalibrateInfo.RegA24 = Data; pDM_Odm->RFCalibrateInfo.RegA24 = data;
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); rtl8723au_write32(pDM_Odm->Adapter, addr, data);
/* Add 1us delay between BB/RF register setting. */ /* Add 1us delay between BB/RF register setting. */
udelay(1); udelay(1);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("===> ODM_ConfigBBWithHeaderFile23a: [PHY_REG] %08X %08X\n", ("===> %s: [PHY_REG] %08X %08X\n", __func__, addr, data));
Addr, Data));
} }
drivers/staging/rtl8723au/include/odm_RegConfig8723A.h
View file @ 2f3cf84f
...@@ -22,6 +22,6 @@ void odm_ConfigMAC_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u8 Data); ...@@ -22,6 +22,6 @@ void odm_ConfigMAC_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u8 Data);
void odm_ConfigBB_AGC_8723A(struct dm_odm_t *pDM_Odm, u32 addr, u32 data); void odm_ConfigBB_AGC_8723A(struct dm_odm_t *pDM_Odm, u32 addr, u32 data);
void odm_ConfigBB_PHY_8723A(struct dm_odm_t *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data); void odm_ConfigBB_PHY_8723A(struct dm_odm_t *pDM_Odm, u32 addr, u32 data);
#endif /* end of SUPPORT */ #endif /* end of SUPPORT */
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