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Commit 3116e748 authored by Mark Brown's avatar Mark Brown
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Merge remote-tracking branches 'asoc/topic/mc13783', 'asoc/topic/msm8916',... 

Merge remote-tracking branches 'asoc/topic/mc13783', 'asoc/topic/msm8916', 'asoc/topic/mt8173', 'asoc/topic/mtk' and 'asoc/topic/nau8540' into asoc-next
parents 87c90ac0 33953d85 42e193cd d6e2c4ff 7f12a563 fe83b1b7
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Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
View file @ 3116e748
...@@ -2,153 +2,143 @@ Mediatek AFE PCM controller for mt2701 ...@@ -2,153 +2,143 @@ Mediatek AFE PCM controller for mt2701
Required properties: Required properties:
- compatible = "mediatek,mt2701-audio"; - compatible = "mediatek,mt2701-audio";
- reg: register location and size
- interrupts: should contain AFE and ASYS interrupts - interrupts: should contain AFE and ASYS interrupts
- interrupt-names: should be "afe" and "asys" - interrupt-names: should be "afe" and "asys"
- power-domains: should define the power domain - power-domains: should define the power domain
- clocks: Must contain an entry for each entry in clock-names
See ../clocks/clock-bindings.txt for details
- clock-names: should have these clock names: - clock-names: should have these clock names:
"infra_sys_audio_clk", "infra_sys_audio_clk",
"top_audio_mux1_sel", "top_audio_mux1_sel",
"top_audio_mux2_sel", "top_audio_mux2_sel",
"top_audio_mux1_div", "top_audio_a1sys_hp",
"top_audio_mux2_div", "top_audio_a2sys_hp",
"top_audio_48k_timing", "i2s0_src_sel",
"top_audio_44k_timing", "i2s1_src_sel",
"top_audpll_mux_sel", "i2s2_src_sel",
"top_apll_sel", "i2s3_src_sel",
"top_aud1_pll_98M", "i2s0_src_div",
"top_aud2_pll_90M", "i2s1_src_div",
"top_hadds2_pll_98M", "i2s2_src_div",
"top_hadds2_pll_294M", "i2s3_src_div",
"top_audpll", "i2s0_mclk_en",
"top_audpll_d4", "i2s1_mclk_en",
"top_audpll_d8", "i2s2_mclk_en",
"top_audpll_d16", "i2s3_mclk_en",
"top_audpll_d24", "i2so0_hop_ck",
"top_audintbus_sel", "i2so1_hop_ck",
"clk_26m", "i2so2_hop_ck",
"top_syspll1_d4", "i2so3_hop_ck",
"top_aud_k1_src_sel", "i2si0_hop_ck",
"top_aud_k2_src_sel", "i2si1_hop_ck",
"top_aud_k3_src_sel", "i2si2_hop_ck",
"top_aud_k4_src_sel", "i2si3_hop_ck",
"top_aud_k5_src_sel", "asrc0_out_ck",
"top_aud_k6_src_sel", "asrc1_out_ck",
"top_aud_k1_src_div", "asrc2_out_ck",
"top_aud_k2_src_div", "asrc3_out_ck",
"top_aud_k3_src_div", "audio_afe_pd",
"top_aud_k4_src_div", "audio_afe_conn_pd",
"top_aud_k5_src_div", "audio_a1sys_pd",
"top_aud_k6_src_div", "audio_a2sys_pd",
"top_aud_i2s1_mclk", "audio_mrgif_pd";
"top_aud_i2s2_mclk", - assigned-clocks: list of input clocks and dividers for the audio system.
"top_aud_i2s3_mclk", See ../clocks/clock-bindings.txt for details.
"top_aud_i2s4_mclk", - assigned-clocks-parents: parent of input clocks of assigned clocks.
"top_aud_i2s5_mclk", - assigned-clock-rates: list of clock frequencies of assigned clocks.
"top_aud_i2s6_mclk",
"top_asm_m_sel", Must be a subnode of MediaTek audsys device tree node.
"top_asm_h_sel", See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
"top_univpll2_d4",
"top_univpll2_d2",
"top_syspll_d5";
Example: Example:
afe: mt2701-afe-pcm@11220000 { audsys: audio-subsystem@11220000 {
compatible = "mediatek,mt2701-audio"; compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
reg = <0 0x11220000 0 0x2000>, ...
<0 0x112A0000 0 0x20000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, afe: audio-controller {
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; compatible = "mediatek,mt2701-audio";
interrupt-names = "afe", "asys"; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_AUDIO>, interrupt-names = "afe", "asys";
<&topckgen CLK_TOP_AUD_MUX1_SEL>, power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_MUX1_DIV>, clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_MUX2_DIV>, <&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_48K_TIMING>, <&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_44K_TIMING>, <&topckgen CLK_TOP_AUD_48K_TIMING>,
<&topckgen CLK_TOP_AUDPLL_MUX_SEL>, <&topckgen CLK_TOP_AUD_44K_TIMING>,
<&topckgen CLK_TOP_APLL_SEL>, <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUD1PLL_98M>, <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
<&topckgen CLK_TOP_AUD2PLL_90M>, <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
<&topckgen CLK_TOP_HADDS2PLL_98M>, <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
<&topckgen CLK_TOP_HADDS2PLL_294M>, <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
<&topckgen CLK_TOP_AUDPLL>, <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
<&topckgen CLK_TOP_AUDPLL_D4>, <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
<&topckgen CLK_TOP_AUDPLL_D8>, <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
<&topckgen CLK_TOP_AUDPLL_D16>, <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
<&topckgen CLK_TOP_AUDPLL_D24>, <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
<&topckgen CLK_TOP_AUDINTBUS_SEL>, <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
<&clk26m>, <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
<&topckgen CLK_TOP_SYSPLL1_D4>, <&audsys CLK_AUD_I2SO1>,
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>, <&audsys CLK_AUD_I2SO2>,
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>, <&audsys CLK_AUD_I2SO3>,
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>, <&audsys CLK_AUD_I2SO4>,
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>, <&audsys CLK_AUD_I2SIN1>,
<&topckgen CLK_TOP_AUD_K5_SRC_SEL>, <&audsys CLK_AUD_I2SIN2>,
<&topckgen CLK_TOP_AUD_K6_SRC_SEL>, <&audsys CLK_AUD_I2SIN3>,
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>, <&audsys CLK_AUD_I2SIN4>,
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>, <&audsys CLK_AUD_ASRCO1>,
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>, <&audsys CLK_AUD_ASRCO2>,
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>, <&audsys CLK_AUD_ASRCO3>,
<&topckgen CLK_TOP_AUD_K5_SRC_DIV>, <&audsys CLK_AUD_ASRCO4>,
<&topckgen CLK_TOP_AUD_K6_SRC_DIV>, <&audsys CLK_AUD_AFE>,
<&topckgen CLK_TOP_AUD_I2S1_MCLK>, <&audsys CLK_AUD_AFE_CONN>,
<&topckgen CLK_TOP_AUD_I2S2_MCLK>, <&audsys CLK_AUD_A1SYS>,
<&topckgen CLK_TOP_AUD_I2S3_MCLK>, <&audsys CLK_AUD_A2SYS>,
<&topckgen CLK_TOP_AUD_I2S4_MCLK>, <&audsys CLK_AUD_AFE_MRGIF>;
<&topckgen CLK_TOP_AUD_I2S5_MCLK>,
<&topckgen CLK_TOP_AUD_I2S6_MCLK>, clock-names = "infra_sys_audio_clk",
<&topckgen CLK_TOP_ASM_M_SEL>, "top_audio_mux1_sel",
<&topckgen CLK_TOP_ASM_H_SEL>, "top_audio_mux2_sel",
<&topckgen CLK_TOP_UNIVPLL2_D4>, "top_audio_a1sys_hp",
<&topckgen CLK_TOP_UNIVPLL2_D2>, "top_audio_a2sys_hp",
<&topckgen CLK_TOP_SYSPLL_D5>; "i2s0_src_sel",
"i2s1_src_sel",
"i2s2_src_sel",
"i2s3_src_sel",
"i2s0_src_div",
"i2s1_src_div",
"i2s2_src_div",
"i2s3_src_div",
"i2s0_mclk_en",
"i2s1_mclk_en",
"i2s2_mclk_en",
"i2s3_mclk_en",
"i2so0_hop_ck",
"i2so1_hop_ck",
"i2so2_hop_ck",
"i2so3_hop_ck",
"i2si0_hop_ck",
"i2si1_hop_ck",
"i2si2_hop_ck",
"i2si3_hop_ck",
"asrc0_out_ck",
"asrc1_out_ck",
"asrc2_out_ck",
"asrc3_out_ck",
"audio_afe_pd",
"audio_afe_conn_pd",
"audio_a1sys_pd",
"audio_a2sys_pd",
"audio_mrgif_pd";
clock-names = "infra_sys_audio_clk", assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
"top_audio_mux1_sel", <&topckgen CLK_TOP_AUD_MUX2_SEL>,
"top_audio_mux2_sel", <&topckgen CLK_TOP_AUD_MUX1_DIV>,
"top_audio_mux1_div", <&topckgen CLK_TOP_AUD_MUX2_DIV>;
"top_audio_mux2_div", assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
"top_audio_48k_timing", <&topckgen CLK_TOP_AUD2PLL_90M>;
"top_audio_44k_timing", assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
"top_audpll_mux_sel", };
"top_apll_sel",
"top_aud1_pll_98M",
"top_aud2_pll_90M",
"top_hadds2_pll_98M",
"top_hadds2_pll_294M",
"top_audpll",
"top_audpll_d4",
"top_audpll_d8",
"top_audpll_d16",
"top_audpll_d24",
"top_audintbus_sel",
"clk_26m",
"top_syspll1_d4",
"top_aud_k1_src_sel",
"top_aud_k2_src_sel",
"top_aud_k3_src_sel",
"top_aud_k4_src_sel",
"top_aud_k5_src_sel",
"top_aud_k6_src_sel",
"top_aud_k1_src_div",
"top_aud_k2_src_div",
"top_aud_k3_src_div",
"top_aud_k4_src_div",
"top_aud_k5_src_div",
"top_aud_k6_src_div",
"top_aud_i2s1_mclk",
"top_aud_i2s2_mclk",
"top_aud_i2s3_mclk",
"top_aud_i2s4_mclk",
"top_aud_i2s5_mclk",
"top_aud_i2s6_mclk",
"top_asm_m_sel",
"top_asm_h_sel",
"top_univpll2_d4",
"top_univpll2_d2",
"top_syspll_d5";
}; };
sound/soc/codecs/mc13783.c
View file @ 3116e748
...@@ -610,6 +610,9 @@ static int mc13783_probe(struct snd_soc_codec *codec) ...@@ -610,6 +610,9 @@ static int mc13783_probe(struct snd_soc_codec *codec)
{ {
struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec); struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
snd_soc_codec_init_regmap(codec,
dev_get_regmap(codec->dev->parent, NULL));
/* these are the reset values */ /* these are the reset values */
mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893); mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893);
mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX1, 0x00d35A); mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX1, 0x00d35A);
...@@ -728,15 +731,9 @@ static struct snd_soc_dai_driver mc13783_dai_sync[] = { ...@@ -728,15 +731,9 @@ static struct snd_soc_dai_driver mc13783_dai_sync[] = {
} }
}; };
static struct regmap *mc13783_get_regmap(struct device *dev)
{
return dev_get_regmap(dev->parent, NULL);
}
static const struct snd_soc_codec_driver soc_codec_dev_mc13783 = { static const struct snd_soc_codec_driver soc_codec_dev_mc13783 = {
.probe = mc13783_probe, .probe = mc13783_probe,
.remove = mc13783_remove, .remove = mc13783_remove,
.get_regmap = mc13783_get_regmap,
.component_driver = { .component_driver = {
.controls = mc13783_control_list, .controls = mc13783_control_list,
.num_controls = ARRAY_SIZE(mc13783_control_list), .num_controls = ARRAY_SIZE(mc13783_control_list),
......
sound/soc/codecs/msm8916-wcd-analog.c
View file @ 3116e748
...@@ -712,6 +712,8 @@ static int pm8916_wcd_analog_probe(struct snd_soc_codec *codec) ...@@ -712,6 +712,8 @@ static int pm8916_wcd_analog_probe(struct snd_soc_codec *codec)
return err; return err;
} }
snd_soc_codec_init_regmap(codec,
dev_get_regmap(codec->dev->parent, NULL));
snd_soc_codec_set_drvdata(codec, priv); snd_soc_codec_set_drvdata(codec, priv);
priv->pmic_rev = snd_soc_read(codec, CDC_D_REVISION1); priv->pmic_rev = snd_soc_read(codec, CDC_D_REVISION1);
priv->codec_version = snd_soc_read(codec, CDC_D_PERPH_SUBTYPE); priv->codec_version = snd_soc_read(codec, CDC_D_PERPH_SUBTYPE);
...@@ -943,11 +945,6 @@ static int pm8916_wcd_analog_set_jack(struct snd_soc_codec *codec, ...@@ -943,11 +945,6 @@ static int pm8916_wcd_analog_set_jack(struct snd_soc_codec *codec,
return 0; return 0;
} }
static struct regmap *pm8916_get_regmap(struct device *dev)
{
return dev_get_regmap(dev->parent, NULL);
}
static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg) static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
{ {
struct pm8916_wcd_analog_priv *priv = arg; struct pm8916_wcd_analog_priv *priv = arg;
...@@ -1082,7 +1079,6 @@ static const struct snd_soc_codec_driver pm8916_wcd_analog = { ...@@ -1082,7 +1079,6 @@ static const struct snd_soc_codec_driver pm8916_wcd_analog = {
.probe = pm8916_wcd_analog_probe, .probe = pm8916_wcd_analog_probe,
.remove = pm8916_wcd_analog_remove, .remove = pm8916_wcd_analog_remove,
.set_jack = pm8916_wcd_analog_set_jack, .set_jack = pm8916_wcd_analog_set_jack,
.get_regmap = pm8916_get_regmap,
.component_driver = { .component_driver = {
.controls = pm8916_wcd_analog_snd_controls, .controls = pm8916_wcd_analog_snd_controls,
.num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls), .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),
......
sound/soc/codecs/nau8540.c
View file @ 3116e748
...@@ -233,6 +233,41 @@ static SOC_ENUM_SINGLE_DECL( ...@@ -233,6 +233,41 @@ static SOC_ENUM_SINGLE_DECL(
static const struct snd_kcontrol_new digital_ch1_mux = static const struct snd_kcontrol_new digital_ch1_mux =
SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum); SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum);
static int adc_power_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
if (SND_SOC_DAPM_EVENT_ON(event)) {
msleep(300);
/* DO12 and DO34 pad output enable */
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_DO12_TRI, 0);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_TRI, 0);
} else if (SND_SOC_DAPM_EVENT_OFF(event)) {
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
}
return 0;
}
static int aiftx_power_control(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *k, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
if (SND_SOC_DAPM_EVENT_OFF(event)) {
regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);
regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);
}
return 0;
}
static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = { static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
...@@ -247,14 +282,18 @@ static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = { ...@@ -247,14 +282,18 @@ static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0), SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0),
SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0), SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0),
SND_SOC_DAPM_ADC("ADC1", NULL, SND_SOC_DAPM_ADC_E("ADC1", NULL,
NAU8540_REG_POWER_MANAGEMENT, 0, 0), NAU8540_REG_POWER_MANAGEMENT, 0, 0, adc_power_control,
SND_SOC_DAPM_ADC("ADC2", NULL, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
NAU8540_REG_POWER_MANAGEMENT, 1, 0), SND_SOC_DAPM_ADC_E("ADC2", NULL,
SND_SOC_DAPM_ADC("ADC3", NULL, NAU8540_REG_POWER_MANAGEMENT, 1, 0, adc_power_control,
NAU8540_REG_POWER_MANAGEMENT, 2, 0), SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC("ADC4", NULL, SND_SOC_DAPM_ADC_E("ADC3", NULL,
NAU8540_REG_POWER_MANAGEMENT, 3, 0), NAU8540_REG_POWER_MANAGEMENT, 2, 0, adc_power_control,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_ADC_E("ADC4", NULL,
NAU8540_REG_POWER_MANAGEMENT, 3, 0, adc_power_control,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0), SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
...@@ -270,7 +309,8 @@ static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = { ...@@ -270,7 +309,8 @@ static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
SND_SOC_DAPM_MUX("Digital CH1 Mux", SND_SOC_DAPM_MUX("Digital CH1 Mux",
SND_SOC_NOPM, 0, 0, &digital_ch1_mux), SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0,
aiftx_power_control, SND_SOC_DAPM_POST_PMD),
}; };
static const struct snd_soc_dapm_route nau8540_dapm_routes[] = { static const struct snd_soc_dapm_route nau8540_dapm_routes[] = {
...@@ -575,7 +615,8 @@ static void nau8540_fll_apply(struct regmap *regmap, ...@@ -575,7 +615,8 @@ static void nau8540_fll_apply(struct regmap *regmap,
NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK, NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK,
NAU8540_CLK_SRC_MCLK | fll_param->mclk_src); NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);
regmap_update_bits(regmap, NAU8540_REG_FLL1, regmap_update_bits(regmap, NAU8540_REG_FLL1,
NAU8540_FLL_RATIO_MASK, fll_param->ratio); NAU8540_FLL_RATIO_MASK | NAU8540_ICTRL_LATCH_MASK,
fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT));
/* FLL 16-bit fractional input */ /* FLL 16-bit fractional input */
regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac); regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);
/* FLL 10-bit integer input */ /* FLL 10-bit integer input */
...@@ -596,13 +637,14 @@ static void nau8540_fll_apply(struct regmap *regmap, ...@@ -596,13 +637,14 @@ static void nau8540_fll_apply(struct regmap *regmap,
NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN | NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
NAU8540_FLL_FTR_SW_FILTER); NAU8540_FLL_FTR_SW_FILTER);
regmap_update_bits(regmap, NAU8540_REG_FLL6, regmap_update_bits(regmap, NAU8540_REG_FLL6,
NAU8540_SDM_EN, NAU8540_SDM_EN); NAU8540_SDM_EN | NAU8540_CUTOFF500,
NAU8540_SDM_EN | NAU8540_CUTOFF500);
} else { } else {
regmap_update_bits(regmap, NAU8540_REG_FLL5, regmap_update_bits(regmap, NAU8540_REG_FLL5,
NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN | NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU); NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU);
regmap_update_bits(regmap, regmap_update_bits(regmap, NAU8540_REG_FLL6,
NAU8540_REG_FLL6, NAU8540_SDM_EN, 0); NAU8540_SDM_EN | NAU8540_CUTOFF500, 0);
} }
} }
...@@ -617,17 +659,22 @@ static int nau8540_set_pll(struct snd_soc_codec *codec, int pll_id, int source, ...@@ -617,17 +659,22 @@ static int nau8540_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
switch (pll_id) { switch (pll_id) {
case NAU8540_CLK_FLL_MCLK: case NAU8540_CLK_FLL_MCLK:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_MCLK); NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
NAU8540_FLL_CLK_SRC_MCLK | 0);
break; break;
case NAU8540_CLK_FLL_BLK: case NAU8540_CLK_FLL_BLK:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_BLK); NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
NAU8540_FLL_CLK_SRC_BLK |
(0xf << NAU8540_GAIN_ERR_SFT));
break; break;
case NAU8540_CLK_FLL_FS: case NAU8540_CLK_FLL_FS:
regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_FS); NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
NAU8540_FLL_CLK_SRC_FS |
(0xf << NAU8540_GAIN_ERR_SFT));
break; break;
default: default:
...@@ -710,9 +757,24 @@ static void nau8540_init_regs(struct nau8540 *nau8540) ...@@ -710,9 +757,24 @@ static void nau8540_init_regs(struct nau8540 *nau8540)
regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL, regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,
NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN, NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN,
NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN); NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN);
/* ADC OSR selection, CLK_ADC = Fs * OSR */ /* ADC OSR selection, CLK_ADC = Fs * OSR;
* Channel time alignment enable.
*/
regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE, regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE,
NAU8540_ADC_OSR_MASK, NAU8540_ADC_OSR_64); NAU8540_CH_SYNC | NAU8540_ADC_OSR_MASK,
NAU8540_CH_SYNC | NAU8540_ADC_OSR_64);
/* PGA input mode selection */
regmap_update_bits(regmap, NAU8540_REG_FEPGA1,
NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT,
NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT);
regmap_update_bits(regmap, NAU8540_REG_FEPGA2,
NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT,
NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT);
/* DO12 and DO34 pad output disable */
regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL1,
NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL2,
NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
} }
static int __maybe_unused nau8540_suspend(struct snd_soc_codec *codec) static int __maybe_unused nau8540_suspend(struct snd_soc_codec *codec)
......
sound/soc/codecs/nau8540.h
View file @ 3116e748
...@@ -100,9 +100,13 @@ ...@@ -100,9 +100,13 @@
#define NAU8540_CLK_MCLK_SRC_MASK 0xf #define NAU8540_CLK_MCLK_SRC_MASK 0xf
/* FLL1 (0x04) */ /* FLL1 (0x04) */
#define NAU8540_ICTRL_LATCH_SFT 10
#define NAU8540_ICTRL_LATCH_MASK (0x7 << NAU8540_ICTRL_LATCH_SFT)
#define NAU8540_FLL_RATIO_MASK 0x7f #define NAU8540_FLL_RATIO_MASK 0x7f
/* FLL3 (0x06) */ /* FLL3 (0x06) */
#define NAU8540_GAIN_ERR_SFT 12
#define NAU8540_GAIN_ERR_MASK (0xf << NAU8540_GAIN_ERR_SFT)
#define NAU8540_FLL_CLK_SRC_SFT 10 #define NAU8540_FLL_CLK_SRC_SFT 10
#define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT) #define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT)
#define NAU8540_FLL_CLK_SRC_MCLK (0 << NAU8540_FLL_CLK_SRC_SFT) #define NAU8540_FLL_CLK_SRC_MCLK (0 << NAU8540_FLL_CLK_SRC_SFT)
...@@ -127,6 +131,7 @@ ...@@ -127,6 +131,7 @@
/* FLL6 (0x9) */ /* FLL6 (0x9) */
#define NAU8540_DCO_EN (0x1 << 15) #define NAU8540_DCO_EN (0x1 << 15)
#define NAU8540_SDM_EN (0x1 << 14) #define NAU8540_SDM_EN (0x1 << 14)
#define NAU8540_CUTOFF500 (0x1 << 13)
/* PCM_CTRL0 (0x10) */ /* PCM_CTRL0 (0x10) */
#define NAU8540_I2S_BP_SFT 7 #define NAU8540_I2S_BP_SFT 7
...@@ -146,6 +151,7 @@ ...@@ -146,6 +151,7 @@
#define NAU8540_I2S_DF_PCM_AB 0x3 #define NAU8540_I2S_DF_PCM_AB 0x3
/* PCM_CTRL1 (0x11) */ /* PCM_CTRL1 (0x11) */
#define NAU8540_I2S_DO12_TRI (0x1 << 15)
#define NAU8540_I2S_LRC_DIV_SFT 12 #define NAU8540_I2S_LRC_DIV_SFT 12
#define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT) #define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT)
#define NAU8540_I2S_DO12_OE (0x1 << 4) #define NAU8540_I2S_DO12_OE (0x1 << 4)
...@@ -156,6 +162,7 @@ ...@@ -156,6 +162,7 @@
#define NAU8540_I2S_BLK_DIV_MASK 0x7 #define NAU8540_I2S_BLK_DIV_MASK 0x7
/* PCM_CTRL1 (0x12) */ /* PCM_CTRL1 (0x12) */
#define NAU8540_I2S_DO34_TRI (0x1 << 15)
#define NAU8540_I2S_DO34_OE (0x1 << 11) #define NAU8540_I2S_DO34_OE (0x1 << 11)
#define NAU8540_I2S_TSLOT_L_MASK 0x3ff #define NAU8540_I2S_TSLOT_L_MASK 0x3ff
...@@ -165,6 +172,7 @@ ...@@ -165,6 +172,7 @@
#define NAU8540_TDM_TX_MASK 0xf #define NAU8540_TDM_TX_MASK 0xf
/* ADC_SAMPLE_RATE (0x3A) */ /* ADC_SAMPLE_RATE (0x3A) */
#define NAU8540_CH_SYNC (0x1 << 14)
#define NAU8540_ADC_OSR_MASK 0x3 #define NAU8540_ADC_OSR_MASK 0x3
#define NAU8540_ADC_OSR_256 0x3 #define NAU8540_ADC_OSR_256 0x3
#define NAU8540_ADC_OSR_128 0x2 #define NAU8540_ADC_OSR_128 0x2
...@@ -183,6 +191,18 @@ ...@@ -183,6 +191,18 @@
#define NAU8540_PRECHARGE_DIS (0x1 << 13) #define NAU8540_PRECHARGE_DIS (0x1 << 13)
#define NAU8540_GLOBAL_BIAS_EN (0x1 << 12) #define NAU8540_GLOBAL_BIAS_EN (0x1 << 12)
/* FEPGA1 (0x69) */
#define NAU8540_FEPGA1_MODCH2_SHT_SFT 7
#define NAU8540_FEPGA1_MODCH2_SHT (0x1 << NAU8540_FEPGA1_MODCH2_SHT_SFT)
#define NAU8540_FEPGA1_MODCH1_SHT_SFT 3
#define NAU8540_FEPGA1_MODCH1_SHT (0x1 << NAU8540_FEPGA1_MODCH1_SHT_SFT)
/* FEPGA2 (0x6A) */
#define NAU8540_FEPGA2_MODCH4_SHT_SFT 7
#define NAU8540_FEPGA2_MODCH4_SHT (0x1 << NAU8540_FEPGA2_MODCH4_SHT_SFT)
#define NAU8540_FEPGA2_MODCH3_SHT_SFT 3
#define NAU8540_FEPGA2_MODCH3_SHT (0x1 << NAU8540_FEPGA2_MODCH3_SHT_SFT)
/* System Clock Source */ /* System Clock Source */
enum { enum {
......
sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
View file @ 3116e748
...@@ -14,451 +14,285 @@ ...@@ -14,451 +14,285 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <sound/soc.h>
#include <linux/regmap.h>
#include <linux/pm_runtime.h>
#include "mt2701-afe-common.h" #include "mt2701-afe-common.h"
#include "mt2701-afe-clock-ctrl.h" #include "mt2701-afe-clock-ctrl.h"
static const char *aud_clks[MT2701_CLOCK_NUM] = { static const char *const base_clks[] = {
[MT2701_AUD_INFRA_SYS_AUDIO] = "infra_sys_audio_clk", [MT2701_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
[MT2701_AUD_AUD_MUX1_SEL] = "top_audio_mux1_sel", [MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
[MT2701_AUD_AUD_MUX2_SEL] = "top_audio_mux2_sel", [MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
[MT2701_AUD_AUD_MUX1_DIV] = "top_audio_mux1_div", [MT2701_TOP_AUD_A1SYS] = "top_audio_a1sys_hp",
[MT2701_AUD_AUD_MUX2_DIV] = "top_audio_mux2_div", [MT2701_TOP_AUD_A2SYS] = "top_audio_a2sys_hp",
[MT2701_AUD_AUD_48K_TIMING] = "top_audio_48k_timing", [MT2701_AUDSYS_AFE] = "audio_afe_pd",
[MT2701_AUD_AUD_44K_TIMING] = "top_audio_44k_timing", [MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
[MT2701_AUD_AUDPLL_MUX_SEL] = "top_audpll_mux_sel", [MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
[MT2701_AUD_APLL_SEL] = "top_apll_sel", [MT2701_AUDSYS_A2SYS] = "audio_a2sys_pd",
[MT2701_AUD_AUD1PLL_98M] = "top_aud1_pll_98M",
[MT2701_AUD_AUD2PLL_90M] = "top_aud2_pll_90M",
[MT2701_AUD_HADDS2PLL_98M] = "top_hadds2_pll_98M",
[MT2701_AUD_HADDS2PLL_294M] = "top_hadds2_pll_294M",
[MT2701_AUD_AUDPLL] = "top_audpll",
[MT2701_AUD_AUDPLL_D4] = "top_audpll_d4",
[MT2701_AUD_AUDPLL_D8] = "top_audpll_d8",
[MT2701_AUD_AUDPLL_D16] = "top_audpll_d16",
[MT2701_AUD_AUDPLL_D24] = "top_audpll_d24",
[MT2701_AUD_AUDINTBUS] = "top_audintbus_sel",
[MT2701_AUD_CLK_26M] = "clk_26m",
[MT2701_AUD_SYSPLL1_D4] = "top_syspll1_d4",
[MT2701_AUD_AUD_K1_SRC_SEL] = "top_aud_k1_src_sel",
[MT2701_AUD_AUD_K2_SRC_SEL] = "top_aud_k2_src_sel",
[MT2701_AUD_AUD_K3_SRC_SEL] = "top_aud_k3_src_sel",
[MT2701_AUD_AUD_K4_SRC_SEL] = "top_aud_k4_src_sel",
[MT2701_AUD_AUD_K5_SRC_SEL] = "top_aud_k5_src_sel",
[MT2701_AUD_AUD_K6_SRC_SEL] = "top_aud_k6_src_sel",
[MT2701_AUD_AUD_K1_SRC_DIV] = "top_aud_k1_src_div",
[MT2701_AUD_AUD_K2_SRC_DIV] = "top_aud_k2_src_div",
[MT2701_AUD_AUD_K3_SRC_DIV] = "top_aud_k3_src_div",
[MT2701_AUD_AUD_K4_SRC_DIV] = "top_aud_k4_src_div",
[MT2701_AUD_AUD_K5_SRC_DIV] = "top_aud_k5_src_div",
[MT2701_AUD_AUD_K6_SRC_DIV] = "top_aud_k6_src_div",
[MT2701_AUD_AUD_I2S1_MCLK] = "top_aud_i2s1_mclk",
[MT2701_AUD_AUD_I2S2_MCLK] = "top_aud_i2s2_mclk",
[MT2701_AUD_AUD_I2S3_MCLK] = "top_aud_i2s3_mclk",
[MT2701_AUD_AUD_I2S4_MCLK] = "top_aud_i2s4_mclk",
[MT2701_AUD_AUD_I2S5_MCLK] = "top_aud_i2s5_mclk",
[MT2701_AUD_AUD_I2S6_MCLK] = "top_aud_i2s6_mclk",
[MT2701_AUD_ASM_M_SEL] = "top_asm_m_sel",
[MT2701_AUD_ASM_H_SEL] = "top_asm_h_sel",
[MT2701_AUD_UNIVPLL2_D4] = "top_univpll2_d4",
[MT2701_AUD_UNIVPLL2_D2] = "top_univpll2_d2",
[MT2701_AUD_SYSPLL_D5] = "top_syspll_d5",
}; };
int mt2701_init_clock(struct mtk_base_afe *afe) int mt2701_init_clock(struct mtk_base_afe *afe)
{ {
struct mt2701_afe_private *afe_priv = afe->platform_priv; struct mt2701_afe_private *afe_priv = afe->platform_priv;
int i = 0; int i;
for (i = 0; i < MT2701_CLOCK_NUM; i++) { for (i = 0; i < MT2701_BASE_CLK_NUM; i++) {
afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]); afe_priv->base_ck[i] = devm_clk_get(afe->dev, base_clks[i]);
if (IS_ERR(afe_priv->clocks[i])) { if (IS_ERR(afe_priv->base_ck[i])) {
dev_warn(afe->dev, "%s devm_clk_get %s fail\n", dev_err(afe->dev, "failed to get %s\n", base_clks[i]);
__func__, aud_clks[i]); return PTR_ERR(afe_priv->base_ck[i]);
return PTR_ERR(aud_clks[i]); }
}
/* Get I2S related clocks */
for (i = 0; i < MT2701_I2S_NUM; i++) {
struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i];
char name[13];
snprintf(name, sizeof(name), "i2s%d_src_sel", i);
i2s_path->sel_ck = devm_clk_get(afe->dev, name);
if (IS_ERR(i2s_path->sel_ck)) {
dev_err(afe->dev, "failed to get %s\n", name);
return PTR_ERR(i2s_path->sel_ck);
}
snprintf(name, sizeof(name), "i2s%d_src_div", i);
i2s_path->div_ck = devm_clk_get(afe->dev, name);
if (IS_ERR(i2s_path->div_ck)) {
dev_err(afe->dev, "failed to get %s\n", name);
return PTR_ERR(i2s_path->div_ck);
}
snprintf(name, sizeof(name), "i2s%d_mclk_en", i);
i2s_path->mclk_ck = devm_clk_get(afe->dev, name);
if (IS_ERR(i2s_path->mclk_ck)) {
dev_err(afe->dev, "failed to get %s\n", name);
return PTR_ERR(i2s_path->mclk_ck);
}
snprintf(name, sizeof(name), "i2so%d_hop_ck", i);
i2s_path->hop_ck[I2S_OUT] = devm_clk_get(afe->dev, name);
if (IS_ERR(i2s_path->hop_ck[I2S_OUT])) {
dev_err(afe->dev, "failed to get %s\n", name);
return PTR_ERR(i2s_path->hop_ck[I2S_OUT]);
}
snprintf(name, sizeof(name), "i2si%d_hop_ck", i);
i2s_path->hop_ck[I2S_IN] = devm_clk_get(afe->dev, name);
if (IS_ERR(i2s_path->hop_ck[I2S_IN])) {
dev_err(afe->dev, "failed to get %s\n", name);
return PTR_ERR(i2s_path->hop_ck[I2S_IN]);
}
snprintf(name, sizeof(name), "asrc%d_out_ck", i);
i2s_path->asrco_ck = devm_clk_get(afe->dev, name);
if (IS_ERR(i2s_path->asrco_ck)) {
dev_err(afe->dev, "failed to get %s\n", name);
return PTR_ERR(i2s_path->asrco_ck);
} }
} }
/* Some platforms may support BT path */
afe_priv->mrgif_ck = devm_clk_get(afe->dev, "audio_mrgif_pd");
if (IS_ERR(afe_priv->mrgif_ck)) {
if (PTR_ERR(afe_priv->mrgif_ck) == -EPROBE_DEFER)
return -EPROBE_DEFER;
afe_priv->mrgif_ck = NULL;
}
return 0; return 0;
} }
int mt2701_afe_enable_clock(struct mtk_base_afe *afe) int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir)
{ {
int ret = 0; struct mt2701_afe_private *afe_priv = afe->platform_priv;
struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
int ret;
ret = mt2701_turn_on_a1sys_clock(afe); ret = clk_prepare_enable(i2s_path->asrco_ck);
if (ret) { if (ret) {
dev_err(afe->dev, "%s turn_on_a1sys_clock fail %d\n", dev_err(afe->dev, "failed to enable ASRC clock %d\n", ret);
__func__, ret);
return ret; return ret;
} }
ret = mt2701_turn_on_a2sys_clock(afe); ret = clk_prepare_enable(i2s_path->hop_ck[dir]);
if (ret) { if (ret) {
dev_err(afe->dev, "%s turn_on_a2sys_clock fail %d\n", dev_err(afe->dev, "failed to enable I2S clock %d\n", ret);
__func__, ret); goto err_hop_ck;
mt2701_turn_off_a1sys_clock(afe);
return ret;
} }
ret = mt2701_turn_on_afe_clock(afe); return 0;
if (ret) {
dev_err(afe->dev, "%s turn_on_afe_clock fail %d\n",
__func__, ret);
mt2701_turn_off_a1sys_clock(afe);
mt2701_turn_off_a2sys_clock(afe);
return ret;
}
regmap_update_bits(afe->regmap, ASYS_TOP_CON, err_hop_ck:
AUDIO_TOP_CON0_A1SYS_A2SYS_ON, clk_disable_unprepare(i2s_path->asrco_ck);
AUDIO_TOP_CON0_A1SYS_A2SYS_ON);
regmap_update_bits(afe->regmap, AFE_DAC_CON0,
AFE_DAC_CON0_AFE_ON,
AFE_DAC_CON0_AFE_ON);
regmap_write(afe->regmap, PWR2_TOP_CON,
PWR2_TOP_CON_INIT_VAL);
regmap_write(afe->regmap, PWR1_ASM_CON1,
PWR1_ASM_CON1_INIT_VAL);
regmap_write(afe->regmap, PWR2_ASM_CON1,
PWR2_ASM_CON1_INIT_VAL);
return 0; return ret;
} }
void mt2701_afe_disable_clock(struct mtk_base_afe *afe) void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir)
{ {
mt2701_turn_off_afe_clock(afe); struct mt2701_afe_private *afe_priv = afe->platform_priv;
mt2701_turn_off_a1sys_clock(afe); struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
mt2701_turn_off_a2sys_clock(afe);
regmap_update_bits(afe->regmap, ASYS_TOP_CON, clk_disable_unprepare(i2s_path->hop_ck[dir]);
AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0); clk_disable_unprepare(i2s_path->asrco_ck);
regmap_update_bits(afe->regmap, AFE_DAC_CON0,
AFE_DAC_CON0_AFE_ON, 0);
} }
int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe) int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id)
{ {
struct mt2701_afe_private *afe_priv = afe->platform_priv; struct mt2701_afe_private *afe_priv = afe->platform_priv;
int ret = 0; struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
/* Set Mux */
ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret);
goto A1SYS_CLK_AUD_MUX1_SEL_ERR;
}
ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL],
afe_priv->clocks[MT2701_AUD_AUD1PLL_98M]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
aud_clks[MT2701_AUD_AUD_MUX1_SEL],
aud_clks[MT2701_AUD_AUD1PLL_98M], ret);
goto A1SYS_CLK_AUD_MUX1_SEL_ERR;
}
/* Set Divider */
ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__,
aud_clks[MT2701_AUD_AUD_MUX1_DIV],
ret);
goto A1SYS_CLK_AUD_MUX1_DIV_ERR;
}
ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV],
MT2701_AUD_AUD_MUX1_DIV_RATE);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__,
aud_clks[MT2701_AUD_AUD_MUX1_DIV],
MT2701_AUD_AUD_MUX1_DIV_RATE, ret);
goto A1SYS_CLK_AUD_MUX1_DIV_ERR;
}
/* Enable clock gate */ return clk_prepare_enable(i2s_path->mclk_ck);
ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]); }
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[MT2701_AUD_AUD_48K_TIMING], ret);
goto A1SYS_CLK_AUD_48K_ERR;
}
/* Enable infra audio */ void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id)
ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); {
if (ret) { struct mt2701_afe_private *afe_priv = afe->platform_priv;
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
__func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
goto A1SYS_CLK_INFRA_ERR;
}
return 0; clk_disable_unprepare(i2s_path->mclk_ck);
}
A1SYS_CLK_INFRA_ERR: int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe)
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); {
A1SYS_CLK_AUD_48K_ERR: struct mt2701_afe_private *afe_priv = afe->platform_priv;
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
A1SYS_CLK_AUD_MUX1_DIV_ERR:
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
A1SYS_CLK_AUD_MUX1_SEL_ERR:
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
return ret; return clk_prepare_enable(afe_priv->mrgif_ck);
} }
void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe) void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe)
{ {
struct mt2701_afe_private *afe_priv = afe->platform_priv; struct mt2701_afe_private *afe_priv = afe->platform_priv;
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); clk_disable_unprepare(afe_priv->mrgif_ck);
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
} }
int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe) static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe)
{ {
struct mt2701_afe_private *afe_priv = afe->platform_priv; struct mt2701_afe_private *afe_priv = afe->platform_priv;
int ret = 0; int ret;
/* Set Mux */ /* Enable infra clock gate */
ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]); ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
if (ret) { if (ret)
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", return ret;
__func__, aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret);
goto A2SYS_CLK_AUD_MUX2_SEL_ERR;
}
ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL], /* Enable top a1sys clock gate */
afe_priv->clocks[MT2701_AUD_AUD2PLL_90M]); ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
if (ret) { if (ret)
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__, goto err_a1sys;
aud_clks[MT2701_AUD_AUD_MUX2_SEL],
aud_clks[MT2701_AUD_AUD2PLL_90M], ret);
goto A2SYS_CLK_AUD_MUX2_SEL_ERR;
}
/* Set Divider */ /* Enable top a2sys clock gate */
ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]); ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
if (ret) { if (ret)
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", goto err_a2sys;
__func__, aud_clks[MT2701_AUD_AUD_MUX2_DIV], ret);
goto A2SYS_CLK_AUD_MUX2_DIV_ERR;
}
ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV], /* Internal clock gates */
MT2701_AUD_AUD_MUX2_DIV_RATE); ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
if (ret) { if (ret)
dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__, goto err_afe;
aud_clks[MT2701_AUD_AUD_MUX2_DIV],
MT2701_AUD_AUD_MUX2_DIV_RATE, ret);
goto A2SYS_CLK_AUD_MUX2_DIV_ERR;
}
/* Enable clock gate */ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]); if (ret)
if (ret) { goto err_audio_a1sys;
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[MT2701_AUD_AUD_44K_TIMING], ret);
goto A2SYS_CLK_AUD_44K_ERR;
}
/* Enable infra audio */ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); if (ret)
if (ret) { goto err_audio_a2sys;
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret); ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
goto A2SYS_CLK_INFRA_ERR; if (ret)
} goto err_afe_conn;
return 0; return 0;
A2SYS_CLK_INFRA_ERR: err_afe_conn:
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
A2SYS_CLK_AUD_44K_ERR: err_audio_a2sys:
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]); clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
A2SYS_CLK_AUD_MUX2_DIV_ERR: err_audio_a1sys:
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]); clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
A2SYS_CLK_AUD_MUX2_SEL_ERR: err_afe:
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]); clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
err_a2sys:
clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
err_a1sys:
clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
return ret; return ret;
} }
void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe) static void mt2701_afe_disable_audsys(struct mtk_base_afe *afe)
{ {
struct mt2701_afe_private *afe_priv = afe->platform_priv; struct mt2701_afe_private *afe_priv = afe->platform_priv;
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]); clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]); clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]); clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
} }
int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe) int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
{ {
struct mt2701_afe_private *afe_priv = afe->platform_priv;
int ret; int ret;
/* enable INFRA_SYS */ /* Enable audio system */
ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); ret = mt2701_afe_enable_audsys(afe);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
goto AFE_AUD_INFRA_ERR;
}
/* Set MT2701_AUD_AUDINTBUS to MT2701_AUD_SYSPLL1_D4 */
ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[MT2701_AUD_AUDINTBUS], ret);
goto AFE_AUD_AUDINTBUS_ERR;
}
ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUDINTBUS],
afe_priv->clocks[MT2701_AUD_SYSPLL1_D4]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
aud_clks[MT2701_AUD_AUDINTBUS],
aud_clks[MT2701_AUD_SYSPLL1_D4], ret);
goto AFE_AUD_AUDINTBUS_ERR;
}
/* Set MT2701_AUD_ASM_H_SEL to MT2701_AUD_UNIVPLL2_D2 */
ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
if (ret) { if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", dev_err(afe->dev, "failed to enable audio system %d\n", ret);
__func__, aud_clks[MT2701_AUD_ASM_H_SEL], ret); return ret;
goto AFE_AUD_ASM_H_ERR;
}
ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_H_SEL],
afe_priv->clocks[MT2701_AUD_UNIVPLL2_D2]);
if (ret) {
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
aud_clks[MT2701_AUD_ASM_H_SEL],
aud_clks[MT2701_AUD_UNIVPLL2_D2], ret);
goto AFE_AUD_ASM_H_ERR;
}
/* Set MT2701_AUD_ASM_M_SEL to MT2701_AUD_UNIVPLL2_D4 */
ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
if (ret) {
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
__func__, aud_clks[MT2701_AUD_ASM_M_SEL], ret);
goto AFE_AUD_ASM_M_ERR;
} }
ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_M_SEL], regmap_update_bits(afe->regmap, ASYS_TOP_CON,
afe_priv->clocks[MT2701_AUD_UNIVPLL2_D4]); ASYS_TOP_CON_ASYS_TIMING_ON,
if (ret) { ASYS_TOP_CON_ASYS_TIMING_ON);
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__, regmap_update_bits(afe->regmap, AFE_DAC_CON0,
aud_clks[MT2701_AUD_ASM_M_SEL], AFE_DAC_CON0_AFE_ON,
aud_clks[MT2701_AUD_UNIVPLL2_D4], ret); AFE_DAC_CON0_AFE_ON);
goto AFE_AUD_ASM_M_ERR;
}
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, /* Configure ASRC */
AUDIO_TOP_CON0_PDN_AFE, 0); regmap_write(afe->regmap, PWR1_ASM_CON1, PWR1_ASM_CON1_INIT_VAL);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, regmap_write(afe->regmap, PWR2_ASM_CON1, PWR2_ASM_CON1_INIT_VAL);
AUDIO_TOP_CON0_PDN_APLL_CK, 0);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
AUDIO_TOP_CON4_PDN_A1SYS, 0);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
AUDIO_TOP_CON4_PDN_A2SYS, 0);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
AUDIO_TOP_CON4_PDN_AFE_CONN, 0);
return 0; return 0;
AFE_AUD_ASM_M_ERR:
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
AFE_AUD_ASM_H_ERR:
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
AFE_AUD_AUDINTBUS_ERR:
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
AFE_AUD_INFRA_ERR:
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
return ret;
} }
void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe) int mt2701_afe_disable_clock(struct mtk_base_afe *afe)
{ {
struct mt2701_afe_private *afe_priv = afe->platform_priv; regmap_update_bits(afe->regmap, ASYS_TOP_CON,
ASYS_TOP_CON_ASYS_TIMING_ON, 0);
regmap_update_bits(afe->regmap, AFE_DAC_CON0,
AFE_DAC_CON0_AFE_ON, 0);
mt2701_afe_disable_audsys(afe);
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); return 0;
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
AUDIO_TOP_CON0_PDN_AFE, AUDIO_TOP_CON0_PDN_AFE);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
AUDIO_TOP_CON0_PDN_APLL_CK,
AUDIO_TOP_CON0_PDN_APLL_CK);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
AUDIO_TOP_CON4_PDN_A1SYS,
AUDIO_TOP_CON4_PDN_A1SYS);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
AUDIO_TOP_CON4_PDN_A2SYS,
AUDIO_TOP_CON4_PDN_A2SYS);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
AUDIO_TOP_CON4_PDN_AFE_CONN,
AUDIO_TOP_CON4_PDN_AFE_CONN);
} }
void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain, void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
int mclk) int mclk)
{ {
struct mt2701_afe_private *afe_priv = afe->platform_priv; struct mt2701_afe_private *priv = afe->platform_priv;
struct mt2701_i2s_path *i2s_path = &priv->i2s_path[id];
int ret; int ret;
int aud_src_div_id = MT2701_AUD_AUD_K1_SRC_DIV + id;
int aud_src_clk_id = MT2701_AUD_AUD_K1_SRC_SEL + id;
/* Set MCLK Kx_SRC_SEL(domain) */ /* Set mclk source */
ret = clk_prepare_enable(afe_priv->clocks[aud_src_clk_id]); if (domain == 0)
if (ret) ret = clk_set_parent(i2s_path->sel_ck,
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", priv->base_ck[MT2701_TOP_AUD_MCLK_SRC0]);
__func__, aud_clks[aud_src_clk_id], ret); else
ret = clk_set_parent(i2s_path->sel_ck,
if (domain == 0) { priv->base_ck[MT2701_TOP_AUD_MCLK_SRC1]);
ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id],
afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
if (ret)
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[aud_src_clk_id],
aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret);
} else {
ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id],
afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
if (ret)
dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
__func__, aud_clks[aud_src_clk_id],
aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret);
}
clk_disable_unprepare(afe_priv->clocks[aud_src_clk_id]);
/* Set MCLK Kx_SRC_DIV(divider) */
ret = clk_prepare_enable(afe_priv->clocks[aud_src_div_id]);
if (ret) if (ret)
dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", dev_err(afe->dev, "failed to set domain%d mclk source %d\n",
__func__, aud_clks[aud_src_div_id], ret); domain, ret);
ret = clk_set_rate(afe_priv->clocks[aud_src_div_id], mclk); /* Set mclk divider */
ret = clk_set_rate(i2s_path->div_ck, mclk);
if (ret) if (ret)
dev_err(afe->dev, "%s clk_set_rate %s-%d fail %d\n", __func__, dev_err(afe->dev, "failed to set mclk divider %d\n", ret);
aud_clks[aud_src_div_id], mclk, ret);
clk_disable_unprepare(afe_priv->clocks[aud_src_div_id]);
} }
MODULE_DESCRIPTION("MT2701 afe clock control");
MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
MODULE_LICENSE("GPL v2");
sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h
View file @ 3116e748
...@@ -21,16 +21,15 @@ struct mtk_base_afe; ...@@ -21,16 +21,15 @@ struct mtk_base_afe;
int mt2701_init_clock(struct mtk_base_afe *afe); int mt2701_init_clock(struct mtk_base_afe *afe);
int mt2701_afe_enable_clock(struct mtk_base_afe *afe); int mt2701_afe_enable_clock(struct mtk_base_afe *afe);
void mt2701_afe_disable_clock(struct mtk_base_afe *afe); int mt2701_afe_disable_clock(struct mtk_base_afe *afe);
int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe); int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir);
void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe); void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir);
int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id);
void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id);
int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe); int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe);
void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe); void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe);
int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe);
void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe);
void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain, void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
int mclk); int mclk);
......
sound/soc/mediatek/mt2701/mt2701-afe-common.h
View file @ 3116e748
...@@ -16,6 +16,7 @@ ...@@ -16,6 +16,7 @@
#ifndef _MT_2701_AFE_COMMON_H_ #ifndef _MT_2701_AFE_COMMON_H_
#define _MT_2701_AFE_COMMON_H_ #define _MT_2701_AFE_COMMON_H_
#include <sound/soc.h> #include <sound/soc.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/regmap.h> #include <linux/regmap.h>
...@@ -25,16 +26,7 @@ ...@@ -25,16 +26,7 @@
#define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1) #define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1)
#define MT2701_PLL_DOMAIN_0_RATE 98304000 #define MT2701_PLL_DOMAIN_0_RATE 98304000
#define MT2701_PLL_DOMAIN_1_RATE 90316800 #define MT2701_PLL_DOMAIN_1_RATE 90316800
#define MT2701_AUD_AUD_MUX1_DIV_RATE (MT2701_PLL_DOMAIN_0_RATE / 2) #define MT2701_I2S_NUM 4
#define MT2701_AUD_AUD_MUX2_DIV_RATE (MT2701_PLL_DOMAIN_1_RATE / 2)
enum {
MT2701_I2S_1,
MT2701_I2S_2,
MT2701_I2S_3,
MT2701_I2S_4,
MT2701_I2S_NUM,
};
enum { enum {
MT2701_MEMIF_DL1, MT2701_MEMIF_DL1,
...@@ -62,60 +54,23 @@ enum { ...@@ -62,60 +54,23 @@ enum {
}; };
enum { enum {
MT2701_IRQ_ASYS_START, MT2701_IRQ_ASYS_IRQ1,
MT2701_IRQ_ASYS_IRQ1 = MT2701_IRQ_ASYS_START,
MT2701_IRQ_ASYS_IRQ2, MT2701_IRQ_ASYS_IRQ2,
MT2701_IRQ_ASYS_IRQ3, MT2701_IRQ_ASYS_IRQ3,
MT2701_IRQ_ASYS_END, MT2701_IRQ_ASYS_END,
}; };
/* 2701 clock def */ enum audio_base_clock {
enum audio_system_clock_type { MT2701_INFRA_SYS_AUDIO,
MT2701_AUD_INFRA_SYS_AUDIO, MT2701_TOP_AUD_MCLK_SRC0,
MT2701_AUD_AUD_MUX1_SEL, MT2701_TOP_AUD_MCLK_SRC1,
MT2701_AUD_AUD_MUX2_SEL, MT2701_TOP_AUD_A1SYS,
MT2701_AUD_AUD_MUX1_DIV, MT2701_TOP_AUD_A2SYS,
MT2701_AUD_AUD_MUX2_DIV, MT2701_AUDSYS_AFE,
MT2701_AUD_AUD_48K_TIMING, MT2701_AUDSYS_AFE_CONN,
MT2701_AUD_AUD_44K_TIMING, MT2701_AUDSYS_A1SYS,
MT2701_AUD_AUDPLL_MUX_SEL, MT2701_AUDSYS_A2SYS,
MT2701_AUD_APLL_SEL, MT2701_BASE_CLK_NUM,
MT2701_AUD_AUD1PLL_98M,
MT2701_AUD_AUD2PLL_90M,
MT2701_AUD_HADDS2PLL_98M,
MT2701_AUD_HADDS2PLL_294M,
MT2701_AUD_AUDPLL,
MT2701_AUD_AUDPLL_D4,
MT2701_AUD_AUDPLL_D8,
MT2701_AUD_AUDPLL_D16,
MT2701_AUD_AUDPLL_D24,
MT2701_AUD_AUDINTBUS,
MT2701_AUD_CLK_26M,
MT2701_AUD_SYSPLL1_D4,
MT2701_AUD_AUD_K1_SRC_SEL,
MT2701_AUD_AUD_K2_SRC_SEL,
MT2701_AUD_AUD_K3_SRC_SEL,
MT2701_AUD_AUD_K4_SRC_SEL,
MT2701_AUD_AUD_K5_SRC_SEL,
MT2701_AUD_AUD_K6_SRC_SEL,
MT2701_AUD_AUD_K1_SRC_DIV,
MT2701_AUD_AUD_K2_SRC_DIV,
MT2701_AUD_AUD_K3_SRC_DIV,
MT2701_AUD_AUD_K4_SRC_DIV,
MT2701_AUD_AUD_K5_SRC_DIV,
MT2701_AUD_AUD_K6_SRC_DIV,
MT2701_AUD_AUD_I2S1_MCLK,
MT2701_AUD_AUD_I2S2_MCLK,
MT2701_AUD_AUD_I2S3_MCLK,
MT2701_AUD_AUD_I2S4_MCLK,
MT2701_AUD_AUD_I2S5_MCLK,
MT2701_AUD_AUD_I2S6_MCLK,
MT2701_AUD_ASM_M_SEL,
MT2701_AUD_ASM_H_SEL,
MT2701_AUD_UNIVPLL2_D4,
MT2701_AUD_UNIVPLL2_D2,
MT2701_AUD_SYSPLL_D5,
MT2701_CLOCK_NUM
}; };
static const unsigned int mt2701_afe_backup_list[] = { static const unsigned int mt2701_afe_backup_list[] = {
...@@ -139,12 +94,8 @@ static const unsigned int mt2701_afe_backup_list[] = { ...@@ -139,12 +94,8 @@ static const unsigned int mt2701_afe_backup_list[] = {
AFE_MEMIF_PBUF_SIZE, AFE_MEMIF_PBUF_SIZE,
}; };
struct snd_pcm_substream;
struct mtk_base_irq_data;
struct mt2701_i2s_data { struct mt2701_i2s_data {
int i2s_ctrl_reg; int i2s_ctrl_reg;
int i2s_pwn_shift;
int i2s_asrc_fs_shift; int i2s_asrc_fs_shift;
int i2s_asrc_fs_mask; int i2s_asrc_fs_mask;
}; };
...@@ -160,12 +111,18 @@ struct mt2701_i2s_path { ...@@ -160,12 +111,18 @@ struct mt2701_i2s_path {
int mclk_rate; int mclk_rate;
int on[I2S_DIR_NUM]; int on[I2S_DIR_NUM];
int occupied[I2S_DIR_NUM]; int occupied[I2S_DIR_NUM];
const struct mt2701_i2s_data *i2s_data[2]; const struct mt2701_i2s_data *i2s_data[I2S_DIR_NUM];
struct clk *hop_ck[I2S_DIR_NUM];
struct clk *sel_ck;
struct clk *div_ck;
struct clk *mclk_ck;
struct clk *asrco_ck;
}; };
struct mt2701_afe_private { struct mt2701_afe_private {
struct clk *clocks[MT2701_CLOCK_NUM];
struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM]; struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM];
struct clk *base_ck[MT2701_BASE_CLK_NUM];
struct clk *mrgif_ck;
bool mrg_enable[MT2701_STREAM_DIR_NUM]; bool mrg_enable[MT2701_STREAM_DIR_NUM];
}; };
......
sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
View file @ 3116e748
...@@ -17,19 +17,16 @@ ...@@ -17,19 +17,16 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <sound/soc.h>
#include "mt2701-afe-common.h" #include "mt2701-afe-common.h"
#include "mt2701-afe-clock-ctrl.h" #include "mt2701-afe-clock-ctrl.h"
#include "../common/mtk-afe-platform-driver.h" #include "../common/mtk-afe-platform-driver.h"
#include "../common/mtk-afe-fe-dai.h" #include "../common/mtk-afe-fe-dai.h"
#define AFE_IRQ_STATUS_BITS 0xff
static const struct snd_pcm_hardware mt2701_afe_hardware = { static const struct snd_pcm_hardware mt2701_afe_hardware = {
.info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED
| SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID, | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID,
...@@ -97,40 +94,26 @@ static int mt2701_afe_i2s_startup(struct snd_pcm_substream *substream, ...@@ -97,40 +94,26 @@ static int mt2701_afe_i2s_startup(struct snd_pcm_substream *substream,
{ {
struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
struct mt2701_afe_private *afe_priv = afe->platform_priv;
int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
int clk_num = MT2701_AUD_AUD_I2S1_MCLK + i2s_num;
int ret = 0;
if (i2s_num < 0) if (i2s_num < 0)
return i2s_num; return i2s_num;
/* enable mclk */ return mt2701_afe_enable_mclk(afe, i2s_num);
ret = clk_prepare_enable(afe_priv->clocks[clk_num]);
if (ret)
dev_err(afe->dev, "Failed to enable mclk for I2S: %d\n",
i2s_num);
return ret;
} }
static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream, static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai, struct snd_soc_dai *dai,
int i2s_num,
int dir_invert) int dir_invert)
{ {
struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
struct mt2701_afe_private *afe_priv = afe->platform_priv; struct mt2701_afe_private *afe_priv = afe->platform_priv;
int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
struct mt2701_i2s_path *i2s_path;
const struct mt2701_i2s_data *i2s_data; const struct mt2701_i2s_data *i2s_data;
int stream_dir = substream->stream; int stream_dir = substream->stream;
if (i2s_num < 0)
return i2s_num;
i2s_path = &afe_priv->i2s_path[i2s_num];
if (dir_invert) { if (dir_invert) {
if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
stream_dir = SNDRV_PCM_STREAM_CAPTURE; stream_dir = SNDRV_PCM_STREAM_CAPTURE;
...@@ -151,9 +134,9 @@ static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream, ...@@ -151,9 +134,9 @@ static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream,
/* disable i2s */ /* disable i2s */
regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
ASYS_I2S_CON_I2S_EN, 0); ASYS_I2S_CON_I2S_EN, 0);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
1 << i2s_data->i2s_pwn_shift, mt2701_afe_disable_i2s(afe, i2s_num, stream_dir);
1 << i2s_data->i2s_pwn_shift);
return 0; return 0;
} }
...@@ -165,7 +148,6 @@ static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream, ...@@ -165,7 +148,6 @@ static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
struct mt2701_afe_private *afe_priv = afe->platform_priv; struct mt2701_afe_private *afe_priv = afe->platform_priv;
int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
struct mt2701_i2s_path *i2s_path; struct mt2701_i2s_path *i2s_path;
int clk_num = MT2701_AUD_AUD_I2S1_MCLK + i2s_num;
if (i2s_num < 0) if (i2s_num < 0)
return; return;
...@@ -177,37 +159,32 @@ static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream, ...@@ -177,37 +159,32 @@ static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
else else
goto I2S_UNSTART; goto I2S_UNSTART;
mt2701_afe_i2s_path_shutdown(substream, dai, 0); mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 0);
/* need to disable i2s-out path when disable i2s-in */ /* need to disable i2s-out path when disable i2s-in */
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
mt2701_afe_i2s_path_shutdown(substream, dai, 1); mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 1);
I2S_UNSTART: I2S_UNSTART:
/* disable mclk */ /* disable mclk */
clk_disable_unprepare(afe_priv->clocks[clk_num]); mt2701_afe_disable_mclk(afe, i2s_num);
} }
static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream, static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai, struct snd_soc_dai *dai,
int i2s_num,
int dir_invert) int dir_invert)
{ {
struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
struct mt2701_afe_private *afe_priv = afe->platform_priv; struct mt2701_afe_private *afe_priv = afe->platform_priv;
int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
struct mt2701_i2s_path *i2s_path;
const struct mt2701_i2s_data *i2s_data; const struct mt2701_i2s_data *i2s_data;
struct snd_pcm_runtime * const runtime = substream->runtime; struct snd_pcm_runtime * const runtime = substream->runtime;
int reg, fs, w_len = 1; /* now we support bck 64bits only */ int reg, fs, w_len = 1; /* now we support bck 64bits only */
int stream_dir = substream->stream; int stream_dir = substream->stream;
unsigned int mask = 0, val = 0; unsigned int mask = 0, val = 0;
if (i2s_num < 0)
return i2s_num;
i2s_path = &afe_priv->i2s_path[i2s_num];
if (dir_invert) { if (dir_invert) {
if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
stream_dir = SNDRV_PCM_STREAM_CAPTURE; stream_dir = SNDRV_PCM_STREAM_CAPTURE;
...@@ -251,9 +228,7 @@ static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream, ...@@ -251,9 +228,7 @@ static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream,
fs << i2s_data->i2s_asrc_fs_shift); fs << i2s_data->i2s_asrc_fs_shift);
/* enable i2s */ /* enable i2s */
regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, mt2701_afe_enable_i2s(afe, i2s_num, stream_dir);
1 << i2s_data->i2s_pwn_shift,
0 << i2s_data->i2s_pwn_shift);
/* reset i2s hw status before enable */ /* reset i2s hw status before enable */
regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
...@@ -300,13 +275,13 @@ static int mt2701_afe_i2s_prepare(struct snd_pcm_substream *substream, ...@@ -300,13 +275,13 @@ static int mt2701_afe_i2s_prepare(struct snd_pcm_substream *substream,
mt2701_mclk_configuration(afe, i2s_num, clk_domain, mclk_rate); mt2701_mclk_configuration(afe, i2s_num, clk_domain, mclk_rate);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
mt2701_i2s_path_prepare_enable(substream, dai, 0); mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
} else { } else {
/* need to enable i2s-out path when enable i2s-in */ /* need to enable i2s-out path when enable i2s-in */
/* prepare for another direction "out" */ /* prepare for another direction "out" */
mt2701_i2s_path_prepare_enable(substream, dai, 1); mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 1);
/* prepare for "in" */ /* prepare for "in" */
mt2701_i2s_path_prepare_enable(substream, dai, 0); mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
} }
return 0; return 0;
...@@ -339,9 +314,11 @@ static int mt2701_btmrg_startup(struct snd_pcm_substream *substream, ...@@ -339,9 +314,11 @@ static int mt2701_btmrg_startup(struct snd_pcm_substream *substream,
struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
struct mt2701_afe_private *afe_priv = afe->platform_priv; struct mt2701_afe_private *afe_priv = afe->platform_priv;
int ret;
regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, ret = mt2701_enable_btmrg_clk(afe);
AUDIO_TOP_CON4_PDN_MRGIF, 0); if (ret)
return ret;
afe_priv->mrg_enable[substream->stream] = 1; afe_priv->mrg_enable[substream->stream] = 1;
return 0; return 0;
...@@ -406,9 +383,7 @@ static void mt2701_btmrg_shutdown(struct snd_pcm_substream *substream, ...@@ -406,9 +383,7 @@ static void mt2701_btmrg_shutdown(struct snd_pcm_substream *substream,
AFE_MRGIF_CON_MRG_EN, 0); AFE_MRGIF_CON_MRG_EN, 0);
regmap_update_bits(afe->regmap, AFE_MRGIF_CON, regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
AFE_MRGIF_CON_MRG_I2S_EN, 0); AFE_MRGIF_CON_MRG_I2S_EN, 0);
regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, mt2701_disable_btmrg_clk(afe);
AUDIO_TOP_CON4_PDN_MRGIF,
AUDIO_TOP_CON4_PDN_MRGIF);
} }
afe_priv->mrg_enable[substream->stream] = 0; afe_priv->mrg_enable[substream->stream] = 0;
} }
...@@ -574,7 +549,6 @@ static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops = { ...@@ -574,7 +549,6 @@ static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops = {
.hw_free = mtk_afe_fe_hw_free, .hw_free = mtk_afe_fe_hw_free,
.prepare = mtk_afe_fe_prepare, .prepare = mtk_afe_fe_prepare,
.trigger = mtk_afe_fe_trigger, .trigger = mtk_afe_fe_trigger,
}; };
static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = { static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = {
...@@ -915,31 +889,6 @@ static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s4[] = { ...@@ -915,31 +889,6 @@ static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s4[] = {
PWR2_TOP_CON, 19, 1, 0), PWR2_TOP_CON, 19, 1, 0),
}; };
static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc0[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Asrc0 out Switch", AUDIO_TOP_CON4, 14, 1,
1),
};
static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc1[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Asrc1 out Switch", AUDIO_TOP_CON4, 15, 1,
1),
};
static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc2[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Asrc2 out Switch", PWR2_TOP_CON, 6, 1,
1),
};
static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc3[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Asrc3 out Switch", PWR2_TOP_CON, 7, 1,
1),
};
static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc4[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Asrc4 out Switch", PWR2_TOP_CON, 8, 1,
1),
};
static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = { static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
/* inter-connections */ /* inter-connections */
SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0), SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
...@@ -999,19 +948,6 @@ static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = { ...@@ -999,19 +948,6 @@ static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0, SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0,
mt2701_afe_multi_ch_out_i2s3, mt2701_afe_multi_ch_out_i2s3,
ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)), ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)),
SND_SOC_DAPM_MIXER("ASRC_O0", SND_SOC_NOPM, 0, 0,
mt2701_afe_multi_ch_out_asrc0,
ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc0)),
SND_SOC_DAPM_MIXER("ASRC_O1", SND_SOC_NOPM, 0, 0,
mt2701_afe_multi_ch_out_asrc1,
ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc1)),
SND_SOC_DAPM_MIXER("ASRC_O2", SND_SOC_NOPM, 0, 0,
mt2701_afe_multi_ch_out_asrc2,
ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc2)),
SND_SOC_DAPM_MIXER("ASRC_O3", SND_SOC_NOPM, 0, 0,
mt2701_afe_multi_ch_out_asrc3,
ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc3)),
}; };
static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = { static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
...@@ -1021,7 +957,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = { ...@@ -1021,7 +957,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
{"I2S0 Playback", NULL, "O15"}, {"I2S0 Playback", NULL, "O15"},
{"I2S0 Playback", NULL, "O16"}, {"I2S0 Playback", NULL, "O16"},
{"I2S1 Playback", NULL, "O17"}, {"I2S1 Playback", NULL, "O17"},
{"I2S1 Playback", NULL, "O18"}, {"I2S1 Playback", NULL, "O18"},
{"I2S2 Playback", NULL, "O19"}, {"I2S2 Playback", NULL, "O19"},
...@@ -1038,7 +973,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = { ...@@ -1038,7 +973,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
{"I00", NULL, "I2S0 Capture"}, {"I00", NULL, "I2S0 Capture"},
{"I01", NULL, "I2S0 Capture"}, {"I01", NULL, "I2S0 Capture"},
{"I02", NULL, "I2S1 Capture"}, {"I02", NULL, "I2S1 Capture"},
{"I03", NULL, "I2S1 Capture"}, {"I03", NULL, "I2S1 Capture"},
/* I02,03 link to UL2, also need to open I2S0 */ /* I02,03 link to UL2, also need to open I2S0 */
...@@ -1046,15 +980,10 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = { ...@@ -1046,15 +980,10 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
{"I26", NULL, "BT Capture"}, {"I26", NULL, "BT Capture"},
{"ASRC_O0", "Asrc0 out Switch", "DLM"}, {"I12I13", "Multich I2S0 Out Switch", "DLM"},
{"ASRC_O1", "Asrc1 out Switch", "DLM"}, {"I14I15", "Multich I2S1 Out Switch", "DLM"},
{"ASRC_O2", "Asrc2 out Switch", "DLM"}, {"I16I17", "Multich I2S2 Out Switch", "DLM"},
{"ASRC_O3", "Asrc3 out Switch", "DLM"}, {"I18I19", "Multich I2S3 Out Switch", "DLM"},
{"I12I13", "Multich I2S0 Out Switch", "ASRC_O0"},
{"I14I15", "Multich I2S1 Out Switch", "ASRC_O1"},
{"I16I17", "Multich I2S2 Out Switch", "ASRC_O2"},
{"I18I19", "Multich I2S3 Out Switch", "ASRC_O3"},
{ "I12", NULL, "I12I13" }, { "I12", NULL, "I12I13" },
{ "I13", NULL, "I12I13" }, { "I13", NULL, "I12I13" },
...@@ -1079,7 +1008,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = { ...@@ -1079,7 +1008,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
{ "O21", "I18 Switch", "I18" }, { "O21", "I18 Switch", "I18" },
{ "O22", "I19 Switch", "I19" }, { "O22", "I19 Switch", "I19" },
{ "O31", "I35 Switch", "I35" }, { "O31", "I35 Switch", "I35" },
}; };
static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = { static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = {
...@@ -1386,14 +1314,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = { ...@@ -1386,14 +1314,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
{ {
{ {
.i2s_ctrl_reg = ASYS_I2SO1_CON, .i2s_ctrl_reg = ASYS_I2SO1_CON,
.i2s_pwn_shift = 6,
.i2s_asrc_fs_shift = 0, .i2s_asrc_fs_shift = 0,
.i2s_asrc_fs_mask = 0x1f, .i2s_asrc_fs_mask = 0x1f,
}, },
{ {
.i2s_ctrl_reg = ASYS_I2SIN1_CON, .i2s_ctrl_reg = ASYS_I2SIN1_CON,
.i2s_pwn_shift = 0,
.i2s_asrc_fs_shift = 0, .i2s_asrc_fs_shift = 0,
.i2s_asrc_fs_mask = 0x1f, .i2s_asrc_fs_mask = 0x1f,
...@@ -1402,14 +1328,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = { ...@@ -1402,14 +1328,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
{ {
{ {
.i2s_ctrl_reg = ASYS_I2SO2_CON, .i2s_ctrl_reg = ASYS_I2SO2_CON,
.i2s_pwn_shift = 7,
.i2s_asrc_fs_shift = 5, .i2s_asrc_fs_shift = 5,
.i2s_asrc_fs_mask = 0x1f, .i2s_asrc_fs_mask = 0x1f,
}, },
{ {
.i2s_ctrl_reg = ASYS_I2SIN2_CON, .i2s_ctrl_reg = ASYS_I2SIN2_CON,
.i2s_pwn_shift = 1,
.i2s_asrc_fs_shift = 5, .i2s_asrc_fs_shift = 5,
.i2s_asrc_fs_mask = 0x1f, .i2s_asrc_fs_mask = 0x1f,
...@@ -1418,14 +1342,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = { ...@@ -1418,14 +1342,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
{ {
{ {
.i2s_ctrl_reg = ASYS_I2SO3_CON, .i2s_ctrl_reg = ASYS_I2SO3_CON,
.i2s_pwn_shift = 8,
.i2s_asrc_fs_shift = 10, .i2s_asrc_fs_shift = 10,
.i2s_asrc_fs_mask = 0x1f, .i2s_asrc_fs_mask = 0x1f,
}, },
{ {
.i2s_ctrl_reg = ASYS_I2SIN3_CON, .i2s_ctrl_reg = ASYS_I2SIN3_CON,
.i2s_pwn_shift = 2,
.i2s_asrc_fs_shift = 10, .i2s_asrc_fs_shift = 10,
.i2s_asrc_fs_mask = 0x1f, .i2s_asrc_fs_mask = 0x1f,
...@@ -1434,14 +1356,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = { ...@@ -1434,14 +1356,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
{ {
{ {
.i2s_ctrl_reg = ASYS_I2SO4_CON, .i2s_ctrl_reg = ASYS_I2SO4_CON,
.i2s_pwn_shift = 9,
.i2s_asrc_fs_shift = 15, .i2s_asrc_fs_shift = 15,
.i2s_asrc_fs_mask = 0x1f, .i2s_asrc_fs_mask = 0x1f,
}, },
{ {
.i2s_ctrl_reg = ASYS_I2SIN4_CON, .i2s_ctrl_reg = ASYS_I2SIN4_CON,
.i2s_pwn_shift = 3,
.i2s_asrc_fs_shift = 15, .i2s_asrc_fs_shift = 15,
.i2s_asrc_fs_mask = 0x1f, .i2s_asrc_fs_mask = 0x1f,
...@@ -1449,14 +1369,6 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = { ...@@ -1449,14 +1369,6 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
}, },
}; };
static const struct regmap_config mt2701_afe_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = AFE_END_ADDR,
.cache_type = REGCACHE_NONE,
};
static irqreturn_t mt2701_asys_isr(int irq_id, void *dev) static irqreturn_t mt2701_asys_isr(int irq_id, void *dev)
{ {
int id; int id;
...@@ -1483,8 +1395,7 @@ static int mt2701_afe_runtime_suspend(struct device *dev) ...@@ -1483,8 +1395,7 @@ static int mt2701_afe_runtime_suspend(struct device *dev)
{ {
struct mtk_base_afe *afe = dev_get_drvdata(dev); struct mtk_base_afe *afe = dev_get_drvdata(dev);
mt2701_afe_disable_clock(afe); return mt2701_afe_disable_clock(afe);
return 0;
} }
static int mt2701_afe_runtime_resume(struct device *dev) static int mt2701_afe_runtime_resume(struct device *dev)
...@@ -1496,21 +1407,22 @@ static int mt2701_afe_runtime_resume(struct device *dev) ...@@ -1496,21 +1407,22 @@ static int mt2701_afe_runtime_resume(struct device *dev)
static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev) static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
{ {
struct snd_soc_component *component;
struct mtk_base_afe *afe; struct mtk_base_afe *afe;
struct mt2701_afe_private *afe_priv; struct mt2701_afe_private *afe_priv;
struct resource *res;
struct device *dev; struct device *dev;
int i, irq_id, ret; int i, irq_id, ret;
afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
if (!afe) if (!afe)
return -ENOMEM; return -ENOMEM;
afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
GFP_KERNEL); GFP_KERNEL);
if (!afe->platform_priv) if (!afe->platform_priv)
return -ENOMEM; return -ENOMEM;
afe_priv = afe->platform_priv;
afe_priv = afe->platform_priv;
afe->dev = &pdev->dev; afe->dev = &pdev->dev;
dev = afe->dev; dev = afe->dev;
...@@ -1527,17 +1439,11 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev) ...@@ -1527,17 +1439,11 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
return ret; return ret;
} }
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
if (!afe->regmap) {
afe->base_addr = devm_ioremap_resource(&pdev->dev, res); dev_err(dev, "could not get regmap from parent\n");
return -ENODEV;
if (IS_ERR(afe->base_addr)) }
return PTR_ERR(afe->base_addr);
afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
&mt2701_afe_regmap_config);
if (IS_ERR(afe->regmap))
return PTR_ERR(afe->regmap);
mutex_init(&afe->irq_alloc_lock); mutex_init(&afe->irq_alloc_lock);
...@@ -1545,7 +1451,6 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev) ...@@ -1545,7 +1451,6 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
afe->memif_size = MT2701_MEMIF_NUM; afe->memif_size = MT2701_MEMIF_NUM;
afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
GFP_KERNEL); GFP_KERNEL);
if (!afe->memif) if (!afe->memif)
return -ENOMEM; return -ENOMEM;
...@@ -1558,7 +1463,6 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev) ...@@ -1558,7 +1463,6 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
afe->irqs_size = MT2701_IRQ_ASYS_END; afe->irqs_size = MT2701_IRQ_ASYS_END;
afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
GFP_KERNEL); GFP_KERNEL);
if (!afe->irqs) if (!afe->irqs)
return -ENOMEM; return -ENOMEM;
...@@ -1573,10 +1477,15 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev) ...@@ -1573,10 +1477,15 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
= &mt2701_i2s_data[i][I2S_IN]; = &mt2701_i2s_data[i][I2S_IN];
} }
component = kzalloc(sizeof(*component), GFP_KERNEL);
if (!component)
return -ENOMEM;
component->regmap = afe->regmap;
afe->mtk_afe_hardware = &mt2701_afe_hardware; afe->mtk_afe_hardware = &mt2701_afe_hardware;
afe->memif_fs = mt2701_memif_fs; afe->memif_fs = mt2701_memif_fs;
afe->irq_fs = mt2701_irq_fs; afe->irq_fs = mt2701_irq_fs;
afe->reg_back_up_list = mt2701_afe_backup_list; afe->reg_back_up_list = mt2701_afe_backup_list;
afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list); afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list);
afe->runtime_resume = mt2701_afe_runtime_resume; afe->runtime_resume = mt2701_afe_runtime_resume;
...@@ -1586,7 +1495,7 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev) ...@@ -1586,7 +1495,7 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
ret = mt2701_init_clock(afe); ret = mt2701_init_clock(afe);
if (ret) { if (ret) {
dev_err(dev, "init clock error\n"); dev_err(dev, "init clock error\n");
return ret; goto err_init_clock;
} }
platform_set_drvdata(pdev, afe); platform_set_drvdata(pdev, afe);
...@@ -1605,10 +1514,10 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev) ...@@ -1605,10 +1514,10 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
goto err_platform; goto err_platform;
} }
ret = snd_soc_register_component(&pdev->dev, ret = snd_soc_add_component(dev, component,
&mt2701_afe_pcm_dai_component, &mt2701_afe_pcm_dai_component,
mt2701_afe_pcm_dais, mt2701_afe_pcm_dais,
ARRAY_SIZE(mt2701_afe_pcm_dais)); ARRAY_SIZE(mt2701_afe_pcm_dais));
if (ret) { if (ret) {
dev_warn(dev, "err_dai_component\n"); dev_warn(dev, "err_dai_component\n");
goto err_dai_component; goto err_dai_component;
...@@ -1622,6 +1531,8 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev) ...@@ -1622,6 +1531,8 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
pm_runtime_put_sync(dev); pm_runtime_put_sync(dev);
err_pm_disable: err_pm_disable:
pm_runtime_disable(dev); pm_runtime_disable(dev);
err_init_clock:
kfree(component);
return ret; return ret;
} }
...@@ -1667,4 +1578,3 @@ module_platform_driver(mt2701_afe_pcm_driver); ...@@ -1667,4 +1578,3 @@ module_platform_driver(mt2701_afe_pcm_driver);
MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701"); MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>"); MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");
sound/soc/mediatek/mt2701/mt2701-reg.h
View file @ 3116e748
...@@ -17,17 +17,6 @@ ...@@ -17,17 +17,6 @@
#ifndef _MT2701_REG_H_ #ifndef _MT2701_REG_H_
#define _MT2701_REG_H_ #define _MT2701_REG_H_
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
#include <sound/soc.h>
#include "mt2701-afe-common.h"
/*****************************************************************************
* R E G I S T E R D E F I N I T I O N
*****************************************************************************/
#define AUDIO_TOP_CON0 0x0000 #define AUDIO_TOP_CON0 0x0000
#define AUDIO_TOP_CON4 0x0010 #define AUDIO_TOP_CON4 0x0010
#define AUDIO_TOP_CON5 0x0014 #define AUDIO_TOP_CON5 0x0014
...@@ -109,18 +98,6 @@ ...@@ -109,18 +98,6 @@
#define AFE_DAI_BASE 0x1370 #define AFE_DAI_BASE 0x1370
#define AFE_DAI_CUR 0x137c #define AFE_DAI_CUR 0x137c
/* AUDIO_TOP_CON0 (0x0000) */
#define AUDIO_TOP_CON0_A1SYS_A2SYS_ON (0x3 << 0)
#define AUDIO_TOP_CON0_PDN_AFE (0x1 << 2)
#define AUDIO_TOP_CON0_PDN_APLL_CK (0x1 << 23)
/* AUDIO_TOP_CON4 (0x0010) */
#define AUDIO_TOP_CON4_I2SO1_PWN (0x1 << 6)
#define AUDIO_TOP_CON4_PDN_A1SYS (0x1 << 21)
#define AUDIO_TOP_CON4_PDN_A2SYS (0x1 << 22)
#define AUDIO_TOP_CON4_PDN_AFE_CONN (0x1 << 23)
#define AUDIO_TOP_CON4_PDN_MRGIF (0x1 << 25)
/* AFE_DAIBT_CON0 (0x001c) */ /* AFE_DAIBT_CON0 (0x001c) */
#define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0) #define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0)
#define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1) #define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1)
...@@ -137,22 +114,8 @@ ...@@ -137,22 +114,8 @@
#define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20) #define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20)
#define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20) #define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20)
/* ASYS_I2SO1_CON (0x061c) */ /* ASYS_TOP_CON (0x0600) */
#define ASYS_I2SO1_CON_FS (0x1f << 8) #define ASYS_TOP_CON_ASYS_TIMING_ON (0x3 << 0)
#define ASYS_I2SO1_CON_FS_SET(x) ((x) << 8)
#define ASYS_I2SO1_CON_MULTI_CH (0x1 << 16)
#define ASYS_I2SO1_CON_SIDEGEN (0x1 << 30)
#define ASYS_I2SO1_CON_I2S_EN (0x1 << 0)
/* 0:EIAJ 1:I2S */
#define ASYS_I2SO1_CON_I2S_MODE (0x1 << 3)
#define ASYS_I2SO1_CON_WIDE_MODE (0x1 << 1)
#define ASYS_I2SO1_CON_WIDE_MODE_SET(x) ((x) << 1)
/* PWR2_TOP_CON (0x0634) */
#define PWR2_TOP_CON_INIT_VAL (0xffe1ffff)
/* ASYS_IRQ_CLR (0x07c0) */
#define ASYS_IRQ_CLR_ALL (0xffffffff)
/* PWR2_ASM_CON1 (0x1070) */ /* PWR2_ASM_CON1 (0x1070) */
#define PWR2_ASM_CON1_INIT_VAL (0x492492) #define PWR2_ASM_CON1_INIT_VAL (0x492492)
...@@ -182,5 +145,4 @@ ...@@ -182,5 +145,4 @@
#define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1) #define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1)
#define ASYS_I2S_IN_PHASE_FIX (0x1 << 31) #define ASYS_I2S_IN_PHASE_FIX (0x1 << 31)
#define AFE_END_ADDR 0x15e0
#endif #endif
sound/soc/mediatek/mt8173/mt8173-afe-pcm.c
View file @ 3116e748
...@@ -1083,7 +1083,7 @@ static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe) ...@@ -1083,7 +1083,7 @@ static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe)
static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev) static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev)
{ {
int ret, i; int ret, i;
unsigned int irq_id; int irq_id;
struct mtk_base_afe *afe; struct mtk_base_afe *afe;
struct mt8173_afe_private *afe_priv; struct mt8173_afe_private *afe_priv;
struct resource *res; struct resource *res;
...@@ -1105,9 +1105,9 @@ static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev) ...@@ -1105,9 +1105,9 @@ static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev)
afe->dev = &pdev->dev; afe->dev = &pdev->dev;
irq_id = platform_get_irq(pdev, 0); irq_id = platform_get_irq(pdev, 0);
if (!irq_id) { if (irq_id <= 0) {
dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name); dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name);
return -ENXIO; return irq_id < 0 ? irq_id : -ENXIO;
} }
ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler, ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler,
0, "Afe_ISR_Handle", (void *)afe); 0, "Afe_ISR_Handle", (void *)afe);
......
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