[CPUFREQ] Lots of whitespace & CodingStyle cleanup.

Signed-off-by: Dave Jones <davej@redhat.com>

arch/i386/kernel/cpu/cpufreq/Kconfig

@@ -96,7 +96,6 @@ config X86_POWERNOW_K8_ACPI
 
 config X86_GX_SUSPMOD
 	tristate "Cyrix MediaGX/NatSemi Geode Suspend Modulation"
-	depends on PCI
 	help
 	 This add the CPUFreq driver for NatSemi Geode processors which
 	 support suspend modulation.

arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c

@@ -57,7 +57,7 @@ MODULE_PARM_DESC(min_fsb,
 
 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-nforce2", msg)
 
-/*
+/**
  * nforce2_calc_fsb - calculate FSB
  * @pll: PLL value
  *
@@ -76,7 +76,7 @@ static int nforce2_calc_fsb(int pll)
 	return 0;
 }
 
-/*
+/**
  * nforce2_calc_pll - calculate PLL value
  * @fsb: FSB
  *
@@ -106,7 +106,7 @@ static int nforce2_calc_pll(unsigned int fsb)
 	return NFORCE2_PLL(mul, div);
 }
 
-/*
+/**
  * nforce2_write_pll - write PLL value to chipset
  * @pll: PLL value
  *
@@ -121,15 +121,13 @@ static void nforce2_write_pll(int pll)
 	pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp);
 
 	/* Now write the value in all 64 registers */
-	for (temp = 0; temp <= 0x3f; temp++) {
-		pci_write_config_dword(nforce2_chipset_dev, 
-                                       NFORCE2_PLLREG, pll);
-	}
+	for (temp = 0; temp <= 0x3f; temp++)
+		pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLREG, pll);
 
 	return;
 }
 
-/*
+/**
  * nforce2_fsb_read - Read FSB
  *
  *   Read FSB from chipset
@@ -140,14 +138,9 @@ static unsigned int nforce2_fsb_read(int bootfsb)
 	struct pci_dev *nforce2_sub5;
 	u32 fsb, temp = 0;
 
-	
 	/* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
 	nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
-                                      0x01EF,
-                                      PCI_ANY_ID,
-                                      PCI_ANY_ID,
-                                      NULL);
-	
+						0x01EF,PCI_ANY_ID,PCI_ANY_ID,NULL);
 	if (!nforce2_sub5)
 		return 0;
 
@@ -155,21 +148,19 @@ static unsigned int nforce2_fsb_read(int bootfsb)
 	fsb /= 1000000;
 
 	/* Check if PLL register is already set */
-	pci_read_config_byte(nforce2_chipset_dev, 
-                             NFORCE2_PLLENABLE, (u8 *)&temp);
+	pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
 
 	if(bootfsb || !temp)
 		return fsb;
 		
 	/* Use PLL register FSB value */
-	pci_read_config_dword(nforce2_chipset_dev, 
-                              NFORCE2_PLLREG, &temp);
+	pci_read_config_dword(nforce2_chipset_dev,NFORCE2_PLLREG, &temp);
 	fsb = nforce2_calc_fsb(temp);
 
 	return fsb;
 }
 
-/*
+/**
  * nforce2_set_fsb - set new FSB
  * @fsb: New FSB
  *
@@ -194,8 +185,7 @@ static int nforce2_set_fsb(unsigned int fsb)
 	}
 
 	/* First write? Then set actual value */
-	pci_read_config_byte(nforce2_chipset_dev, 
-                             NFORCE2_PLLENABLE, (u8 *)&temp);
+	pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
 	if (!temp) {
 		pll = nforce2_calc_pll(tfsb);
 
@@ -406,9 +396,7 @@ static unsigned int nforce2_detect_chipset(void)
 
 	nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
 					PCI_DEVICE_ID_NVIDIA_NFORCE2,
-                                             PCI_ANY_ID,
-                                             PCI_ANY_ID,
-                                             NULL);
+					PCI_ANY_ID, PCI_ANY_ID, NULL);
 
 	if (nforce2_chipset_dev == NULL)
 		return -ENODEV;

arch/i386/kernel/cpu/cpufreq/elanfreq.c

@@ -86,16 +86,16 @@ static unsigned int elanfreq_get_cpu_frequency(unsigned int cpu)
 	clockspeed_reg = inb_p(REG_CSCDR);
 	local_irq_enable();
 
-        if ((clockspeed_reg & 0xE0) == 0xE0) { return 0; }
+	if ((clockspeed_reg & 0xE0) == 0xE0)
+		return 0;
 
 	/* Are we in CPU clock multiplied mode (66/99 MHz)? */
 	if ((clockspeed_reg & 0xE0) == 0xC0) {
-                if ((clockspeed_reg & 0x01) == 0) {
+		if ((clockspeed_reg & 0x01) == 0)
 			return 66000;
-		} else {
+		else
 			return 99000;
 	}
-        }
 
 	/* 33 MHz is not 32 MHz... */
 	if ((clockspeed_reg & 0xE0)==0xA0)
@@ -117,8 +117,8 @@ static unsigned int elanfreq_get_cpu_frequency(unsigned int cpu)
  *	There is no return value.
  */
 
-static void elanfreq_set_cpu_state (unsigned int state) {
-
+static void elanfreq_set_cpu_state (unsigned int state)
+{
 	struct cpufreq_freqs    freqs;
 
 	freqs.old = elanfreq_get_cpu_frequency(0);
@@ -127,7 +127,8 @@ static void elanfreq_set_cpu_state (unsigned int state) {
 
 	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 
-	printk(KERN_INFO "elanfreq: attempting to set frequency to %i kHz\n",elan_multiplier[state].clock);
+	printk(KERN_INFO "elanfreq: attempting to set frequency to %i kHz\n",
+			elan_multiplier[state].clock);
 
 
 	/*
@@ -227,7 +228,6 @@ static int elanfreq_cpu_init(struct cpufreq_policy *policy)
 		return (result);
 
 	cpufreq_frequency_table_get_attr(elanfreq_table, policy->cpu);
-
 	return 0;
 }
 
@@ -285,12 +285,10 @@ static int __init elanfreq_init(void)
 
 	/* Test if we have the right hardware */
 	if ((c->x86_vendor != X86_VENDOR_AMD) ||
-		(c->x86 != 4) || (c->x86_model!=10))
-	{
+		(c->x86 != 4) || (c->x86_model!=10)) {
 		printk(KERN_INFO "elanfreq: error: no Elan processor found!\n");
                 return -ENODEV;
 	}
-	
 	return cpufreq_register_driver(&elanfreq_driver);
 }
 
@@ -309,4 +307,3 @@ MODULE_DESCRIPTION("cpufreq driver for AMD's Elan CPUs");
 
 module_init(elanfreq_init);
 module_exit(elanfreq_exit);
-

arch/i386/kernel/cpu/cpufreq/gx-suspmod.c

@@ -190,10 +190,9 @@ static __init struct pci_dev *gx_detect_chipset(void)
 
 	/* detect which companion chip is used */
 	while ((gx_pci = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, gx_pci)) != NULL) {
-		if ((pci_match_id(gx_chipset_tbl, gx_pci)) != NULL) {
+		if ((pci_match_id(gx_chipset_tbl, gx_pci)) != NULL)
 			return gx_pci;
 	}
-	}
 
 	dprintk("error: no supported chipset found!\n");
 	return NULL;
@@ -217,7 +216,7 @@ static unsigned int gx_get_cpuspeed(unsigned int cpu)
  *      gx_validate_speed:
  *      determine current cpu speed
  *
-**/
+ **/
 
 static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, u8 *off_duration)
 {
@@ -258,7 +257,6 @@ static void gx_set_cpuspeed(unsigned int khz)
 	unsigned long flags;
 	struct cpufreq_freqs freqs;
 
-
 	freqs.cpu = 0;
 	freqs.old = gx_get_cpuspeed(0);
 

arch/i386/kernel/cpu/cpufreq/powernow-k8.c

@@ -83,11 +83,10 @@ static u32 find_millivolts_from_vid(struct powernow_k8_data *data, u32 vid)
  */
 static u32 convert_fid_to_vco_fid(u32 fid)
 {
-	if (fid < HI_FID_TABLE_BOTTOM) {
+	if (fid < HI_FID_TABLE_BOTTOM)
 		return 8 + (2 * fid);
-	} else {
+	else
 		return fid;
-	}
 }
 
 /*
@@ -782,9 +781,7 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
 		/* verify only 1 entry from the lo frequency table */
 		if (fid < HI_FID_TABLE_BOTTOM) {
 			if (cntlofreq) {
-				/* if both entries are the same, ignore this
-				 * one... 
-				 */
+				/* if both entries are the same, ignore this one ... */
 				if ((powernow_table[i].frequency != powernow_table[cntlofreq].frequency) ||
 				    (powernow_table[i].index != powernow_table[cntlofreq].index)) {
 					printk(KERN_ERR PFX "Too many lo freq table entries\n");

arch/i386/kernel/cpu/cpufreq/speedstep-lib.c

@@ -264,8 +264,7 @@ unsigned int speedstep_detect_processor (void)
 
 	switch (c->x86_model) {
 	case 0x0B: /* Intel PIII [Tualatin] */
-		/* cpuid_ebx(1) is 0x04 for desktop PIII, 
-		                   0x06 for mobile PIII-M */
+		/* cpuid_ebx(1) is 0x04 for desktop PIII, 0x06 for mobile PIII-M */
 		ebx = cpuid_ebx(0x00000001);
 		dprintk("ebx is %x\n", ebx);
 
@@ -277,7 +276,6 @@ unsigned int speedstep_detect_processor (void)
 		/* So far all PIII-M processors support SpeedStep. See
 		 * Intel's 24540640.pdf of June 2003
 		 */
-
 		return SPEEDSTEP_PROCESSOR_PIII_T;
 
 	case 0x08: /* Intel PIII [Coppermine] */
@@ -399,7 +397,7 @@ unsigned int speedstep_get_freqs(unsigned int processor,
 		}
 	}
 
- out:
+out:
 	local_irq_restore(flags);
 	return (ret);
 }

arch/i386/kernel/cpu/cpufreq/speedstep-smi.c

@@ -373,7 +373,6 @@ static int __init speedstep_init(void)
 	dprintk("signature:0x%.8lx, command:0x%.8lx, event:0x%.8lx, perf_level:0x%.8lx.\n",
 		ist_info.signature, ist_info.command, ist_info.event, ist_info.perf_level);
 
-
 	/* Error if no IST-SMI BIOS or no PARM
 		 sig= 'ISGE' aka 'Intel Speedstep Gate E' */
 	if ((ist_info.signature !=  0x47534943) && (
@@ -386,17 +385,15 @@ static int __init speedstep_init(void)
 		smi_sig = ist_info.signature;
 
 	/* setup smi_port from MODLULE_PARM or BIOS */
-	if ((smi_port > 0xff) || (smi_port < 0)) {
+	if ((smi_port > 0xff) || (smi_port < 0))
 		return -EINVAL;
-	} else if (smi_port == 0) {
+	else if (smi_port == 0)
 		smi_port = ist_info.command & 0xff;
-	}
 
-	if ((smi_cmd > 0xff) || (smi_cmd < 0)) {
+	if ((smi_cmd > 0xff) || (smi_cmd < 0))
 		return -EINVAL;
-	} else if (smi_cmd == 0) {
+	else if (smi_cmd == 0)
 		smi_cmd = (ist_info.command >> 16) & 0xff;
-	}
 
 	return cpufreq_register_driver(&speedstep_driver);
 }

drivers/cpufreq/freq_table.c

@@ -60,8 +60,7 @@ int cpufreq_frequency_table_verify(struct cpufreq_policy *policy,
 		return -EINVAL;
 
 	cpufreq_verify_within_limits(policy,
-				     policy->cpuinfo.min_freq, 
-				     policy->cpuinfo.max_freq);
+				     policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
 
 	for (i=0; (table[i].frequency != CPUFREQ_TABLE_END); i++) {
 		unsigned int freq = table[i].frequency;
@@ -77,8 +76,7 @@ int cpufreq_frequency_table_verify(struct cpufreq_policy *policy,
 		policy->max = next_larger;
 
 	cpufreq_verify_within_limits(policy,
-				     policy->cpuinfo.min_freq, 
-				     policy->cpuinfo.max_freq);
+				     policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
 
 	dprintk("verification lead to (%u - %u kHz) for cpu %u\n", policy->min, policy->max, policy->cpu);