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Commit 32f960e9 authored by Kumar Gala's avatar Kumar Gala
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[POWERPC] 85xx: Convert dts to v1 syntax 

Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent a5dc66e2
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arch/powerpc/boot/dts/mpc8540ads.dts
View file @ 32f960e9
/* /*
* MPC8540 ADS Device Tree Source * MPC8540 ADS Device Tree Source
* *
* Copyright 2006 Freescale Semiconductor Inc. * Copyright 2006, 2008 Freescale Semiconductor Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
* option) any later version. * option) any later version.
*/ */
/dts-v1/;
/ { / {
model = "MPC8540ADS"; model = "MPC8540ADS";
...@@ -31,11 +32,11 @@ cpus { ...@@ -31,11 +32,11 @@ cpus {
PowerPC,8540@0 { PowerPC,8540@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0x0>;
d-cache-line-size = <20>; // 32 bytes d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes i-cache-line-size = <32>; // 32 bytes
d-cache-size = <8000>; // L1, 32K d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot clock-frequency = <0>; // 825 MHz, from uboot
...@@ -44,31 +45,31 @@ PowerPC,8540@0 { ...@@ -44,31 +45,31 @@ PowerPC,8540@0 {
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <00000000 08000000>; // 128M at 0x0 reg = <0x0 0x8000000>; // 128M at 0x0
}; };
soc8540@e0000000 { soc8540@e0000000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
device_type = "soc"; device_type = "soc";
ranges = <0 e0000000 00100000>; ranges = <0x0 0xe0000000 0x100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M reg = <0xe0000000 0x100000>; // CCSRBAR 1M
bus-frequency = <0>; bus-frequency = <0>;
memory-controller@2000 { memory-controller@2000 {
compatible = "fsl,8540-memory-controller"; compatible = "fsl,8540-memory-controller";
reg = <2000 1000>; reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <12 2>; interrupts = <18 2>;
}; };
l2-cache-controller@20000 { l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller"; compatible = "fsl,8540-l2-cache-controller";
reg = <20000 1000>; reg = <0x20000 0x1000>;
cache-line-size = <20>; // 32 bytes cache-line-size = <32>; // 32 bytes
cache-size = <40000>; // L2, 256K cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <10 2>; interrupts = <16 2>;
}; };
i2c@3000 { i2c@3000 {
...@@ -76,8 +77,8 @@ i2c@3000 { ...@@ -76,8 +77,8 @@ i2c@3000 {
#size-cells = <0>; #size-cells = <0>;
cell-index = <0>; cell-index = <0>;
compatible = "fsl-i2c"; compatible = "fsl-i2c";
reg = <3000 100>; reg = <0x3000 0x100>;
interrupts = <2b 2>; interrupts = <43 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
dfsrr; dfsrr;
}; };
...@@ -86,24 +87,24 @@ mdio@24520 { ...@@ -86,24 +87,24 @@ mdio@24520 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,gianfar-mdio"; compatible = "fsl,gianfar-mdio";
reg = <24520 20>; reg = <0x24520 0x20>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <5 1>; interrupts = <5 1>;
reg = <0>; reg = <0x0>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <5 1>; interrupts = <5 1>;
reg = <1>; reg = <0x1>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
phy3: ethernet-phy@3 { phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <7 1>; interrupts = <7 1>;
reg = <3>; reg = <0x3>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
}; };
...@@ -113,9 +114,9 @@ enet0: ethernet@24000 { ...@@ -113,9 +114,9 @@ enet0: ethernet@24000 {
device_type = "network"; device_type = "network";
model = "TSEC"; model = "TSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <24000 1000>; reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>; interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
...@@ -125,9 +126,9 @@ enet1: ethernet@25000 { ...@@ -125,9 +126,9 @@ enet1: ethernet@25000 {
device_type = "network"; device_type = "network";
model = "TSEC"; model = "TSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <25000 1000>; reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>; interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy1>; phy-handle = <&phy1>;
}; };
...@@ -137,9 +138,9 @@ enet2: ethernet@26000 { ...@@ -137,9 +138,9 @@ enet2: ethernet@26000 {
device_type = "network"; device_type = "network";
model = "FEC"; model = "FEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <26000 1000>; reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2>; interrupts = <41 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy3>; phy-handle = <&phy3>;
}; };
...@@ -148,9 +149,9 @@ serial0: serial@4500 { ...@@ -148,9 +149,9 @@ serial0: serial@4500 {
cell-index = <0>; cell-index = <0>;
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4500 100>; // reg base, size reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot? clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>; interrupts = <42 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
...@@ -158,9 +159,9 @@ serial1: serial@4600 { ...@@ -158,9 +159,9 @@ serial1: serial@4600 {
cell-index = <1>; cell-index = <1>;
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4600 100>; // reg base, size reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot? clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>; interrupts = <42 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
mpic: pic@40000 { mpic: pic@40000 {
...@@ -168,7 +169,7 @@ mpic: pic@40000 { ...@@ -168,7 +169,7 @@ mpic: pic@40000 {
interrupt-controller; interrupt-controller;
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
reg = <40000 40000>; reg = <0x40000 0x40000>;
compatible = "chrp,open-pic"; compatible = "chrp,open-pic";
device_type = "open-pic"; device_type = "open-pic";
big-endian; big-endian;
...@@ -177,90 +178,90 @@ mpic: pic@40000 { ...@@ -177,90 +178,90 @@ mpic: pic@40000 {
pci0: pci@e0008000 { pci0: pci@e0008000 {
cell-index = <0>; cell-index = <0>;
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x02 */ /* IDSEL 0x02 */
1000 0 0 1 &mpic 1 1 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
1000 0 0 2 &mpic 2 1 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
1000 0 0 3 &mpic 3 1 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
1000 0 0 4 &mpic 4 1 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x03 */ /* IDSEL 0x03 */
1800 0 0 1 &mpic 4 1 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
1800 0 0 2 &mpic 1 1 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
1800 0 0 3 &mpic 2 1 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
1800 0 0 4 &mpic 3 1 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x04 */ /* IDSEL 0x04 */
2000 0 0 1 &mpic 3 1 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
2000 0 0 2 &mpic 4 1 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
2000 0 0 3 &mpic 1 1 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
2000 0 0 4 &mpic 2 1 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x05 */ /* IDSEL 0x05 */
2800 0 0 1 &mpic 2 1 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
2800 0 0 2 &mpic 3 1 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
2800 0 0 3 &mpic 4 1 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
2800 0 0 4 &mpic 1 1 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x0c */ /* IDSEL 0x0c */
6000 0 0 1 &mpic 1 1 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
6000 0 0 2 &mpic 2 1 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
6000 0 0 3 &mpic 3 1 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
6000 0 0 4 &mpic 4 1 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x0d */ /* IDSEL 0x0d */
6800 0 0 1 &mpic 4 1 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
6800 0 0 2 &mpic 1 1 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
6800 0 0 3 &mpic 2 1 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
6800 0 0 4 &mpic 3 1 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x0e */ /* IDSEL 0x0e */
7000 0 0 1 &mpic 3 1 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
7000 0 0 2 &mpic 4 1 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
7000 0 0 3 &mpic 1 1 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
7000 0 0 4 &mpic 2 1 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x0f */ /* IDSEL 0x0f */
7800 0 0 1 &mpic 2 1 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
7800 0 0 2 &mpic 3 1 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
7800 0 0 3 &mpic 4 1 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
7800 0 0 4 &mpic 1 1 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x12 */ /* IDSEL 0x12 */
9000 0 0 1 &mpic 1 1 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
9000 0 0 2 &mpic 2 1 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
9000 0 0 3 &mpic 3 1 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
9000 0 0 4 &mpic 4 1 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x13 */ /* IDSEL 0x13 */
9800 0 0 1 &mpic 4 1 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
9800 0 0 2 &mpic 1 1 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
9800 0 0 3 &mpic 2 1 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
9800 0 0 4 &mpic 3 1 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x14 */ /* IDSEL 0x14 */
a000 0 0 1 &mpic 3 1 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
a000 0 0 2 &mpic 4 1 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
a000 0 0 3 &mpic 1 1 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
a000 0 0 4 &mpic 2 1 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x15 */ /* IDSEL 0x15 */
a800 0 0 1 &mpic 2 1 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
a800 0 0 2 &mpic 3 1 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
a800 0 0 3 &mpic 4 1 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
a800 0 0 4 &mpic 1 1>; 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <18 2>; interrupts = <24 2>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
01000000 0 00000000 e2000000 0 00100000>; 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
clock-frequency = <3f940aa>; clock-frequency = <66666666>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <e0008000 1000>; reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
}; };
......
arch/powerpc/boot/dts/mpc8541cds.dts
View file @ 32f960e9
/* /*
* MPC8541 CDS Device Tree Source * MPC8541 CDS Device Tree Source
* *
* Copyright 2006 Freescale Semiconductor Inc. * Copyright 2006, 2008 Freescale Semiconductor Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
* option) any later version. * option) any later version.
*/ */
/dts-v1/;
/ { / {
model = "MPC8541CDS"; model = "MPC8541CDS";
...@@ -31,11 +32,11 @@ cpus { ...@@ -31,11 +32,11 @@ cpus {
PowerPC,8541@0 { PowerPC,8541@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0x0>;
d-cache-line-size = <20>; // 32 bytes d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes i-cache-line-size = <32>; // 32 bytes
d-cache-size = <8000>; // L1, 32K d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot clock-frequency = <0>; // 825 MHz, from uboot
...@@ -44,31 +45,31 @@ PowerPC,8541@0 { ...@@ -44,31 +45,31 @@ PowerPC,8541@0 {
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <00000000 08000000>; // 128M at 0x0 reg = <0x0 0x8000000>; // 128M at 0x0
}; };
soc8541@e0000000 { soc8541@e0000000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
device_type = "soc"; device_type = "soc";
ranges = <0 e0000000 00100000>; ranges = <0x0 0xe0000000 0x100000>;
reg = <e0000000 00001000>; // CCSRBAR 1M reg = <0xe0000000 0x1000>; // CCSRBAR 1M
bus-frequency = <0>; bus-frequency = <0>;
memory-controller@2000 { memory-controller@2000 {
compatible = "fsl,8541-memory-controller"; compatible = "fsl,8541-memory-controller";
reg = <2000 1000>; reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <12 2>; interrupts = <18 2>;
}; };
l2-cache-controller@20000 { l2-cache-controller@20000 {
compatible = "fsl,8541-l2-cache-controller"; compatible = "fsl,8541-l2-cache-controller";
reg = <20000 1000>; reg = <0x20000 0x1000>;
cache-line-size = <20>; // 32 bytes cache-line-size = <32>; // 32 bytes
cache-size = <40000>; // L2, 256K cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <10 2>; interrupts = <16 2>;
}; };
i2c@3000 { i2c@3000 {
...@@ -76,8 +77,8 @@ i2c@3000 { ...@@ -76,8 +77,8 @@ i2c@3000 {
#size-cells = <0>; #size-cells = <0>;
cell-index = <0>; cell-index = <0>;
compatible = "fsl-i2c"; compatible = "fsl-i2c";
reg = <3000 100>; reg = <0x3000 0x100>;
interrupts = <2b 2>; interrupts = <43 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
dfsrr; dfsrr;
}; };
...@@ -86,18 +87,18 @@ mdio@24520 { ...@@ -86,18 +87,18 @@ mdio@24520 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,gianfar-mdio"; compatible = "fsl,gianfar-mdio";
reg = <24520 20>; reg = <0x24520 0x20>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <5 1>; interrupts = <5 1>;
reg = <0>; reg = <0x0>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <5 1>; interrupts = <5 1>;
reg = <1>; reg = <0x1>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
}; };
...@@ -107,9 +108,9 @@ enet0: ethernet@24000 { ...@@ -107,9 +108,9 @@ enet0: ethernet@24000 {
device_type = "network"; device_type = "network";
model = "TSEC"; model = "TSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <24000 1000>; reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>; interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
...@@ -119,9 +120,9 @@ enet1: ethernet@25000 { ...@@ -119,9 +120,9 @@ enet1: ethernet@25000 {
device_type = "network"; device_type = "network";
model = "TSEC"; model = "TSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <25000 1000>; reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>; interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy1>; phy-handle = <&phy1>;
}; };
...@@ -130,9 +131,9 @@ serial0: serial@4500 { ...@@ -130,9 +131,9 @@ serial0: serial@4500 {
cell-index = <0>; cell-index = <0>;
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4500 100>; // reg base, size reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot? clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>; interrupts = <42 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
...@@ -140,9 +141,9 @@ serial1: serial@4600 { ...@@ -140,9 +141,9 @@ serial1: serial@4600 {
cell-index = <1>; cell-index = <1>;
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4600 100>; // reg base, size reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot? clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>; interrupts = <42 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
...@@ -151,7 +152,7 @@ mpic: pic@40000 { ...@@ -151,7 +152,7 @@ mpic: pic@40000 {
interrupt-controller; interrupt-controller;
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
reg = <40000 40000>; reg = <0x40000 0x40000>;
compatible = "chrp,open-pic"; compatible = "chrp,open-pic";
device_type = "open-pic"; device_type = "open-pic";
big-endian; big-endian;
...@@ -161,17 +162,17 @@ cpm@919c0 { ...@@ -161,17 +162,17 @@ cpm@919c0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "fsl,mpc8541-cpm", "fsl,cpm2"; compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
reg = <919c0 30>; reg = <0x919c0 0x30>;
ranges; ranges;
muram@80000 { muram@80000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 80000 10000>; ranges = <0x0 0x80000 0x10000>;
data@0 { data@0 {
compatible = "fsl,cpm-muram-data"; compatible = "fsl,cpm-muram-data";
reg = <0 2000 9000 1000>; reg = <0x0 0x2000 0x9000 0x1000>;
}; };
}; };
...@@ -179,16 +180,16 @@ brg@919f0 { ...@@ -179,16 +180,16 @@ brg@919f0 {
compatible = "fsl,mpc8541-brg", compatible = "fsl,mpc8541-brg",
"fsl,cpm2-brg", "fsl,cpm2-brg",
"fsl,cpm-brg"; "fsl,cpm-brg";
reg = <919f0 10 915f0 10>; reg = <0x919f0 0x10 0x915f0 0x10>;
}; };
cpmpic: pic@90c00 { cpmpic: pic@90c00 {
interrupt-controller; interrupt-controller;
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupts = <2e 2>; interrupts = <46 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
reg = <90c00 80>; reg = <0x90c00 0x80>;
compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
}; };
}; };
...@@ -196,68 +197,68 @@ cpmpic: pic@90c00 { ...@@ -196,68 +197,68 @@ cpmpic: pic@90c00 {
pci0: pci@e0008000 { pci0: pci@e0008000 {
cell-index = <0>; cell-index = <0>;
interrupt-map-mask = <1f800 0 0 7>; interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x10 */ /* IDSEL 0x10 */
08000 0 0 1 &mpic 0 1 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
08000 0 0 2 &mpic 1 1 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
08000 0 0 3 &mpic 2 1 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
08000 0 0 4 &mpic 3 1 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x11 */ /* IDSEL 0x11 */
08800 0 0 1 &mpic 0 1 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
08800 0 0 2 &mpic 1 1 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
08800 0 0 3 &mpic 2 1 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
08800 0 0 4 &mpic 3 1 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x12 (Slot 1) */ /* IDSEL 0x12 (Slot 1) */
09000 0 0 1 &mpic 0 1 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
09000 0 0 2 &mpic 1 1 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
09000 0 0 3 &mpic 2 1 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
09000 0 0 4 &mpic 3 1 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x13 (Slot 2) */ /* IDSEL 0x13 (Slot 2) */
09800 0 0 1 &mpic 1 1 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
09800 0 0 2 &mpic 2 1 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
09800 0 0 3 &mpic 3 1 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
09800 0 0 4 &mpic 0 1 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x14 (Slot 3) */ /* IDSEL 0x14 (Slot 3) */
0a000 0 0 1 &mpic 2 1 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
0a000 0 0 2 &mpic 3 1 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
0a000 0 0 3 &mpic 0 1 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
0a000 0 0 4 &mpic 1 1 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x15 (Slot 4) */ /* IDSEL 0x15 (Slot 4) */
0a800 0 0 1 &mpic 3 1 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
0a800 0 0 2 &mpic 0 1 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
0a800 0 0 3 &mpic 1 1 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
0a800 0 0 4 &mpic 2 1 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
/* Bus 1 (Tundra Bridge) */ /* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */ /* IDSEL 0x12 (ISA bridge) */
19000 0 0 1 &mpic 0 1 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
19000 0 0 2 &mpic 1 1 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
19000 0 0 3 &mpic 2 1 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
19000 0 0 4 &mpic 3 1>; 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <18 2>; interrupts = <24 2>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
01000000 0 00000000 e2000000 0 00100000>; 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
clock-frequency = <3f940aa>; clock-frequency = <66666666>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <e0008000 1000>; reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pci"; compatible = "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
i8259@19000 { i8259@19000 {
interrupt-controller; interrupt-controller;
device_type = "interrupt-controller"; device_type = "interrupt-controller";
reg = <19000 0 0 0 1>; reg = <0x19000 0x0 0x0 0x0 0x1>;
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
compatible = "chrp,iic"; compatible = "chrp,iic";
...@@ -268,24 +269,24 @@ i8259@19000 { ...@@ -268,24 +269,24 @@ i8259@19000 {
pci1: pci@e0009000 { pci1: pci@e0009000 {
cell-index = <1>; cell-index = <1>;
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x15 */ /* IDSEL 0x15 */
a800 0 0 1 &mpic b 1 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
a800 0 0 2 &mpic b 1 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
a800 0 0 3 &mpic b 1 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
a800 0 0 4 &mpic b 1>; 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <19 2>; interrupts = <25 2>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 20000000 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
01000000 0 00000000 e3000000 0 00100000>; 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
clock-frequency = <3f940aa>; clock-frequency = <66666666>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <e0009000 1000>; reg = <0xe0009000 0x1000>;
compatible = "fsl,mpc8540-pci"; compatible = "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
}; };
......
arch/powerpc/boot/dts/mpc8544ds.dts
View file @ 32f960e9
/* /*
* MPC8544 DS Device Tree Source * MPC8544 DS Device Tree Source
* *
* Copyright 2007 Freescale Semiconductor Inc. * Copyright 2007, 2008 Freescale Semiconductor Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
* option) any later version. * option) any later version.
*/ */
/dts-v1/;
/ { / {
model = "MPC8544DS"; model = "MPC8544DS";
compatible = "MPC8544DS", "MPC85xxDS"; compatible = "MPC8544DS", "MPC85xxDS";
...@@ -27,17 +28,17 @@ aliases { ...@@ -27,17 +28,17 @@ aliases {
}; };
cpus { cpus {
#cpus = <1>; #cpus = <0x1>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
PowerPC,8544@0 { PowerPC,8544@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0x0>;
d-cache-line-size = <20>; // 32 bytes d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes i-cache-line-size = <32>; // 32 bytes
d-cache-size = <8000>; // L1, 32K d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; timebase-frequency = <0>;
bus-frequency = <0>; bus-frequency = <0>;
clock-frequency = <0>; clock-frequency = <0>;
...@@ -46,7 +47,7 @@ PowerPC,8544@0 { ...@@ -46,7 +47,7 @@ PowerPC,8544@0 {
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <00000000 00000000>; // Filled by U-Boot reg = <0x0 0x0>; // Filled by U-Boot
}; };
soc8544@e0000000 { soc8544@e0000000 {
...@@ -54,24 +55,24 @@ soc8544@e0000000 { ...@@ -54,24 +55,24 @@ soc8544@e0000000 {
#size-cells = <1>; #size-cells = <1>;
device_type = "soc"; device_type = "soc";
ranges = <00000000 e0000000 00100000>; ranges = <0x0 0xe0000000 0x100000>;
reg = <e0000000 00001000>; // CCSRBAR 1M reg = <0xe0000000 0x1000>; // CCSRBAR 1M
bus-frequency = <0>; // Filled out by uboot. bus-frequency = <0>; // Filled out by uboot.
memory-controller@2000 { memory-controller@2000 {
compatible = "fsl,8544-memory-controller"; compatible = "fsl,8544-memory-controller";
reg = <2000 1000>; reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <12 2>; interrupts = <18 2>;
}; };
l2-cache-controller@20000 { l2-cache-controller@20000 {
compatible = "fsl,8544-l2-cache-controller"; compatible = "fsl,8544-l2-cache-controller";
reg = <20000 1000>; reg = <0x20000 0x1000>;
cache-line-size = <20>; // 32 bytes cache-line-size = <32>; // 32 bytes
cache-size = <40000>; // L2, 256K cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <10 2>; interrupts = <16 2>;
}; };
i2c@3000 { i2c@3000 {
...@@ -79,8 +80,8 @@ i2c@3000 { ...@@ -79,8 +80,8 @@ i2c@3000 {
#size-cells = <0>; #size-cells = <0>;
cell-index = <0>; cell-index = <0>;
compatible = "fsl-i2c"; compatible = "fsl-i2c";
reg = <3000 100>; reg = <0x3000 0x100>;
interrupts = <2b 2>; interrupts = <43 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
dfsrr; dfsrr;
}; };
...@@ -90,8 +91,8 @@ i2c@3100 { ...@@ -90,8 +91,8 @@ i2c@3100 {
#size-cells = <0>; #size-cells = <0>;
cell-index = <1>; cell-index = <1>;
compatible = "fsl-i2c"; compatible = "fsl-i2c";
reg = <3100 100>; reg = <0x3100 0x100>;
interrupts = <2b 2>; interrupts = <43 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
dfsrr; dfsrr;
}; };
...@@ -100,18 +101,18 @@ mdio@24520 { ...@@ -100,18 +101,18 @@ mdio@24520 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,gianfar-mdio"; compatible = "fsl,gianfar-mdio";
reg = <24520 20>; reg = <0x24520 0x20>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <a 1>; interrupts = <10 1>;
reg = <0>; reg = <0x0>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <a 1>; interrupts = <10 1>;
reg = <1>; reg = <0x1>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
}; };
...@@ -120,40 +121,40 @@ dma@21300 { ...@@ -120,40 +121,40 @@ dma@21300 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma"; compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
reg = <21300 4>; reg = <0x21300 0x4>;
ranges = <0 21100 200>; ranges = <0x0 0x21100 0x200>;
cell-index = <0>; cell-index = <0>;
dma-channel@0 { dma-channel@0 {
compatible = "fsl,mpc8544-dma-channel", compatible = "fsl,mpc8544-dma-channel",
"fsl,eloplus-dma-channel"; "fsl,eloplus-dma-channel";
reg = <0 80>; reg = <0x0 0x80>;
cell-index = <0>; cell-index = <0>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <14 2>; interrupts = <20 2>;
}; };
dma-channel@80 { dma-channel@80 {
compatible = "fsl,mpc8544-dma-channel", compatible = "fsl,mpc8544-dma-channel",
"fsl,eloplus-dma-channel"; "fsl,eloplus-dma-channel";
reg = <80 80>; reg = <0x80 0x80>;
cell-index = <1>; cell-index = <1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <15 2>; interrupts = <21 2>;
}; };
dma-channel@100 { dma-channel@100 {
compatible = "fsl,mpc8544-dma-channel", compatible = "fsl,mpc8544-dma-channel",
"fsl,eloplus-dma-channel"; "fsl,eloplus-dma-channel";
reg = <100 80>; reg = <0x100 0x80>;
cell-index = <2>; cell-index = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <16 2>; interrupts = <22 2>;
}; };
dma-channel@180 { dma-channel@180 {
compatible = "fsl,mpc8544-dma-channel", compatible = "fsl,mpc8544-dma-channel",
"fsl,eloplus-dma-channel"; "fsl,eloplus-dma-channel";
reg = <180 80>; reg = <0x180 0x80>;
cell-index = <3>; cell-index = <3>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <17 2>; interrupts = <23 2>;
}; };
}; };
...@@ -162,9 +163,9 @@ enet0: ethernet@24000 { ...@@ -162,9 +163,9 @@ enet0: ethernet@24000 {
device_type = "network"; device_type = "network";
model = "TSEC"; model = "TSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <24000 1000>; reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>; interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
...@@ -175,9 +176,9 @@ enet1: ethernet@26000 { ...@@ -175,9 +176,9 @@ enet1: ethernet@26000 {
device_type = "network"; device_type = "network";
model = "TSEC"; model = "TSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <26000 1000>; reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1f 2 20 2 21 2>; interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy1>; phy-handle = <&phy1>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
...@@ -187,9 +188,9 @@ serial0: serial@4500 { ...@@ -187,9 +188,9 @@ serial0: serial@4500 {
cell-index = <0>; cell-index = <0>;
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4500 100>; reg = <0x4500 0x100>;
clock-frequency = <0>; clock-frequency = <0>;
interrupts = <2a 2>; interrupts = <42 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
...@@ -197,15 +198,15 @@ serial1: serial@4600 { ...@@ -197,15 +198,15 @@ serial1: serial@4600 {
cell-index = <1>; cell-index = <1>;
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4600 100>; reg = <0x4600 0x100>;
clock-frequency = <0>; clock-frequency = <0>;
interrupts = <2a 2>; interrupts = <42 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
global-utilities@e0000 { //global utilities block global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8548-guts"; compatible = "fsl,mpc8548-guts";
reg = <e0000 1000>; reg = <0xe0000 0x1000>;
fsl,has-rstcr; fsl,has-rstcr;
}; };
...@@ -214,7 +215,7 @@ mpic: pic@40000 { ...@@ -214,7 +215,7 @@ mpic: pic@40000 {
interrupt-controller; interrupt-controller;
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
reg = <40000 40000>; reg = <0x40000 0x40000>;
compatible = "chrp,open-pic"; compatible = "chrp,open-pic";
device_type = "open-pic"; device_type = "open-pic";
big-endian; big-endian;
...@@ -225,32 +226,32 @@ pci0: pci@e0008000 { ...@@ -225,32 +226,32 @@ pci0: pci@e0008000 {
cell-index = <0>; cell-index = <0>;
compatible = "fsl,mpc8540-pci"; compatible = "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x11 J17 Slot 1 */ /* IDSEL 0x11 J17 Slot 1 */
8800 0 0 1 &mpic 2 1 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
8800 0 0 2 &mpic 3 1 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
8800 0 0 3 &mpic 4 1 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
8800 0 0 4 &mpic 1 1 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x12 J16 Slot 2 */ /* IDSEL 0x12 J16 Slot 2 */
9000 0 0 1 &mpic 3 1 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
9000 0 0 2 &mpic 4 1 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
9000 0 0 3 &mpic 2 1 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
9000 0 0 4 &mpic 1 1>; 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <18 2>; interrupts = <24 2>;
bus-range = <0 ff>; bus-range = <0 255>;
ranges = <02000000 0 c0000000 c0000000 0 20000000 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
01000000 0 00000000 e1000000 0 00010000>; 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
clock-frequency = <3f940aa>; clock-frequency = <66666666>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <e0008000 1000>; reg = <0xe0008000 0x1000>;
}; };
pci1: pcie@e0009000 { pci1: pcie@e0009000 {
...@@ -260,33 +261,33 @@ pci1: pcie@e0009000 { ...@@ -260,33 +261,33 @@ pci1: pcie@e0009000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <e0009000 1000>; reg = <0xe0009000 0x1000>;
bus-range = <0 ff>; bus-range = <0 255>;
ranges = <02000000 0 80000000 80000000 0 20000000 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
01000000 0 00000000 e1010000 0 00010000>; 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
clock-frequency = <1fca055>; clock-frequency = <33333333>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <1a 2>; interrupts = <26 2>;
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x0 */ /* IDSEL 0x0 */
0000 0 0 1 &mpic 4 1 0000 0x0 0x0 0x1 &mpic 0x4 0x1
0000 0 0 2 &mpic 5 1 0000 0x0 0x0 0x2 &mpic 0x5 0x1
0000 0 0 3 &mpic 6 1 0000 0x0 0x0 0x3 &mpic 0x6 0x1
0000 0 0 4 &mpic 7 1 0000 0x0 0x0 0x4 &mpic 0x7 0x1
>; >;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>; reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
device_type = "pci"; device_type = "pci";
ranges = <02000000 0 80000000 ranges = <0x2000000 0x0 0x80000000
02000000 0 80000000 0x2000000 0x0 0x80000000
0 20000000 0x0 0x20000000
01000000 0 00000000 0x1000000 0x0 0x0
01000000 0 00000000 0x1000000 0x0 0x0
0 00010000>; 0x0 0x10000>;
}; };
}; };
...@@ -297,33 +298,33 @@ pci2: pcie@e000a000 { ...@@ -297,33 +298,33 @@ pci2: pcie@e000a000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <e000a000 1000>; reg = <0xe000a000 0x1000>;
bus-range = <0 ff>; bus-range = <0 255>;
ranges = <02000000 0 a0000000 a0000000 0 10000000 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
01000000 0 00000000 e1020000 0 00010000>; 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
clock-frequency = <1fca055>; clock-frequency = <33333333>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <19 2>; interrupts = <25 2>;
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x0 */ /* IDSEL 0x0 */
0000 0 0 1 &mpic 0 1 0000 0x0 0x0 0x1 &mpic 0x0 0x1
0000 0 0 2 &mpic 1 1 0000 0x0 0x0 0x2 &mpic 0x1 0x1
0000 0 0 3 &mpic 2 1 0000 0x0 0x0 0x3 &mpic 0x2 0x1
0000 0 0 4 &mpic 3 1 0000 0x0 0x0 0x4 &mpic 0x3 0x1
>; >;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>; reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
device_type = "pci"; device_type = "pci";
ranges = <02000000 0 a0000000 ranges = <0x2000000 0x0 0xa0000000
02000000 0 a0000000 0x2000000 0x0 0xa0000000
0 10000000 0x0 0x10000000
01000000 0 00000000 0x1000000 0x0 0x0
01000000 0 00000000 0x1000000 0x0 0x0
0 00010000>; 0x0 0x10000>;
}; };
}; };
...@@ -334,72 +335,72 @@ pci3: pcie@e000b000 { ...@@ -334,72 +335,72 @@ pci3: pcie@e000b000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <e000b000 1000>; reg = <0xe000b000 0x1000>;
bus-range = <0 ff>; bus-range = <0 255>;
ranges = <02000000 0 b0000000 b0000000 0 00100000 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
01000000 0 00000000 b0100000 0 00100000>; 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
clock-frequency = <1fca055>; clock-frequency = <33333333>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <1b 2>; interrupts = <27 2>;
interrupt-map-mask = <ff00 0 0 1>; interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
interrupt-map = < interrupt-map = <
// IDSEL 0x1c USB // IDSEL 0x1c USB
e000 0 0 1 &i8259 c 2 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
e100 0 0 2 &i8259 9 2 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
e200 0 0 3 &i8259 a 2 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
e300 0 0 4 &i8259 b 2 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
// IDSEL 0x1d Audio // IDSEL 0x1d Audio
e800 0 0 1 &i8259 6 2 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
// IDSEL 0x1e Legacy // IDSEL 0x1e Legacy
f000 0 0 1 &i8259 7 2 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
f100 0 0 1 &i8259 7 2 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
// IDSEL 0x1f IDE/SATA // IDSEL 0x1f IDE/SATA
f800 0 0 1 &i8259 e 2 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
f900 0 0 1 &i8259 5 2 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
>; >;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>; reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
device_type = "pci"; device_type = "pci";
ranges = <02000000 0 b0000000 ranges = <0x2000000 0x0 0xb0000000
02000000 0 b0000000 0x2000000 0x0 0xb0000000
0 00100000 0x0 0x100000
01000000 0 00000000 0x1000000 0x0 0x0
01000000 0 00000000 0x1000000 0x0 0x0
0 00100000>; 0x0 0x100000>;
uli1575@0 { uli1575@0 {
reg = <0 0 0 0 0>; reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
ranges = <02000000 0 b0000000 ranges = <0x2000000 0x0 0xb0000000
02000000 0 b0000000 0x2000000 0x0 0xb0000000
0 00100000 0x0 0x100000
01000000 0 00000000 0x1000000 0x0 0x0
01000000 0 00000000 0x1000000 0x0 0x0
0 00100000>; 0x0 0x100000>;
isa@1e { isa@1e {
device_type = "isa"; device_type = "isa";
#interrupt-cells = <2>; #interrupt-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
#address-cells = <2>; #address-cells = <2>;
reg = <f000 0 0 0 0>; reg = <0xf000 0x0 0x0 0x0 0x0>;
ranges = <1 0 ranges = <0x1 0x0
01000000 0 0 0x1000000 0x0 0x0
00001000>; 0x1000>;
interrupt-parent = <&i8259>; interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 { i8259: interrupt-controller@20 {
reg = <1 20 2 reg = <0x1 0x20 0x2
1 a0 2 0x1 0xa0 0x2
1 4d0 2>; 0x1 0x4d0 0x2>;
interrupt-controller; interrupt-controller;
device_type = "interrupt-controller"; device_type = "interrupt-controller";
#address-cells = <0>; #address-cells = <0>;
...@@ -412,28 +413,28 @@ i8259: interrupt-controller@20 { ...@@ -412,28 +413,28 @@ i8259: interrupt-controller@20 {
i8042@60 { i8042@60 {
#size-cells = <0>; #size-cells = <0>;
#address-cells = <1>; #address-cells = <1>;
reg = <1 60 1 1 64 1>; reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
interrupts = <1 3 c 3>; interrupts = <1 3 12 3>;
interrupt-parent = <&i8259>; interrupt-parent = <&i8259>;
keyboard@0 { keyboard@0 {
reg = <0>; reg = <0x0>;
compatible = "pnpPNP,303"; compatible = "pnpPNP,303";
}; };
mouse@1 { mouse@1 {
reg = <1>; reg = <0x1>;
compatible = "pnpPNP,f03"; compatible = "pnpPNP,f03";
}; };
}; };
rtc@70 { rtc@70 {
compatible = "pnpPNP,b00"; compatible = "pnpPNP,b00";
reg = <1 70 2>; reg = <0x1 0x70 0x2>;
}; };
gpio@400 { gpio@400 {
reg = <1 400 80>; reg = <0x1 0x400 0x80>;
}; };
}; };
}; };
......
arch/powerpc/boot/dts/mpc8548cds.dts
View file @ 32f960e9
/* /*
* MPC8548 CDS Device Tree Source * MPC8548 CDS Device Tree Source
* *
* Copyright 2006 Freescale Semiconductor Inc. * Copyright 2006, 2008 Freescale Semiconductor Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
* option) any later version. * option) any later version.
*/ */
/dts-v1/;
/ { / {
model = "MPC8548CDS"; model = "MPC8548CDS";
...@@ -36,11 +37,11 @@ cpus { ...@@ -36,11 +37,11 @@ cpus {
PowerPC,8548@0 { PowerPC,8548@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0x0>;
d-cache-line-size = <20>; // 32 bytes d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes i-cache-line-size = <32>; // 32 bytes
d-cache-size = <8000>; // L1, 32K d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot clock-frequency = <0>; // 825 MHz, from uboot
...@@ -49,31 +50,31 @@ PowerPC,8548@0 { ...@@ -49,31 +50,31 @@ PowerPC,8548@0 {
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <00000000 08000000>; // 128M at 0x0 reg = <0x0 0x8000000>; // 128M at 0x0
}; };
soc8548@e0000000 { soc8548@e0000000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
device_type = "soc"; device_type = "soc";
ranges = <00000000 e0000000 00100000>; ranges = <0x0 0xe0000000 0x100000>;
reg = <e0000000 00001000>; // CCSRBAR reg = <0xe0000000 0x1000>; // CCSRBAR
bus-frequency = <0>; bus-frequency = <0>;
memory-controller@2000 { memory-controller@2000 {
compatible = "fsl,8548-memory-controller"; compatible = "fsl,8548-memory-controller";
reg = <2000 1000>; reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <12 2>; interrupts = <18 2>;
}; };
l2-cache-controller@20000 { l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller"; compatible = "fsl,8548-l2-cache-controller";
reg = <20000 1000>; reg = <0x20000 0x1000>;
cache-line-size = <20>; // 32 bytes cache-line-size = <32>; // 32 bytes
cache-size = <80000>; // L2, 512K cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <10 2>; interrupts = <16 2>;
}; };
i2c@3000 { i2c@3000 {
...@@ -81,8 +82,8 @@ i2c@3000 { ...@@ -81,8 +82,8 @@ i2c@3000 {
#size-cells = <0>; #size-cells = <0>;
cell-index = <0>; cell-index = <0>;
compatible = "fsl-i2c"; compatible = "fsl-i2c";
reg = <3000 100>; reg = <0x3000 0x100>;
interrupts = <2b 2>; interrupts = <43 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
dfsrr; dfsrr;
}; };
...@@ -92,8 +93,8 @@ i2c@3100 { ...@@ -92,8 +93,8 @@ i2c@3100 {
#size-cells = <0>; #size-cells = <0>;
cell-index = <1>; cell-index = <1>;
compatible = "fsl-i2c"; compatible = "fsl-i2c";
reg = <3100 100>; reg = <0x3100 0x100>;
interrupts = <2b 2>; interrupts = <43 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
dfsrr; dfsrr;
}; };
...@@ -102,30 +103,30 @@ mdio@24520 { ...@@ -102,30 +103,30 @@ mdio@24520 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,gianfar-mdio"; compatible = "fsl,gianfar-mdio";
reg = <24520 20>; reg = <0x24520 0x20>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <5 1>; interrupts = <5 1>;
reg = <0>; reg = <0x0>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <5 1>; interrupts = <5 1>;
reg = <1>; reg = <0x1>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
phy2: ethernet-phy@2 { phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <5 1>; interrupts = <5 1>;
reg = <2>; reg = <0x2>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
phy3: ethernet-phy@3 { phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <5 1>; interrupts = <5 1>;
reg = <3>; reg = <0x3>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
}; };
...@@ -135,9 +136,9 @@ enet0: ethernet@24000 { ...@@ -135,9 +136,9 @@ enet0: ethernet@24000 {
device_type = "network"; device_type = "network";
model = "eTSEC"; model = "eTSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <24000 1000>; reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>; interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
...@@ -147,9 +148,9 @@ enet1: ethernet@25000 { ...@@ -147,9 +148,9 @@ enet1: ethernet@25000 {
device_type = "network"; device_type = "network";
model = "eTSEC"; model = "eTSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <25000 1000>; reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>; interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy1>; phy-handle = <&phy1>;
}; };
...@@ -160,9 +161,9 @@ enet2: ethernet@26000 { ...@@ -160,9 +161,9 @@ enet2: ethernet@26000 {
device_type = "network"; device_type = "network";
model = "eTSEC"; model = "eTSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <26000 1000>; reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1f 2 20 2 21 2>; interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy2>; phy-handle = <&phy2>;
}; };
...@@ -172,9 +173,9 @@ enet3: ethernet@27000 { ...@@ -172,9 +173,9 @@ enet3: ethernet@27000 {
device_type = "network"; device_type = "network";
model = "eTSEC"; model = "eTSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <27000 1000>; reg = <0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <25 2 26 2 27 2>; interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy3>; phy-handle = <&phy3>;
}; };
...@@ -184,9 +185,9 @@ serial0: serial@4500 { ...@@ -184,9 +185,9 @@ serial0: serial@4500 {
cell-index = <0>; cell-index = <0>;
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4500 100>; // reg base, size reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot? clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>; interrupts = <42 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
...@@ -194,15 +195,15 @@ serial1: serial@4600 { ...@@ -194,15 +195,15 @@ serial1: serial@4600 {
cell-index = <1>; cell-index = <1>;
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4600 100>; // reg base, size reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot? clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>; interrupts = <42 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
global-utilities@e0000 { //global utilities reg global-utilities@e0000 { //global utilities reg
compatible = "fsl,mpc8548-guts"; compatible = "fsl,mpc8548-guts";
reg = <e0000 1000>; reg = <0xe0000 0x1000>;
fsl,has-rstcr; fsl,has-rstcr;
}; };
...@@ -211,7 +212,7 @@ mpic: pic@40000 { ...@@ -211,7 +212,7 @@ mpic: pic@40000 {
interrupt-controller; interrupt-controller;
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
reg = <40000 40000>; reg = <0x40000 0x40000>;
compatible = "chrp,open-pic"; compatible = "chrp,open-pic";
device_type = "open-pic"; device_type = "open-pic";
big-endian; big-endian;
...@@ -220,139 +221,139 @@ mpic: pic@40000 { ...@@ -220,139 +221,139 @@ mpic: pic@40000 {
pci0: pci@e0008000 { pci0: pci@e0008000 {
cell-index = <0>; cell-index = <0>;
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x4 (PCIX Slot 2) */ /* IDSEL 0x4 (PCIX Slot 2) */
02000 0 0 1 &mpic 0 1 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
02000 0 0 2 &mpic 1 1 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
02000 0 0 3 &mpic 2 1 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
02000 0 0 4 &mpic 3 1 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x5 (PCIX Slot 3) */ /* IDSEL 0x5 (PCIX Slot 3) */
02800 0 0 1 &mpic 1 1 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
02800 0 0 2 &mpic 2 1 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
02800 0 0 3 &mpic 3 1 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
02800 0 0 4 &mpic 0 1 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x6 (PCIX Slot 4) */ /* IDSEL 0x6 (PCIX Slot 4) */
03000 0 0 1 &mpic 2 1 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
03000 0 0 2 &mpic 3 1 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
03000 0 0 3 &mpic 0 1 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
03000 0 0 4 &mpic 1 1 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x8 (PCIX Slot 5) */ /* IDSEL 0x8 (PCIX Slot 5) */
04000 0 0 1 &mpic 0 1 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
04000 0 0 2 &mpic 1 1 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
04000 0 0 3 &mpic 2 1 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
04000 0 0 4 &mpic 3 1 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0xC (Tsi310 bridge) */ /* IDSEL 0xC (Tsi310 bridge) */
06000 0 0 1 &mpic 0 1 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
06000 0 0 2 &mpic 1 1 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
06000 0 0 3 &mpic 2 1 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
06000 0 0 4 &mpic 3 1 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x14 (Slot 2) */ /* IDSEL 0x14 (Slot 2) */
0a000 0 0 1 &mpic 0 1 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
0a000 0 0 2 &mpic 1 1 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
0a000 0 0 3 &mpic 2 1 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
0a000 0 0 4 &mpic 3 1 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x15 (Slot 3) */ /* IDSEL 0x15 (Slot 3) */
0a800 0 0 1 &mpic 1 1 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
0a800 0 0 2 &mpic 2 1 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
0a800 0 0 3 &mpic 3 1 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
0a800 0 0 4 &mpic 0 1 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x16 (Slot 4) */ /* IDSEL 0x16 (Slot 4) */
0b000 0 0 1 &mpic 2 1 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
0b000 0 0 2 &mpic 3 1 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
0b000 0 0 3 &mpic 0 1 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
0b000 0 0 4 &mpic 1 1 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x18 (Slot 5) */ /* IDSEL 0x18 (Slot 5) */
0c000 0 0 1 &mpic 0 1 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
0c000 0 0 2 &mpic 1 1 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
0c000 0 0 3 &mpic 2 1 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
0c000 0 0 4 &mpic 3 1 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x1C (Tsi310 bridge PCI primary) */ /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
0E000 0 0 1 &mpic 0 1 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
0E000 0 0 2 &mpic 1 1 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
0E000 0 0 3 &mpic 2 1 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
0E000 0 0 4 &mpic 3 1>; 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <18 2>; interrupts = <24 2>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 10000000 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
01000000 0 00000000 e2000000 0 00800000>; 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
clock-frequency = <3f940aa>; clock-frequency = <66666666>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <e0008000 1000>; reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
pci_bridge@1c { pci_bridge@1c {
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x00 (PrPMC Site) */ /* IDSEL 0x00 (PrPMC Site) */
0000 0 0 1 &mpic 0 1 0000 0x0 0x0 0x1 &mpic 0x0 0x1
0000 0 0 2 &mpic 1 1 0000 0x0 0x0 0x2 &mpic 0x1 0x1
0000 0 0 3 &mpic 2 1 0000 0x0 0x0 0x3 &mpic 0x2 0x1
0000 0 0 4 &mpic 3 1 0000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x04 (VIA chip) */ /* IDSEL 0x04 (VIA chip) */
2000 0 0 1 &mpic 0 1 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
2000 0 0 2 &mpic 1 1 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
2000 0 0 3 &mpic 2 1 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
2000 0 0 4 &mpic 3 1 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x05 (8139) */ /* IDSEL 0x05 (8139) */
2800 0 0 1 &mpic 1 1 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
/* IDSEL 0x06 (Slot 6) */ /* IDSEL 0x06 (Slot 6) */
3000 0 0 1 &mpic 2 1 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
3000 0 0 2 &mpic 3 1 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
3000 0 0 3 &mpic 0 1 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
3000 0 0 4 &mpic 1 1 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDESL 0x07 (Slot 7) */ /* IDESL 0x07 (Slot 7) */
3800 0 0 1 &mpic 3 1 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
3800 0 0 2 &mpic 0 1 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
3800 0 0 3 &mpic 1 1 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
3800 0 0 4 &mpic 2 1>; 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
reg = <e000 0 0 0 0>; reg = <0xe000 0x0 0x0 0x0 0x0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
ranges = <02000000 0 80000000 ranges = <0x2000000 0x0 0x80000000
02000000 0 80000000 0x2000000 0x0 0x80000000
0 20000000 0x0 0x20000000
01000000 0 00000000 0x1000000 0x0 0x0
01000000 0 00000000 0x1000000 0x0 0x0
0 00080000>; 0x0 0x80000>;
clock-frequency = <1fca055>; clock-frequency = <33333333>;
isa@4 { isa@4 {
device_type = "isa"; device_type = "isa";
#interrupt-cells = <2>; #interrupt-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
#address-cells = <2>; #address-cells = <2>;
reg = <2000 0 0 0 0>; reg = <0x2000 0x0 0x0 0x0 0x0>;
ranges = <1 0 01000000 0 0 00001000>; ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
interrupt-parent = <&i8259>; interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 { i8259: interrupt-controller@20 {
interrupt-controller; interrupt-controller;
device_type = "interrupt-controller"; device_type = "interrupt-controller";
reg = <1 20 2 reg = <0x1 0x20 0x2
1 a0 2 0x1 0xa0 0x2
1 4d0 2>; 0x1 0x4d0 0x2>;
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
compatible = "chrp,iic"; compatible = "chrp,iic";
...@@ -362,7 +363,7 @@ i8259: interrupt-controller@20 { ...@@ -362,7 +363,7 @@ i8259: interrupt-controller@20 {
rtc@70 { rtc@70 {
compatible = "pnpPNP,b00"; compatible = "pnpPNP,b00";
reg = <1 70 2>; reg = <0x1 0x70 0x2>;
}; };
}; };
}; };
...@@ -370,64 +371,64 @@ rtc@70 { ...@@ -370,64 +371,64 @@ rtc@70 {
pci1: pci@e0009000 { pci1: pci@e0009000 {
cell-index = <1>; cell-index = <1>;
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x15 */ /* IDSEL 0x15 */
a800 0 0 1 &mpic b 1 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
a800 0 0 2 &mpic 1 1 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
a800 0 0 3 &mpic 2 1 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
a800 0 0 4 &mpic 3 1>; 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <19 2>; interrupts = <25 2>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
01000000 0 00000000 e2800000 0 00800000>; 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
clock-frequency = <3f940aa>; clock-frequency = <66666666>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <e0009000 1000>; reg = <0xe0009000 0x1000>;
compatible = "fsl,mpc8540-pci"; compatible = "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
}; };
pci2: pcie@e000a000 { pci2: pcie@e000a000 {
cell-index = <2>; cell-index = <2>;
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x0 (PEX) */ /* IDSEL 0x0 (PEX) */
00000 0 0 1 &mpic 0 1 00000 0x0 0x0 0x1 &mpic 0x0 0x1
00000 0 0 2 &mpic 1 1 00000 0x0 0x0 0x2 &mpic 0x1 0x1
00000 0 0 3 &mpic 2 1 00000 0x0 0x0 0x3 &mpic 0x2 0x1
00000 0 0 4 &mpic 3 1>; 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <1a 2>; interrupts = <26 2>;
bus-range = <0 ff>; bus-range = <0 255>;
ranges = <02000000 0 a0000000 a0000000 0 20000000 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
01000000 0 00000000 e3000000 0 08000000>; 0x1000000 0x0 0x0 0xe3000000 0x0 0x8000000>;
clock-frequency = <1fca055>; clock-frequency = <33333333>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <e000a000 1000>; reg = <0xe000a000 0x1000>;
compatible = "fsl,mpc8548-pcie"; compatible = "fsl,mpc8548-pcie";
device_type = "pci"; device_type = "pci";
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>; reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
device_type = "pci"; device_type = "pci";
ranges = <02000000 0 a0000000 ranges = <0x2000000 0x0 0xa0000000
02000000 0 a0000000 0x2000000 0x0 0xa0000000
0 20000000 0x0 0x20000000
01000000 0 00000000 0x1000000 0x0 0x0
01000000 0 00000000 0x1000000 0x0 0x0
0 08000000>; 0x0 0x8000000>;
}; };
}; };
}; };
arch/powerpc/boot/dts/mpc8555cds.dts
View file @ 32f960e9
/* /*
* MPC8555 CDS Device Tree Source * MPC8555 CDS Device Tree Source
* *
* Copyright 2006 Freescale Semiconductor Inc. * Copyright 2006, 2008 Freescale Semiconductor Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
* option) any later version. * option) any later version.
*/ */
/dts-v1/;
/ { / {
model = "MPC8555CDS"; model = "MPC8555CDS";
...@@ -31,11 +32,11 @@ cpus { ...@@ -31,11 +32,11 @@ cpus {
PowerPC,8555@0 { PowerPC,8555@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0x0>;
d-cache-line-size = <20>; // 32 bytes d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes i-cache-line-size = <32>; // 32 bytes
d-cache-size = <8000>; // L1, 32K d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // 33 MHz, from uboot timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot clock-frequency = <0>; // 825 MHz, from uboot
...@@ -44,31 +45,31 @@ PowerPC,8555@0 { ...@@ -44,31 +45,31 @@ PowerPC,8555@0 {
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <00000000 08000000>; // 128M at 0x0 reg = <0x0 0x8000000>; // 128M at 0x0
}; };
soc8555@e0000000 { soc8555@e0000000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
device_type = "soc"; device_type = "soc";
ranges = <0 e0000000 00100000>; ranges = <0x0 0xe0000000 0x100000>;
reg = <e0000000 00001000>; // CCSRBAR 1M reg = <0xe0000000 0x1000>; // CCSRBAR 1M
bus-frequency = <0>; bus-frequency = <0>;
memory-controller@2000 { memory-controller@2000 {
compatible = "fsl,8555-memory-controller"; compatible = "fsl,8555-memory-controller";
reg = <2000 1000>; reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <12 2>; interrupts = <18 2>;
}; };
l2-cache-controller@20000 { l2-cache-controller@20000 {
compatible = "fsl,8555-l2-cache-controller"; compatible = "fsl,8555-l2-cache-controller";
reg = <20000 1000>; reg = <0x20000 0x1000>;
cache-line-size = <20>; // 32 bytes cache-line-size = <32>; // 32 bytes
cache-size = <40000>; // L2, 256K cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <10 2>; interrupts = <16 2>;
}; };
i2c@3000 { i2c@3000 {
...@@ -76,8 +77,8 @@ i2c@3000 { ...@@ -76,8 +77,8 @@ i2c@3000 {
#size-cells = <0>; #size-cells = <0>;
cell-index = <0>; cell-index = <0>;
compatible = "fsl-i2c"; compatible = "fsl-i2c";
reg = <3000 100>; reg = <0x3000 0x100>;
interrupts = <2b 2>; interrupts = <43 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
dfsrr; dfsrr;
}; };
...@@ -86,18 +87,18 @@ mdio@24520 { ...@@ -86,18 +87,18 @@ mdio@24520 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,gianfar-mdio"; compatible = "fsl,gianfar-mdio";
reg = <24520 20>; reg = <0x24520 0x20>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <5 1>; interrupts = <5 1>;
reg = <0>; reg = <0x0>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <5 1>; interrupts = <5 1>;
reg = <1>; reg = <0x1>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
}; };
...@@ -107,9 +108,9 @@ enet0: ethernet@24000 { ...@@ -107,9 +108,9 @@ enet0: ethernet@24000 {
device_type = "network"; device_type = "network";
model = "TSEC"; model = "TSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <24000 1000>; reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>; interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
...@@ -119,9 +120,9 @@ enet1: ethernet@25000 { ...@@ -119,9 +120,9 @@ enet1: ethernet@25000 {
device_type = "network"; device_type = "network";
model = "TSEC"; model = "TSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <25000 1000>; reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>; interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy1>; phy-handle = <&phy1>;
}; };
...@@ -130,9 +131,9 @@ serial0: serial@4500 { ...@@ -130,9 +131,9 @@ serial0: serial@4500 {
cell-index = <0>; cell-index = <0>;
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4500 100>; // reg base, size reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot? clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>; interrupts = <42 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
...@@ -140,9 +141,9 @@ serial1: serial@4600 { ...@@ -140,9 +141,9 @@ serial1: serial@4600 {
cell-index = <1>; cell-index = <1>;
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4600 100>; // reg base, size reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot? clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>; interrupts = <42 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
...@@ -151,7 +152,7 @@ mpic: pic@40000 { ...@@ -151,7 +152,7 @@ mpic: pic@40000 {
interrupt-controller; interrupt-controller;
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
reg = <40000 40000>; reg = <0x40000 0x40000>;
compatible = "chrp,open-pic"; compatible = "chrp,open-pic";
device_type = "open-pic"; device_type = "open-pic";
big-endian; big-endian;
...@@ -161,17 +162,17 @@ cpm@919c0 { ...@@ -161,17 +162,17 @@ cpm@919c0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "fsl,mpc8555-cpm", "fsl,cpm2"; compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
reg = <919c0 30>; reg = <0x919c0 0x30>;
ranges; ranges;
muram@80000 { muram@80000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 80000 10000>; ranges = <0x0 0x80000 0x10000>;
data@0 { data@0 {
compatible = "fsl,cpm-muram-data"; compatible = "fsl,cpm-muram-data";
reg = <0 2000 9000 1000>; reg = <0x0 0x2000 0x9000 0x1000>;
}; };
}; };
...@@ -179,16 +180,16 @@ brg@919f0 { ...@@ -179,16 +180,16 @@ brg@919f0 {
compatible = "fsl,mpc8555-brg", compatible = "fsl,mpc8555-brg",
"fsl,cpm2-brg", "fsl,cpm2-brg",
"fsl,cpm-brg"; "fsl,cpm-brg";
reg = <919f0 10 915f0 10>; reg = <0x919f0 0x10 0x915f0 0x10>;
}; };
cpmpic: pic@90c00 { cpmpic: pic@90c00 {
interrupt-controller; interrupt-controller;
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupts = <2e 2>; interrupts = <46 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
reg = <90c00 80>; reg = <0x90c00 0x80>;
compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
}; };
}; };
...@@ -196,68 +197,68 @@ cpmpic: pic@90c00 { ...@@ -196,68 +197,68 @@ cpmpic: pic@90c00 {
pci0: pci@e0008000 { pci0: pci@e0008000 {
cell-index = <0>; cell-index = <0>;
interrupt-map-mask = <1f800 0 0 7>; interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x10 */ /* IDSEL 0x10 */
08000 0 0 1 &mpic 0 1 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
08000 0 0 2 &mpic 1 1 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
08000 0 0 3 &mpic 2 1 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
08000 0 0 4 &mpic 3 1 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x11 */ /* IDSEL 0x11 */
08800 0 0 1 &mpic 0 1 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
08800 0 0 2 &mpic 1 1 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
08800 0 0 3 &mpic 2 1 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
08800 0 0 4 &mpic 3 1 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x12 (Slot 1) */ /* IDSEL 0x12 (Slot 1) */
09000 0 0 1 &mpic 0 1 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
09000 0 0 2 &mpic 1 1 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
09000 0 0 3 &mpic 2 1 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
09000 0 0 4 &mpic 3 1 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x13 (Slot 2) */ /* IDSEL 0x13 (Slot 2) */
09800 0 0 1 &mpic 1 1 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
09800 0 0 2 &mpic 2 1 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
09800 0 0 3 &mpic 3 1 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
09800 0 0 4 &mpic 0 1 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
/* IDSEL 0x14 (Slot 3) */ /* IDSEL 0x14 (Slot 3) */
0a000 0 0 1 &mpic 2 1 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
0a000 0 0 2 &mpic 3 1 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
0a000 0 0 3 &mpic 0 1 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
0a000 0 0 4 &mpic 1 1 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x15 (Slot 4) */ /* IDSEL 0x15 (Slot 4) */
0a800 0 0 1 &mpic 3 1 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
0a800 0 0 2 &mpic 0 1 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
0a800 0 0 3 &mpic 1 1 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
0a800 0 0 4 &mpic 2 1 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
/* Bus 1 (Tundra Bridge) */ /* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */ /* IDSEL 0x12 (ISA bridge) */
19000 0 0 1 &mpic 0 1 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
19000 0 0 2 &mpic 1 1 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
19000 0 0 3 &mpic 2 1 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
19000 0 0 4 &mpic 3 1>; 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <18 2>; interrupts = <24 2>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
01000000 0 00000000 e2000000 0 00100000>; 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
clock-frequency = <3f940aa>; clock-frequency = <66666666>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <e0008000 1000>; reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pci"; compatible = "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
i8259@19000 { i8259@19000 {
interrupt-controller; interrupt-controller;
device_type = "interrupt-controller"; device_type = "interrupt-controller";
reg = <19000 0 0 0 1>; reg = <0x19000 0x0 0x0 0x0 0x1>;
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
compatible = "chrp,iic"; compatible = "chrp,iic";
...@@ -268,24 +269,24 @@ i8259@19000 { ...@@ -268,24 +269,24 @@ i8259@19000 {
pci1: pci@e0009000 { pci1: pci@e0009000 {
cell-index = <1>; cell-index = <1>;
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x15 */ /* IDSEL 0x15 */
a800 0 0 1 &mpic b 1 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
a800 0 0 2 &mpic b 1 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
a800 0 0 3 &mpic b 1 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
a800 0 0 4 &mpic b 1>; 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <19 2>; interrupts = <25 2>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 20000000 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
01000000 0 00000000 e3000000 0 00100000>; 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
clock-frequency = <3f940aa>; clock-frequency = <66666666>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <e0009000 1000>; reg = <0xe0009000 0x1000>;
compatible = "fsl,mpc8540-pci"; compatible = "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
}; };
......
arch/powerpc/boot/dts/mpc8560ads.dts
View file @ 32f960e9
/* /*
* MPC8560 ADS Device Tree Source * MPC8560 ADS Device Tree Source
* *
* Copyright 2006 Freescale Semiconductor Inc. * Copyright 2006, 2008 Freescale Semiconductor Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
* option) any later version. * option) any later version.
*/ */
/dts-v1/;
/ { / {
model = "MPC8560ADS"; model = "MPC8560ADS";
...@@ -32,74 +33,74 @@ cpus { ...@@ -32,74 +33,74 @@ cpus {
PowerPC,8560@0 { PowerPC,8560@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0x0>;
d-cache-line-size = <20>; // 32 bytes d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes i-cache-line-size = <32>; // 32 bytes
d-cache-size = <8000>; // L1, 32K d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <04ead9a0>; timebase-frequency = <82500000>;
bus-frequency = <13ab6680>; bus-frequency = <330000000>;
clock-frequency = <312c8040>; clock-frequency = <825000000>;
}; };
}; };
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <00000000 10000000>; reg = <0x0 0x10000000>;
}; };
soc8560@e0000000 { soc8560@e0000000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
device_type = "soc"; device_type = "soc";
ranges = <0 e0000000 00100000>; ranges = <0x0 0xe0000000 0x100000>;
reg = <e0000000 00000200>; reg = <0xe0000000 0x200>;
bus-frequency = <13ab6680>; bus-frequency = <330000000>;
memory-controller@2000 { memory-controller@2000 {
compatible = "fsl,8540-memory-controller"; compatible = "fsl,8540-memory-controller";
reg = <2000 1000>; reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <12 2>; interrupts = <18 2>;
}; };
l2-cache-controller@20000 { l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller"; compatible = "fsl,8540-l2-cache-controller";
reg = <20000 1000>; reg = <0x20000 0x1000>;
cache-line-size = <20>; // 32 bytes cache-line-size = <32>; // 32 bytes
cache-size = <40000>; // L2, 256K cache-size = <0x40000>; // L2, 256K
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <10 2>; interrupts = <16 2>;
}; };
mdio@24520 { mdio@24520 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,gianfar-mdio"; compatible = "fsl,gianfar-mdio";
reg = <24520 20>; reg = <0x24520 0x20>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <5 1>; interrupts = <5 1>;
reg = <0>; reg = <0x0>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <5 1>; interrupts = <5 1>;
reg = <1>; reg = <0x1>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
phy2: ethernet-phy@2 { phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <7 1>; interrupts = <7 1>;
reg = <2>; reg = <0x2>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
phy3: ethernet-phy@3 { phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <7 1>; interrupts = <7 1>;
reg = <3>; reg = <0x3>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
}; };
...@@ -109,9 +110,9 @@ enet0: ethernet@24000 { ...@@ -109,9 +110,9 @@ enet0: ethernet@24000 {
device_type = "network"; device_type = "network";
model = "TSEC"; model = "TSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <24000 1000>; reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>; interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
...@@ -121,9 +122,9 @@ enet1: ethernet@25000 { ...@@ -121,9 +122,9 @@ enet1: ethernet@25000 {
device_type = "network"; device_type = "network";
model = "TSEC"; model = "TSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <25000 1000>; reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>; interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy1>; phy-handle = <&phy1>;
}; };
...@@ -132,7 +133,7 @@ mpic: pic@40000 { ...@@ -132,7 +133,7 @@ mpic: pic@40000 {
interrupt-controller; interrupt-controller;
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
reg = <40000 40000>; reg = <0x40000 0x40000>;
device_type = "open-pic"; device_type = "open-pic";
}; };
...@@ -140,17 +141,17 @@ cpm@919c0 { ...@@ -140,17 +141,17 @@ cpm@919c0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "fsl,mpc8560-cpm", "fsl,cpm2"; compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
reg = <919c0 30>; reg = <0x919c0 0x30>;
ranges; ranges;
muram@80000 { muram@80000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 80000 10000>; ranges = <0x0 0x80000 0x10000>;
data@0 { data@0 {
compatible = "fsl,cpm-muram-data"; compatible = "fsl,cpm-muram-data";
reg = <0 4000 9000 2000>; reg = <0x0 0x4000 0x9000 0x2000>;
}; };
}; };
...@@ -158,17 +159,17 @@ brg@919f0 { ...@@ -158,17 +159,17 @@ brg@919f0 {
compatible = "fsl,mpc8560-brg", compatible = "fsl,mpc8560-brg",
"fsl,cpm2-brg", "fsl,cpm2-brg",
"fsl,cpm-brg"; "fsl,cpm-brg";
reg = <919f0 10 915f0 10>; reg = <0x919f0 0x10 0x915f0 0x10>;
clock-frequency = <d#165000000>; clock-frequency = <165000000>;
}; };
cpmpic: pic@90c00 { cpmpic: pic@90c00 {
interrupt-controller; interrupt-controller;
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupts = <2e 2>; interrupts = <46 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
reg = <90c00 80>; reg = <0x90c00 0x80>;
compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
}; };
...@@ -176,11 +177,11 @@ serial0: serial@91a00 { ...@@ -176,11 +177,11 @@ serial0: serial@91a00 {
device_type = "serial"; device_type = "serial";
compatible = "fsl,mpc8560-scc-uart", compatible = "fsl,mpc8560-scc-uart",
"fsl,cpm2-scc-uart"; "fsl,cpm2-scc-uart";
reg = <91a00 20 88000 100>; reg = <0x91a00 0x20 0x88000 0x100>;
fsl,cpm-brg = <1>; fsl,cpm-brg = <1>;
fsl,cpm-command = <00800000>; fsl,cpm-command = <0x800000>;
current-speed = <1c200>; current-speed = <115200>;
interrupts = <28 8>; interrupts = <40 8>;
interrupt-parent = <&cpmpic>; interrupt-parent = <&cpmpic>;
}; };
...@@ -188,11 +189,11 @@ serial1: serial@91a20 { ...@@ -188,11 +189,11 @@ serial1: serial@91a20 {
device_type = "serial"; device_type = "serial";
compatible = "fsl,mpc8560-scc-uart", compatible = "fsl,mpc8560-scc-uart",
"fsl,cpm2-scc-uart"; "fsl,cpm2-scc-uart";
reg = <91a20 20 88100 100>; reg = <0x91a20 0x20 0x88100 0x100>;
fsl,cpm-brg = <2>; fsl,cpm-brg = <2>;
fsl,cpm-command = <04a00000>; fsl,cpm-command = <0x4a00000>;
current-speed = <1c200>; current-speed = <115200>;
interrupts = <29 8>; interrupts = <41 8>;
interrupt-parent = <&cpmpic>; interrupt-parent = <&cpmpic>;
}; };
...@@ -200,10 +201,10 @@ enet2: ethernet@91320 { ...@@ -200,10 +201,10 @@ enet2: ethernet@91320 {
device_type = "network"; device_type = "network";
compatible = "fsl,mpc8560-fcc-enet", compatible = "fsl,mpc8560-fcc-enet",
"fsl,cpm2-fcc-enet"; "fsl,cpm2-fcc-enet";
reg = <91320 20 88500 100 913b0 1>; reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
fsl,cpm-command = <16200300>; fsl,cpm-command = <0x16200300>;
interrupts = <21 8>; interrupts = <33 8>;
interrupt-parent = <&cpmpic>; interrupt-parent = <&cpmpic>;
phy-handle = <&phy2>; phy-handle = <&phy2>;
}; };
...@@ -212,10 +213,10 @@ enet3: ethernet@91340 { ...@@ -212,10 +213,10 @@ enet3: ethernet@91340 {
device_type = "network"; device_type = "network";
compatible = "fsl,mpc8560-fcc-enet", compatible = "fsl,mpc8560-fcc-enet",
"fsl,cpm2-fcc-enet"; "fsl,cpm2-fcc-enet";
reg = <91340 20 88600 100 913d0 1>; reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
fsl,cpm-command = <1a400300>; fsl,cpm-command = <0x1a400300>;
interrupts = <22 8>; interrupts = <34 8>;
interrupt-parent = <&cpmpic>; interrupt-parent = <&cpmpic>;
phy-handle = <&phy3>; phy-handle = <&phy3>;
}; };
...@@ -229,87 +230,87 @@ pci0: pci@e0008000 { ...@@ -229,87 +230,87 @@ pci0: pci@e0008000 {
#address-cells = <3>; #address-cells = <3>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
reg = <e0008000 1000>; reg = <0xe0008000 0x1000>;
clock-frequency = <3f940aa>; clock-frequency = <66666666>;
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x2 */ /* IDSEL 0x2 */
1000 0 0 1 &mpic 1 1 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
1000 0 0 2 &mpic 2 1 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
1000 0 0 3 &mpic 3 1 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
1000 0 0 4 &mpic 4 1 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x3 */ /* IDSEL 0x3 */
1800 0 0 1 &mpic 4 1 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
1800 0 0 2 &mpic 1 1 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
1800 0 0 3 &mpic 2 1 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
1800 0 0 4 &mpic 3 1 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 0x4 */ /* IDSEL 0x4 */
2000 0 0 1 &mpic 3 1 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
2000 0 0 2 &mpic 4 1 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
2000 0 0 3 &mpic 1 1 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
2000 0 0 4 &mpic 2 1 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x5 */ /* IDSEL 0x5 */
2800 0 0 1 &mpic 2 1 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
2800 0 0 2 &mpic 3 1 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
2800 0 0 3 &mpic 4 1 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
2800 0 0 4 &mpic 1 1 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 12 */ /* IDSEL 12 */
6000 0 0 1 &mpic 1 1 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
6000 0 0 2 &mpic 2 1 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
6000 0 0 3 &mpic 3 1 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
6000 0 0 4 &mpic 4 1 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 13 */ /* IDSEL 13 */
6800 0 0 1 &mpic 4 1 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
6800 0 0 2 &mpic 1 1 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
6800 0 0 3 &mpic 2 1 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
6800 0 0 4 &mpic 3 1 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 14*/ /* IDSEL 14*/
7000 0 0 1 &mpic 3 1 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
7000 0 0 2 &mpic 4 1 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
7000 0 0 3 &mpic 1 1 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
7000 0 0 4 &mpic 2 1 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 15 */ /* IDSEL 15 */
7800 0 0 1 &mpic 2 1 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
7800 0 0 2 &mpic 3 1 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
7800 0 0 3 &mpic 4 1 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
7800 0 0 4 &mpic 1 1 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 18 */ /* IDSEL 18 */
9000 0 0 1 &mpic 1 1 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
9000 0 0 2 &mpic 2 1 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
9000 0 0 3 &mpic 3 1 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
9000 0 0 4 &mpic 4 1 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 19 */ /* IDSEL 19 */
9800 0 0 1 &mpic 4 1 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
9800 0 0 2 &mpic 1 1 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
9800 0 0 3 &mpic 2 1 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
9800 0 0 4 &mpic 3 1 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
/* IDSEL 20 */ /* IDSEL 20 */
a000 0 0 1 &mpic 3 1 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
a000 0 0 2 &mpic 4 1 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
a000 0 0 3 &mpic 1 1 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
a000 0 0 4 &mpic 2 1 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 21 */ /* IDSEL 21 */
a800 0 0 1 &mpic 2 1 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
a800 0 0 2 &mpic 3 1 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
a800 0 0 3 &mpic 4 1 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
a800 0 0 4 &mpic 1 1>; 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <18 2>; interrupts = <24 2>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
01000000 0 00000000 e2000000 0 01000000>; 0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>;
}; };
}; };
arch/powerpc/boot/dts/mpc8568mds.dts
View file @ 32f960e9
/* /*
* MPC8568E MDS Device Tree Source * MPC8568E MDS Device Tree Source
* *
* Copyright 2007 Freescale Semiconductor Inc. * Copyright 2007, 2008 Freescale Semiconductor Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
* option) any later version. * option) any later version.
*/ */
/dts-v1/;
/* /*
/memreserve/ 00000000 1000000; /memreserve/ 00000000 1000000;
...@@ -37,11 +38,11 @@ cpus { ...@@ -37,11 +38,11 @@ cpus {
PowerPC,8568@0 { PowerPC,8568@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0x0>;
d-cache-line-size = <20>; // 32 bytes d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes i-cache-line-size = <32>; // 32 bytes
d-cache-size = <8000>; // L1, 32K d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; timebase-frequency = <0>;
bus-frequency = <0>; bus-frequency = <0>;
clock-frequency = <0>; clock-frequency = <0>;
...@@ -50,36 +51,36 @@ PowerPC,8568@0 { ...@@ -50,36 +51,36 @@ PowerPC,8568@0 {
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <00000000 10000000>; reg = <0x0 0x10000000>;
}; };
bcsr@f8000000 { bcsr@f8000000 {
device_type = "board-control"; device_type = "board-control";
reg = <f8000000 8000>; reg = <0xf8000000 0x8000>;
}; };
soc8568@e0000000 { soc8568@e0000000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
device_type = "soc"; device_type = "soc";
ranges = <0 e0000000 00100000>; ranges = <0x0 0xe0000000 0x100000>;
reg = <e0000000 00001000>; reg = <0xe0000000 0x1000>;
bus-frequency = <0>; bus-frequency = <0>;
memory-controller@2000 { memory-controller@2000 {
compatible = "fsl,8568-memory-controller"; compatible = "fsl,8568-memory-controller";
reg = <2000 1000>; reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <12 2>; interrupts = <18 2>;
}; };
l2-cache-controller@20000 { l2-cache-controller@20000 {
compatible = "fsl,8568-l2-cache-controller"; compatible = "fsl,8568-l2-cache-controller";
reg = <20000 1000>; reg = <0x20000 0x1000>;
cache-line-size = <20>; // 32 bytes cache-line-size = <32>; // 32 bytes
cache-size = <80000>; // L2, 512K cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <10 2>; interrupts = <16 2>;
}; };
i2c@3000 { i2c@3000 {
...@@ -87,14 +88,14 @@ i2c@3000 { ...@@ -87,14 +88,14 @@ i2c@3000 {
#size-cells = <0>; #size-cells = <0>;
cell-index = <0>; cell-index = <0>;
compatible = "fsl-i2c"; compatible = "fsl-i2c";
reg = <3000 100>; reg = <0x3000 0x100>;
interrupts = <2b 2>; interrupts = <43 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
dfsrr; dfsrr;
rtc@68 { rtc@68 {
compatible = "dallas,ds1374"; compatible = "dallas,ds1374";
reg = <68>; reg = <0x68>;
}; };
}; };
...@@ -103,8 +104,8 @@ i2c@3100 { ...@@ -103,8 +104,8 @@ i2c@3100 {
#size-cells = <0>; #size-cells = <0>;
cell-index = <1>; cell-index = <1>;
compatible = "fsl-i2c"; compatible = "fsl-i2c";
reg = <3100 100>; reg = <0x3100 0x100>;
interrupts = <2b 2>; interrupts = <43 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
dfsrr; dfsrr;
}; };
...@@ -113,30 +114,30 @@ mdio@24520 { ...@@ -113,30 +114,30 @@ mdio@24520 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,gianfar-mdio"; compatible = "fsl,gianfar-mdio";
reg = <24520 20>; reg = <0x24520 0x20>;
phy0: ethernet-phy@7 { phy0: ethernet-phy@7 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <1 1>; interrupts = <1 1>;
reg = <7>; reg = <0x7>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <2 1>; interrupts = <2 1>;
reg = <1>; reg = <0x1>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
phy2: ethernet-phy@2 { phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <1 1>; interrupts = <1 1>;
reg = <2>; reg = <0x2>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
phy3: ethernet-phy@3 { phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <2 1>; interrupts = <2 1>;
reg = <3>; reg = <0x3>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
}; };
...@@ -146,9 +147,9 @@ enet0: ethernet@24000 { ...@@ -146,9 +147,9 @@ enet0: ethernet@24000 {
device_type = "network"; device_type = "network";
model = "eTSEC"; model = "eTSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <24000 1000>; reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>; interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy2>; phy-handle = <&phy2>;
}; };
...@@ -158,9 +159,9 @@ enet1: ethernet@25000 { ...@@ -158,9 +159,9 @@ enet1: ethernet@25000 {
device_type = "network"; device_type = "network";
model = "eTSEC"; model = "eTSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <25000 1000>; reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>; interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy3>; phy-handle = <&phy3>;
}; };
...@@ -169,15 +170,15 @@ serial0: serial@4500 { ...@@ -169,15 +170,15 @@ serial0: serial@4500 {
cell-index = <0>; cell-index = <0>;
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4500 100>; reg = <0x4500 0x100>;
clock-frequency = <0>; clock-frequency = <0>;
interrupts = <2a 2>; interrupts = <42 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
global-utilities@e0000 { //global utilities block global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8548-guts"; compatible = "fsl,mpc8548-guts";
reg = <e0000 1000>; reg = <0xe0000 0x1000>;
fsl,has-rstcr; fsl,has-rstcr;
}; };
...@@ -185,9 +186,9 @@ serial1: serial@4600 { ...@@ -185,9 +186,9 @@ serial1: serial@4600 {
cell-index = <1>; cell-index = <1>;
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4600 100>; reg = <0x4600 0x100>;
clock-frequency = <0>; clock-frequency = <0>;
interrupts = <2a 2>; interrupts = <42 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
...@@ -195,13 +196,13 @@ crypto@30000 { ...@@ -195,13 +196,13 @@ crypto@30000 {
device_type = "crypto"; device_type = "crypto";
model = "SEC2"; model = "SEC2";
compatible = "talitos"; compatible = "talitos";
reg = <30000 f000>; reg = <0x30000 0xf000>;
interrupts = <2d 2>; interrupts = <45 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
num-channels = <4>; num-channels = <4>;
channel-fifo-len = <18>; channel-fifo-len = <24>;
exec-units-mask = <000000fe>; exec-units-mask = <0xfe>;
descriptor-types-mask = <012b0ebf>; descriptor-types-mask = <0x12b0ebf>;
}; };
mpic: pic@40000 { mpic: pic@40000 {
...@@ -209,73 +210,73 @@ mpic: pic@40000 { ...@@ -209,73 +210,73 @@ mpic: pic@40000 {
interrupt-controller; interrupt-controller;
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
reg = <40000 40000>; reg = <0x40000 0x40000>;
compatible = "chrp,open-pic"; compatible = "chrp,open-pic";
device_type = "open-pic"; device_type = "open-pic";
big-endian; big-endian;
}; };
par_io@e0100 { par_io@e0100 {
reg = <e0100 100>; reg = <0xe0100 0x100>;
device_type = "par_io"; device_type = "par_io";
num-ports = <7>; num-ports = <7>;
pio1: ucc_pin@01 { pio1: ucc_pin@01 {
pio-map = < pio-map = <
/* port pin dir open_drain assignment has_irq */ /* port pin dir open_drain assignment has_irq */
4 0a 1 0 2 0 /* TxD0 */ 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
4 09 1 0 2 0 /* TxD1 */ 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
4 08 1 0 2 0 /* TxD2 */ 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
4 07 1 0 2 0 /* TxD3 */ 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
4 17 1 0 2 0 /* TxD4 */ 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
4 16 1 0 2 0 /* TxD5 */ 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
4 15 1 0 2 0 /* TxD6 */ 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
4 14 1 0 2 0 /* TxD7 */ 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
4 0f 2 0 2 0 /* RxD0 */ 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
4 0e 2 0 2 0 /* RxD1 */ 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
4 0d 2 0 2 0 /* RxD2 */ 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
4 0c 2 0 2 0 /* RxD3 */ 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
4 1d 2 0 2 0 /* RxD4 */ 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
4 1c 2 0 2 0 /* RxD5 */ 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
4 1b 2 0 2 0 /* RxD6 */ 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
4 1a 2 0 2 0 /* RxD7 */ 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
4 0b 1 0 2 0 /* TX_EN */ 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
4 18 1 0 2 0 /* TX_ER */ 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
4 10 2 0 2 0 /* RX_DV */ 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
4 1e 2 0 2 0 /* RX_ER */ 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
4 11 2 0 2 0 /* RX_CLK */ 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
4 13 1 0 2 0 /* GTX_CLK */ 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
1 1f 2 0 3 0>; /* GTX125 */ 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
}; };
pio2: ucc_pin@02 { pio2: ucc_pin@02 {
pio-map = < pio-map = <
/* port pin dir open_drain assignment has_irq */ /* port pin dir open_drain assignment has_irq */
5 0a 1 0 2 0 /* TxD0 */ 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
5 09 1 0 2 0 /* TxD1 */ 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
5 08 1 0 2 0 /* TxD2 */ 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
5 07 1 0 2 0 /* TxD3 */ 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
5 17 1 0 2 0 /* TxD4 */ 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
5 16 1 0 2 0 /* TxD5 */ 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
5 15 1 0 2 0 /* TxD6 */ 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
5 14 1 0 2 0 /* TxD7 */ 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
5 0f 2 0 2 0 /* RxD0 */ 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
5 0e 2 0 2 0 /* RxD1 */ 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
5 0d 2 0 2 0 /* RxD2 */ 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
5 0c 2 0 2 0 /* RxD3 */ 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
5 1d 2 0 2 0 /* RxD4 */ 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
5 1c 2 0 2 0 /* RxD5 */ 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
5 1b 2 0 2 0 /* RxD6 */ 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
5 1a 2 0 2 0 /* RxD7 */ 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
5 0b 1 0 2 0 /* TX_EN */ 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
5 18 1 0 2 0 /* TX_ER */ 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
5 10 2 0 2 0 /* RX_DV */ 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
5 1e 2 0 2 0 /* RX_ER */ 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
5 11 2 0 2 0 /* RX_CLK */ 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
5 13 1 0 2 0 /* GTX_CLK */ 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
1 1f 2 0 3 0 /* GTX125 */ 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
4 06 3 0 2 0 /* MDIO */ 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
4 05 1 0 2 0>; /* MDC */ 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
}; };
}; };
}; };
...@@ -285,28 +286,28 @@ qe@e0080000 { ...@@ -285,28 +286,28 @@ qe@e0080000 {
#size-cells = <1>; #size-cells = <1>;
device_type = "qe"; device_type = "qe";
compatible = "fsl,qe"; compatible = "fsl,qe";
ranges = <0 e0080000 00040000>; ranges = <0x0 0xe0080000 0x40000>;
reg = <e0080000 480>; reg = <0xe0080000 0x480>;
brg-frequency = <0>; brg-frequency = <0>;
bus-frequency = <179A7B00>; bus-frequency = <396000000>;
muram@10000 { muram@10000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram"; compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0 00010000 0000c000>; ranges = <0x0 0x10000 0xc000>;
data-only@0 { data-only@0 {
compatible = "fsl,qe-muram-data", compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data"; "fsl,cpm-muram-data";
reg = <0 c000>; reg = <0x0 0xc000>;
}; };
}; };
spi@4c0 { spi@4c0 {
cell-index = <0>; cell-index = <0>;
compatible = "fsl,spi"; compatible = "fsl,spi";
reg = <4c0 40>; reg = <0x4c0 0x40>;
interrupts = <2>; interrupts = <2>;
interrupt-parent = <&qeic>; interrupt-parent = <&qeic>;
mode = "cpu"; mode = "cpu";
...@@ -315,7 +316,7 @@ spi@4c0 { ...@@ -315,7 +316,7 @@ spi@4c0 {
spi@500 { spi@500 {
cell-index = <1>; cell-index = <1>;
compatible = "fsl,spi"; compatible = "fsl,spi";
reg = <500 40>; reg = <0x500 0x40>;
interrupts = <1>; interrupts = <1>;
interrupt-parent = <&qeic>; interrupt-parent = <&qeic>;
mode = "cpu"; mode = "cpu";
...@@ -325,8 +326,8 @@ enet2: ucc@2000 { ...@@ -325,8 +326,8 @@ enet2: ucc@2000 {
device_type = "network"; device_type = "network";
compatible = "ucc_geth"; compatible = "ucc_geth";
cell-index = <1>; cell-index = <1>;
reg = <2000 200>; reg = <0x2000 0x200>;
interrupts = <20>; interrupts = <32>;
interrupt-parent = <&qeic>; interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none"; rx-clock-name = "none";
...@@ -340,8 +341,8 @@ enet3: ucc@3000 { ...@@ -340,8 +341,8 @@ enet3: ucc@3000 {
device_type = "network"; device_type = "network";
compatible = "ucc_geth"; compatible = "ucc_geth";
cell-index = <2>; cell-index = <2>;
reg = <3000 200>; reg = <0x3000 0x200>;
interrupts = <21>; interrupts = <33>;
interrupt-parent = <&qeic>; interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none"; rx-clock-name = "none";
...@@ -354,7 +355,7 @@ enet3: ucc@3000 { ...@@ -354,7 +355,7 @@ enet3: ucc@3000 {
mdio@2120 { mdio@2120 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <2120 18>; reg = <0x2120 0x18>;
compatible = "fsl,ucc-mdio"; compatible = "fsl,ucc-mdio";
/* These are the same PHYs as on /* These are the same PHYs as on
...@@ -362,25 +363,25 @@ mdio@2120 { ...@@ -362,25 +363,25 @@ mdio@2120 {
qe_phy0: ethernet-phy@07 { qe_phy0: ethernet-phy@07 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <1 1>; interrupts = <1 1>;
reg = <7>; reg = <0x7>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
qe_phy1: ethernet-phy@01 { qe_phy1: ethernet-phy@01 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <2 1>; interrupts = <2 1>;
reg = <1>; reg = <0x1>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
qe_phy2: ethernet-phy@02 { qe_phy2: ethernet-phy@02 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <1 1>; interrupts = <1 1>;
reg = <2>; reg = <0x2>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
qe_phy3: ethernet-phy@03 { qe_phy3: ethernet-phy@03 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <2 1>; interrupts = <2 1>;
reg = <3>; reg = <0x3>;
device_type = "ethernet-phy"; device_type = "ethernet-phy";
}; };
}; };
...@@ -390,9 +391,9 @@ qeic: interrupt-controller@80 { ...@@ -390,9 +391,9 @@ qeic: interrupt-controller@80 {
compatible = "fsl,qe-ic"; compatible = "fsl,qe-ic";
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
reg = <80 80>; reg = <0x80 0x80>;
big-endian; big-endian;
interrupts = <2e 2 2e 2>; //high:30 low:30 interrupts = <46 2 46 2>; //high:30 low:30
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
...@@ -400,30 +401,30 @@ qeic: interrupt-controller@80 { ...@@ -400,30 +401,30 @@ qeic: interrupt-controller@80 {
pci0: pci@e0008000 { pci0: pci@e0008000 {
cell-index = <0>; cell-index = <0>;
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x12 AD18 */ /* IDSEL 0x12 AD18 */
9000 0 0 1 &mpic 5 1 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
9000 0 0 2 &mpic 6 1 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
9000 0 0 3 &mpic 7 1 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
9000 0 0 4 &mpic 4 1 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
/* IDSEL 0x13 AD19 */ /* IDSEL 0x13 AD19 */
9800 0 0 1 &mpic 6 1 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
9800 0 0 2 &mpic 7 1 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
9800 0 0 3 &mpic 4 1 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
9800 0 0 4 &mpic 5 1>; 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <18 2>; interrupts = <24 2>;
bus-range = <0 ff>; bus-range = <0 255>;
ranges = <02000000 0 80000000 80000000 0 20000000 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
01000000 0 00000000 e2000000 0 00800000>; 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
clock-frequency = <3f940aa>; clock-frequency = <66666666>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <e0008000 1000>; reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pci"; compatible = "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
}; };
...@@ -431,39 +432,39 @@ pci0: pci@e0008000 { ...@@ -431,39 +432,39 @@ pci0: pci@e0008000 {
/* PCI Express */ /* PCI Express */
pci1: pcie@e000a000 { pci1: pcie@e000a000 {
cell-index = <2>; cell-index = <2>;
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x0 (PEX) */ /* IDSEL 0x0 (PEX) */
00000 0 0 1 &mpic 0 1 00000 0x0 0x0 0x1 &mpic 0x0 0x1
00000 0 0 2 &mpic 1 1 00000 0x0 0x0 0x2 &mpic 0x1 0x1
00000 0 0 3 &mpic 2 1 00000 0x0 0x0 0x3 &mpic 0x2 0x1
00000 0 0 4 &mpic 3 1>; 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <1a 2>; interrupts = <26 2>;
bus-range = <0 ff>; bus-range = <0 255>;
ranges = <02000000 0 a0000000 a0000000 0 10000000 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
01000000 0 00000000 e2800000 0 00800000>; 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
clock-frequency = <1fca055>; clock-frequency = <33333333>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <e000a000 1000>; reg = <0xe000a000 0x1000>;
compatible = "fsl,mpc8548-pcie"; compatible = "fsl,mpc8548-pcie";
device_type = "pci"; device_type = "pci";
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>; reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
device_type = "pci"; device_type = "pci";
ranges = <02000000 0 a0000000 ranges = <0x2000000 0x0 0xa0000000
02000000 0 a0000000 0x2000000 0x0 0xa0000000
0 10000000 0x0 0x10000000
01000000 0 00000000 0x1000000 0x0 0x0
01000000 0 00000000 0x1000000 0x0 0x0
0 00800000>; 0x0 0x800000>;
}; };
}; };
}; };
arch/powerpc/boot/dts/mpc8572ds.dts
View file @ 32f960e9
/* /*
* MPC8572 DS Device Tree Source * MPC8572 DS Device Tree Source
* *
* Copyright 2007 Freescale Semiconductor Inc. * Copyright 2007, 2008 Freescale Semiconductor Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
* option) any later version. * option) any later version.
*/ */
/dts-v1/;
/ { / {
model = "fsl,MPC8572DS"; model = "fsl,MPC8572DS";
compatible = "fsl,MPC8572DS"; compatible = "fsl,MPC8572DS";
...@@ -33,11 +34,11 @@ cpus { ...@@ -33,11 +34,11 @@ cpus {
PowerPC,8572@0 { PowerPC,8572@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0x0>;
d-cache-line-size = <20>; // 32 bytes d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes i-cache-line-size = <32>; // 32 bytes
d-cache-size = <8000>; // L1, 32K d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; timebase-frequency = <0>;
bus-frequency = <0>; bus-frequency = <0>;
clock-frequency = <0>; clock-frequency = <0>;
...@@ -45,11 +46,11 @@ PowerPC,8572@0 { ...@@ -45,11 +46,11 @@ PowerPC,8572@0 {
PowerPC,8572@1 { PowerPC,8572@1 {
device_type = "cpu"; device_type = "cpu";
reg = <1>; reg = <0x1>;
d-cache-line-size = <20>; // 32 bytes d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes i-cache-line-size = <32>; // 32 bytes
d-cache-size = <8000>; // L1, 32K d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; timebase-frequency = <0>;
bus-frequency = <0>; bus-frequency = <0>;
clock-frequency = <0>; clock-frequency = <0>;
...@@ -58,38 +59,38 @@ PowerPC,8572@1 { ...@@ -58,38 +59,38 @@ PowerPC,8572@1 {
memory { memory {
device_type = "memory"; device_type = "memory";
reg = <00000000 00000000>; // Filled by U-Boot reg = <0x0 0x0>; // Filled by U-Boot
}; };
soc8572@ffe00000 { soc8572@ffe00000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
device_type = "soc"; device_type = "soc";
ranges = <00000000 ffe00000 00100000>; ranges = <0x0 0xffe00000 0x100000>;
reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
bus-frequency = <0>; // Filled out by uboot. bus-frequency = <0>; // Filled out by uboot.
memory-controller@2000 { memory-controller@2000 {
compatible = "fsl,mpc8572-memory-controller"; compatible = "fsl,mpc8572-memory-controller";
reg = <2000 1000>; reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <12 2>; interrupts = <18 2>;
}; };
memory-controller@6000 { memory-controller@6000 {
compatible = "fsl,mpc8572-memory-controller"; compatible = "fsl,mpc8572-memory-controller";
reg = <6000 1000>; reg = <0x6000 0x1000>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <12 2>; interrupts = <18 2>;
}; };
l2-cache-controller@20000 { l2-cache-controller@20000 {
compatible = "fsl,mpc8572-l2-cache-controller"; compatible = "fsl,mpc8572-l2-cache-controller";
reg = <20000 1000>; reg = <0x20000 0x1000>;
cache-line-size = <20>; // 32 bytes cache-line-size = <32>; // 32 bytes
cache-size = <80000>; // L2, 512K cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <10 2>; interrupts = <16 2>;
}; };
i2c@3000 { i2c@3000 {
...@@ -97,8 +98,8 @@ i2c@3000 { ...@@ -97,8 +98,8 @@ i2c@3000 {
#size-cells = <0>; #size-cells = <0>;
cell-index = <0>; cell-index = <0>;
compatible = "fsl-i2c"; compatible = "fsl-i2c";
reg = <3000 100>; reg = <0x3000 0x100>;
interrupts = <2b 2>; interrupts = <43 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
dfsrr; dfsrr;
}; };
...@@ -108,8 +109,8 @@ i2c@3100 { ...@@ -108,8 +109,8 @@ i2c@3100 {
#size-cells = <0>; #size-cells = <0>;
cell-index = <1>; cell-index = <1>;
compatible = "fsl-i2c"; compatible = "fsl-i2c";
reg = <3100 100>; reg = <0x3100 0x100>;
interrupts = <2b 2>; interrupts = <43 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
dfsrr; dfsrr;
}; };
...@@ -118,27 +119,27 @@ mdio@24520 { ...@@ -118,27 +119,27 @@ mdio@24520 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,gianfar-mdio"; compatible = "fsl,gianfar-mdio";
reg = <24520 20>; reg = <0x24520 0x20>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <a 1>; interrupts = <10 1>;
reg = <0>; reg = <0x0>;
}; };
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <a 1>; interrupts = <10 1>;
reg = <1>; reg = <0x1>;
}; };
phy2: ethernet-phy@2 { phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <a 1>; interrupts = <10 1>;
reg = <2>; reg = <0x2>;
}; };
phy3: ethernet-phy@3 { phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <a 1>; interrupts = <10 1>;
reg = <3>; reg = <0x3>;
}; };
}; };
...@@ -147,9 +148,9 @@ enet0: ethernet@24000 { ...@@ -147,9 +148,9 @@ enet0: ethernet@24000 {
device_type = "network"; device_type = "network";
model = "eTSEC"; model = "eTSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <24000 1000>; reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1d 2 1e 2 22 2>; interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
...@@ -160,9 +161,9 @@ enet1: ethernet@25000 { ...@@ -160,9 +161,9 @@ enet1: ethernet@25000 {
device_type = "network"; device_type = "network";
model = "eTSEC"; model = "eTSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <25000 1000>; reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 2 24 2 28 2>; interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy1>; phy-handle = <&phy1>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
...@@ -173,9 +174,9 @@ enet2: ethernet@26000 { ...@@ -173,9 +174,9 @@ enet2: ethernet@26000 {
device_type = "network"; device_type = "network";
model = "eTSEC"; model = "eTSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <26000 1000>; reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1f 2 20 2 21 2>; interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy2>; phy-handle = <&phy2>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
...@@ -186,9 +187,9 @@ enet3: ethernet@27000 { ...@@ -186,9 +187,9 @@ enet3: ethernet@27000 {
device_type = "network"; device_type = "network";
model = "eTSEC"; model = "eTSEC";
compatible = "gianfar"; compatible = "gianfar";
reg = <27000 1000>; reg = <0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <25 2 26 2 27 2>; interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
phy-handle = <&phy3>; phy-handle = <&phy3>;
phy-connection-type = "rgmii-id"; phy-connection-type = "rgmii-id";
...@@ -198,9 +199,9 @@ serial0: serial@4500 { ...@@ -198,9 +199,9 @@ serial0: serial@4500 {
cell-index = <0>; cell-index = <0>;
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4500 100>; reg = <0x4500 0x100>;
clock-frequency = <0>; clock-frequency = <0>;
interrupts = <2a 2>; interrupts = <42 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
...@@ -208,15 +209,15 @@ serial1: serial@4600 { ...@@ -208,15 +209,15 @@ serial1: serial@4600 {
cell-index = <1>; cell-index = <1>;
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4600 100>; reg = <0x4600 0x100>;
clock-frequency = <0>; clock-frequency = <0>;
interrupts = <2a 2>; interrupts = <42 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
global-utilities@e0000 { //global utilities block global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8572-guts"; compatible = "fsl,mpc8572-guts";
reg = <e0000 1000>; reg = <0xe0000 0x1000>;
fsl,has-rstcr; fsl,has-rstcr;
}; };
...@@ -225,7 +226,7 @@ mpic: pic@40000 { ...@@ -225,7 +226,7 @@ mpic: pic@40000 {
interrupt-controller; interrupt-controller;
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
reg = <40000 40000>; reg = <0x40000 0x40000>;
compatible = "chrp,open-pic"; compatible = "chrp,open-pic";
device_type = "open-pic"; device_type = "open-pic";
big-endian; big-endian;
...@@ -239,167 +240,167 @@ pci0: pcie@ffe08000 { ...@@ -239,167 +240,167 @@ pci0: pcie@ffe08000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <ffe08000 1000>; reg = <0xffe08000 0x1000>;
bus-range = <0 ff>; bus-range = <0 255>;
ranges = <02000000 0 80000000 80000000 0 20000000 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
01000000 0 00000000 ffc00000 0 00010000>; 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
clock-frequency = <1fca055>; clock-frequency = <33333333>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <18 2>; interrupts = <24 2>;
interrupt-map-mask = <ff00 0 0 7>; interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x11 func 0 - PCI slot 1 */ /* IDSEL 0x11 func 0 - PCI slot 1 */
8800 0 0 1 &mpic 2 1 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
8800 0 0 2 &mpic 3 1 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
8800 0 0 3 &mpic 4 1 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
8800 0 0 4 &mpic 1 1 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 1 - PCI slot 1 */ /* IDSEL 0x11 func 1 - PCI slot 1 */
8900 0 0 1 &mpic 2 1 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
8900 0 0 2 &mpic 3 1 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
8900 0 0 3 &mpic 4 1 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
8900 0 0 4 &mpic 1 1 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 2 - PCI slot 1 */ /* IDSEL 0x11 func 2 - PCI slot 1 */
8a00 0 0 1 &mpic 2 1 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
8a00 0 0 2 &mpic 3 1 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
8a00 0 0 3 &mpic 4 1 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
8a00 0 0 4 &mpic 1 1 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 3 - PCI slot 1 */ /* IDSEL 0x11 func 3 - PCI slot 1 */
8b00 0 0 1 &mpic 2 1 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
8b00 0 0 2 &mpic 3 1 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
8b00 0 0 3 &mpic 4 1 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
8b00 0 0 4 &mpic 1 1 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 4 - PCI slot 1 */ /* IDSEL 0x11 func 4 - PCI slot 1 */
8c00 0 0 1 &mpic 2 1 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
8c00 0 0 2 &mpic 3 1 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
8c00 0 0 3 &mpic 4 1 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
8c00 0 0 4 &mpic 1 1 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 5 - PCI slot 1 */ /* IDSEL 0x11 func 5 - PCI slot 1 */
8d00 0 0 1 &mpic 2 1 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
8d00 0 0 2 &mpic 3 1 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
8d00 0 0 3 &mpic 4 1 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
8d00 0 0 4 &mpic 1 1 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 6 - PCI slot 1 */ /* IDSEL 0x11 func 6 - PCI slot 1 */
8e00 0 0 1 &mpic 2 1 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
8e00 0 0 2 &mpic 3 1 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
8e00 0 0 3 &mpic 4 1 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
8e00 0 0 4 &mpic 1 1 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 7 - PCI slot 1 */ /* IDSEL 0x11 func 7 - PCI slot 1 */
8f00 0 0 1 &mpic 2 1 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
8f00 0 0 2 &mpic 3 1 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
8f00 0 0 3 &mpic 4 1 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
8f00 0 0 4 &mpic 1 1 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x12 func 0 - PCI slot 2 */ /* IDSEL 0x12 func 0 - PCI slot 2 */
9000 0 0 1 &mpic 3 1 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
9000 0 0 2 &mpic 4 1 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
9000 0 0 3 &mpic 1 1 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
9000 0 0 4 &mpic 2 1 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 1 - PCI slot 2 */ /* IDSEL 0x12 func 1 - PCI slot 2 */
9100 0 0 1 &mpic 3 1 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
9100 0 0 2 &mpic 4 1 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
9100 0 0 3 &mpic 1 1 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
9100 0 0 4 &mpic 2 1 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 2 - PCI slot 2 */ /* IDSEL 0x12 func 2 - PCI slot 2 */
9200 0 0 1 &mpic 3 1 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
9200 0 0 2 &mpic 4 1 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
9200 0 0 3 &mpic 1 1 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
9200 0 0 4 &mpic 2 1 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 3 - PCI slot 2 */ /* IDSEL 0x12 func 3 - PCI slot 2 */
9300 0 0 1 &mpic 3 1 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
9300 0 0 2 &mpic 4 1 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
9300 0 0 3 &mpic 1 1 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
9300 0 0 4 &mpic 2 1 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 4 - PCI slot 2 */ /* IDSEL 0x12 func 4 - PCI slot 2 */
9400 0 0 1 &mpic 3 1 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
9400 0 0 2 &mpic 4 1 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
9400 0 0 3 &mpic 1 1 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
9400 0 0 4 &mpic 2 1 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 5 - PCI slot 2 */ /* IDSEL 0x12 func 5 - PCI slot 2 */
9500 0 0 1 &mpic 3 1 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
9500 0 0 2 &mpic 4 1 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
9500 0 0 3 &mpic 1 1 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
9500 0 0 4 &mpic 2 1 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 6 - PCI slot 2 */ /* IDSEL 0x12 func 6 - PCI slot 2 */
9600 0 0 1 &mpic 3 1 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
9600 0 0 2 &mpic 4 1 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
9600 0 0 3 &mpic 1 1 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
9600 0 0 4 &mpic 2 1 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 7 - PCI slot 2 */ /* IDSEL 0x12 func 7 - PCI slot 2 */
9700 0 0 1 &mpic 3 1 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
9700 0 0 2 &mpic 4 1 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
9700 0 0 3 &mpic 1 1 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
9700 0 0 4 &mpic 2 1 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
// IDSEL 0x1c USB // IDSEL 0x1c USB
e000 0 0 1 &i8259 c 2 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
e100 0 0 2 &i8259 9 2 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
e200 0 0 3 &i8259 a 2 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
e300 0 0 4 &i8259 b 2 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
// IDSEL 0x1d Audio // IDSEL 0x1d Audio
e800 0 0 1 &i8259 6 2 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
// IDSEL 0x1e Legacy // IDSEL 0x1e Legacy
f000 0 0 1 &i8259 7 2 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
f100 0 0 1 &i8259 7 2 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
// IDSEL 0x1f IDE/SATA // IDSEL 0x1f IDE/SATA
f800 0 0 1 &i8259 e 2 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
f900 0 0 1 &i8259 5 2 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
>; >;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>; reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
device_type = "pci"; device_type = "pci";
ranges = <02000000 0 80000000 ranges = <0x2000000 0x0 0x80000000
02000000 0 80000000 0x2000000 0x0 0x80000000
0 20000000 0x0 0x20000000
01000000 0 00000000 0x1000000 0x0 0x0
01000000 0 00000000 0x1000000 0x0 0x0
0 00100000>; 0x0 0x100000>;
uli1575@0 { uli1575@0 {
reg = <0 0 0 0 0>; reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
ranges = <02000000 0 80000000 ranges = <0x2000000 0x0 0x80000000
02000000 0 80000000 0x2000000 0x0 0x80000000
0 20000000 0x0 0x20000000
01000000 0 00000000 0x1000000 0x0 0x0
01000000 0 00000000 0x1000000 0x0 0x0
0 00100000>; 0x0 0x100000>;
isa@1e { isa@1e {
device_type = "isa"; device_type = "isa";
#interrupt-cells = <2>; #interrupt-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
#address-cells = <2>; #address-cells = <2>;
reg = <f000 0 0 0 0>; reg = <0xf000 0x0 0x0 0x0 0x0>;
ranges = <1 0 01000000 0 0 ranges = <0x1 0x0 0x1000000 0x0 0x0
00001000>; 0x1000>;
interrupt-parent = <&i8259>; interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 { i8259: interrupt-controller@20 {
reg = <1 20 2 reg = <0x1 0x20 0x2
1 a0 2 0x1 0xa0 0x2
1 4d0 2>; 0x1 0x4d0 0x2>;
interrupt-controller; interrupt-controller;
device_type = "interrupt-controller"; device_type = "interrupt-controller";
#address-cells = <0>; #address-cells = <0>;
...@@ -412,29 +413,29 @@ i8259: interrupt-controller@20 { ...@@ -412,29 +413,29 @@ i8259: interrupt-controller@20 {
i8042@60 { i8042@60 {
#size-cells = <0>; #size-cells = <0>;
#address-cells = <1>; #address-cells = <1>;
reg = <1 60 1 1 64 1>; reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
interrupts = <1 3 c 3>; interrupts = <1 3 12 3>;
interrupt-parent = interrupt-parent =
<&i8259>; <&i8259>;
keyboard@0 { keyboard@0 {
reg = <0>; reg = <0x0>;
compatible = "pnpPNP,303"; compatible = "pnpPNP,303";
}; };
mouse@1 { mouse@1 {
reg = <1>; reg = <0x1>;
compatible = "pnpPNP,f03"; compatible = "pnpPNP,f03";
}; };
}; };
rtc@70 { rtc@70 {
compatible = "pnpPNP,b00"; compatible = "pnpPNP,b00";
reg = <1 70 2>; reg = <0x1 0x70 0x2>;
}; };
gpio@400 { gpio@400 {
reg = <1 400 80>; reg = <0x1 0x400 0x80>;
}; };
}; };
}; };
...@@ -449,33 +450,33 @@ pci1: pcie@ffe09000 { ...@@ -449,33 +450,33 @@ pci1: pcie@ffe09000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <ffe09000 1000>; reg = <0xffe09000 0x1000>;
bus-range = <0 ff>; bus-range = <0 255>;
ranges = <02000000 0 a0000000 a0000000 0 20000000 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
01000000 0 00000000 ffc10000 0 00010000>; 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
clock-frequency = <1fca055>; clock-frequency = <33333333>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <1a 2>; interrupts = <26 2>;
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x0 */ /* IDSEL 0x0 */
0000 0 0 1 &mpic 4 1 0000 0x0 0x0 0x1 &mpic 0x4 0x1
0000 0 0 2 &mpic 5 1 0000 0x0 0x0 0x2 &mpic 0x5 0x1
0000 0 0 3 &mpic 6 1 0000 0x0 0x0 0x3 &mpic 0x6 0x1
0000 0 0 4 &mpic 7 1 0000 0x0 0x0 0x4 &mpic 0x7 0x1
>; >;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>; reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
device_type = "pci"; device_type = "pci";
ranges = <02000000 0 a0000000 ranges = <0x2000000 0x0 0xa0000000
02000000 0 a0000000 0x2000000 0x0 0xa0000000
0 20000000 0x0 0x20000000
01000000 0 00000000 0x1000000 0x0 0x0
01000000 0 00000000 0x1000000 0x0 0x0
0 00100000>; 0x0 0x100000>;
}; };
}; };
...@@ -486,33 +487,33 @@ pci2: pcie@ffe0a000 { ...@@ -486,33 +487,33 @@ pci2: pcie@ffe0a000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <ffe0a000 1000>; reg = <0xffe0a000 0x1000>;
bus-range = <0 ff>; bus-range = <0 255>;
ranges = <02000000 0 c0000000 c0000000 0 20000000 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
01000000 0 00000000 ffc20000 0 00010000>; 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
clock-frequency = <1fca055>; clock-frequency = <33333333>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <1b 2>; interrupts = <27 2>;
interrupt-map-mask = <f800 0 0 7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x0 */ /* IDSEL 0x0 */
0000 0 0 1 &mpic 0 1 0000 0x0 0x0 0x1 &mpic 0x0 0x1
0000 0 0 2 &mpic 1 1 0000 0x0 0x0 0x2 &mpic 0x1 0x1
0000 0 0 3 &mpic 2 1 0000 0x0 0x0 0x3 &mpic 0x2 0x1
0000 0 0 4 &mpic 3 1 0000 0x0 0x0 0x4 &mpic 0x3 0x1
>; >;
pcie@0 { pcie@0 {
reg = <0 0 0 0 0>; reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
device_type = "pci"; device_type = "pci";
ranges = <02000000 0 c0000000 ranges = <0x2000000 0x0 0xc0000000
02000000 0 c0000000 0x2000000 0x0 0xc0000000
0 20000000 0x0 0x20000000
01000000 0 00000000 0x1000000 0x0 0x0
01000000 0 00000000 0x1000000 0x0 0x0
0 00100000>; 0x0 0x100000>;
}; };
}; };
}; };
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